Product specification Supersedes data 1999 2000 Product specifica

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Product specification Supersedes data 1999 2000 Product specifica

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GTL16612 18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
Product specification Supersedes data 1999 2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
FEATURES
18-bit bidirectional interface Translates between GTL/GTL+ logic levels ports) tolerant LVTTL/TTL side ports) current loading when LVTTL/TTL output tied 3-State buffers Output capability: mA/-32 LVTTL/TTL side input levels control pins Power-up reset Power-up 3-State Positive edge triggered clock inputs Latch-up protection exceeds JESD78 protection exceeds 2000 JESD22-A114,
JESD22-A115 1000 JESD22-C101 ports); GTL/GTL+ side ports) LVTTL/TTL logic levels ports)
DESCRIPTION
GTL16612 high-performance BiCMOS product designed operation with compatibility This device 18-bit universal transceiver featuring non-inverting 3-State compatible outputs both send receive directions. Data flow each direction controlled output enable (OEAB OEBA), latch enable (LEAB LEBA), clock (CPAB CPBA) inputs. A-to-B data flow, device operates transparent mode when LEAB High. When LEAB Low, data latched CPAB held High logic level. LEAB Low, A-bus data stored latch/flip-flop Low-to-High transition CPAB. When OEAB Low, outputs active. When OEAB High, outputs high-impedance state. clocks controlled with clock-enable inputs (CEBA/CEAB). Data flow B-to-A similar that A-to-B uses OEBA, LEBA CPBA.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CI/O ICCZ PARAMETER Propagation delay Input capacitance (Control pins) capacitance Total supply current Outputs disabled; VI/O Outputs disabled CONDITIONS Tamb 25°C TYPICAL UNIT
ORDERING INFORMATION
PACKAGES 56-Pin Plastic TSSOP Type TEMPERATURE RANGE -40°C +85°C ORDER CODE GTL16612 NUMBER SOT364-1
2000
853-2166 23903
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
CONFIGURATION
OEAB LEAB OEBA LEBA CEAB CPAB VREF CPBA CEBA
DESCRIPTION
NUMBER 55,30 SYMBOL OEAB/OEBA CEBA/CEAB LEAB/LEBA CPAB/CPBA NAME FUNCTION A-to-B/ B-to-A Output enable input (active Low) B-to-A/A-to-B clock enable A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge)
A0-A17
Data inputs/outputs side)
B0-B17
Data inputs/outputs side)
VREF
Ground Positive supply voltage reference voltage connection
SW00485
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
LOGIC SYMBOL (Positive Logic)
OEAB
CEAB
CPAB
LEAB
LEBA
CPBA
CEBA
OEBA
other channels
SW00254
FUNCTION TABLE
INPUTS CEAB1 OEAB1 LEAB1 CPAB1 OUTPUT
Don't care High voltage level voltage level High High impedance "off state A-to-B data flow shown: B-to-A flow similar uses OEBA, LEBA, CPBA, CEBA. Output level before indicated steady-state input conditions were established. Output level before indicated steady-state input conditions were established, provided that CPAB before LEAB went Low.
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER supply voltage input diode current input voltage3 output diode current output voltage3 port port port Output High state; port Output High state; port port Tstg Current into output state port Current into output HIGH state Storage temperature range port +150 CONDITIONS RATING -0.5 +4.6 -0.5 +7.0 -0.5 +4.6 -0.5 +7.0 -0.5 +4.6 UNIT
NOTES: Stresses beyond those listed cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. performance capability high-performance integrated circuit conjunction with thermal environment create junction temperatures which detrimental reliability. maximum junction temperature this integrated circuit should exceed 150°C. input output negative voltage ratings exceeded input output clamp current ratings observed.
RECOMMENDED OPERATING CONDITIONS
RANGE LIMITS SYMBOL PARAMETER supply voltage Termination voltage GTL+ VREF reference voltage GTL+ port Input voltage Except port port HIGH-level HIGH level input voltage Except port port Tamb LOW-level level input voltage Except port HIGH-level output current LOW-level level output current port Operating free-air temperature range port port VREF+50 VREF-50 TEST CONDITIONS 1.14 1.35 0.74 1.26 1.65 0.87 1.10 UNIT
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
ELECTRICAL CHARACTERISTICS (3.3 "0.3 RANGE)
GTL16612
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp -40°C +85°C Input clamp voltage High-level High level output voltage -100 Low-level output voltage Input leakage current IOFF IHOLD IPU/PD ICCH ICCL ICCZ5 ICCH ICCL Additional supply current input pin2 B-Port Port Outputs input VCC-0.6 Other inputs 0.04 12.0 Output current Hold current outputs current, Current into output High state when Power up/down 3-State output current3 A-Port Port Outputs Disabled Outputs high VCC, 10.5 18.5 11.5 17.5 port port -140 ±100 Data pins4 port port Control pins port 0.55 ±100 port VCC-0.2 TYP1 -0.85 0.07 0.25 -1.2 UNIT
VCC; Don't care Outputs high
NOTES: typical values Tamb 25°C. This increase supply current each LVTTL input specified voltage level other than This parameter valid between with transition time msec. From transition time µsec permitted. This parameter valid Tamb 25°C only. Unused pins GND. ICCZ measured with outputs pulled pulled down ground.
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
CHARACTERISTICS PORT)
Tamb -40°C +85°C. GTL16612 Port ±0.3 VREF SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPHZ tPZL tPLZ PARAMETER LEBA LEBA CPBA CPBA OEBA OEBA OEBA OEBA WAVEFORM TYP1 GTL+ ±0.3 VREF TYP1 UNIT
NOTE: Typical values Tamb +25°C.
CHARACTERISTICS PORT)
Tamb -40°C +85°C. GTL16612 Port ±0.3 VREF SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL PARAMETER LEAB LEAB CPAB CPAB OEAB OEAB WAVEFORM TYP1 GTL+ ±0.3 VREF TYP1 UNIT
NOTE: Typical values Tamb +25°C.
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
SETUP REQUIREMENTS (3.3 ±0.3 RANGE)
GTL16612
Port: Input Tamb -40°C +85°C; VREF Port: Input VREF LIMITS SYMBOL PARAMETER WAVEFORM ±0.3 ts(H) ts(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) Setup time, High CPBA Setup time, High CPAB Hold time, High CPBA, CPAB Setup time, High LEBA, LEAB Hold time, High LEBA, LEAB Setup time, High CEAB CPAB, CEBA CPBA Hold time, High CEAB CPAB, CEBA CPBA Pulse width, High CPBA CPAB Pulse width, High LEBA LEAB UNIT
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
WAVEFORMS
ports control pins; ports mode; ports GTL+ mode.
1/fMAX VCC, whichever less OEBA VCC, whichever less
CPBA CPAB
tW(L) tPHL tW(H) tPLH
tPZH
tPHZ
SW00181
SW00223
Waveform Propagation delay, clock input output, clock pulse width, maximum clock frequency
3.0V VCC, whichever less tPLH tPHL
Waveform 3-State output enable time high level output disable time from high level
OEBA VCC, whichever less
tPZL
tPLZ
SW00176
SW00224
Waveform Propagation delay, transparent mode
Waveform 3-State output enable time level output disable time from level
OEAB VCC, whichever less
LEAB LEBA
3.0V VCC, whichever less
tW(H) tPHL tPLH tPLH tPHL
SW00177
SW00495
Waveform
Propagation delay, enable output, enable pulse width
Waveform
Output enable time open collector output with pullup
CEAB CEBA
VCC, whichever less
CPAB CPBA, LEAB LEBA
2000
tS(H) th(H) tS(L) th(L)
VCC, whichever less SW00222
Waveform Data setup hold times
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
TEST CIRCUIT
Open
D.U.T. VOUT
NEGATIVE PULSE tTHL (tF) tTLH (tR)
PULSE GENERATOR
tTLH (tR) tTHL (tF)
Test Circuit Outputs
FROM OUTPUT UNDER TEST (INCLUDES PROBE CAPACITANCE) TEST POINT
POSITIVE PULSE
Load Circuit Outputs
SWITCH POSITION
TEST tPLZ/tPZL tPLH/tPHL tPHZ/tPZH SWITCH Open
DEFINITIONS
Load resistor; CHARACTERISTICS value. Load capacitance includes probe capacitance: CHARACTERISTICS value. Termination resistance should equal ZOUT pulse generators. 74GTL16 FAMILY Amplitude
INPUT PULSE REQUIREMENTS Rep. Rate
whichever less
v2.5 v2.5
SW00255
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
TSSOP56: plastic thin shrink small outline package; leads; body width 6.1mm
SOT364-1
2000
Product specification
18-bit GTL/GTL+ LVTTL/TTL bidirectional universal translator (3-State)
GTL16612
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition This data sheet contains design target goal specifications product development. Specification change manner without notice. This data sheet contains preliminary data, supplementary data will published later date. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product. This data sheet contains final specifications. Philips Semiconductors reserves right make changes time without notice order improve design supply best possible product.
Production
Please consult most recently issued datasheet before initiating completing design.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
Disclaimers
Life support These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified. Philips Semiconductors East Arques Avenue P.O. 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 2000 rights reserved. Printed U.S.A. Date release: 06-00 Document order number: 9397-750 07217
2000

Product specification Supersedes data 1999 2000 Product specifica

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