Hardware Reference Manual Copyright 2000 Philips Semiconductors.

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Philips Semiconductors Content Protection Link Layer IEEE 1394 Reference Design Version
Hardware Reference Manual
Copyright 2000 Philips Semiconductors. rights reserved.
Philips Semiconductors Full Duplex Link Layer 1394 Reference Design version
Hardware Reference Manual
Release 2.2, October 2000. Copyright 2000, Philips Semiconductors. rights reserved.
contents this document copied duplicated form, whole part, without prior written consent from Philips Semiconductors. Philips provides information data included this document your benefit, possible entirely verify test this information circumstances, particularly information relating non-Philips manufactured products. Philips makes warranties representations relating quality, content, adequacy this information. Every effort been made ensure accuracy this manual; however, Philips assumes responsibility errors omissions this document. Philips shall liable errors incidental consequential damages connection with furnishing, performance, this manual examples herein. Philips assumes responsibility any: damage loss resulting from this manual; loss claims third parties which arise through this RDK; loss claims third parties which arise through this RDK; damage loss caused deletion data result malfunction repair. fact that IEEE 1394 marketplace dynamic environment, Philips reserves right update improve design this product without being required upgrade previously released versions. information this document subject change without notice. Product Company names trademarks registered trademarks their respective owners.
Table Contents
ABOUT THIS MANUAL. Requirements.1 OVERVIEW Functional Description Evaluation Board Features HARDWARE DESIGN
Hardware Description 3.1.1 89C51 Memory 3.1.2 Software Memory 3.1.3 Microcontroller Design 3.1.3.1 Downloading compiled program flash 89C51 MCU.5 3.1.3.2 Interrupts.7 3.1.4 Data Simulator CPLD.7 3.1.5 Evaluation Board Jumpers Switches 3.1.6 Default/Factory Switch Jumper Settings 3.1.7 Evaluation Board Headers Connectors.12 3.1.8 EPROM Socket 3.1.9 Processor Clock Oscillator 3.1.10 Isolation Barrier 3.1.11 Using Galvanic Isolation.17 3.1.11.1 Overview 3.1.11.2 Code U5.18 3.1.12 LEDs 3.1.13 Test Points.19 3.1.14 Prototyping Area 3.1.15 Power Issues.20 Troubleshooting
CUSTOMER SUPPORT GLOSSARY. BILL MATERIALS. EVALUATION BOARD SCHEMATICS.
APPENDIX APPENDIX
List Figures
Figure 2-1: Block diagram Philips 1394 Evaluation Board.2 Figure 3-1: 89C51 microcontroller memory Figure 3-2: Locations Evaluation Board Jumpers Switches Figure 3-3: Host interface interconnectivity switches.10 Figure 3-4: Host interface header.12 Figure 3-5: Link-PHY Interface Test Header.13 Figure 3-6: Interface Header Figure 3-7: interface header Figure 3-8: JTAG Interface CPLD Programming
List Tables
Table 3-1: Software Memory Table Jumper Descriptions Table Description Switches Table 3-4: LEDs Descriptions.19 Table 3-5: Test Points Labels.19 Table 3-6: Troubleshooting Problems Corrections
About This Manual
This manual technical guide hardware design implementation Philips Full Duplex Link Layer Evaluation Board. contains description major functional areas board, with explanations where required. also appends Bill Materials board, complete schematics. Please note that Link chip present this board type part numbers: PDI1394L40 Full Duplex Link, PDI1394L41 Content Protection Link chip, depending upon which purchased.
Requirements
Before reading this manual undertaking 1394 design, recommended that have understanding IEEE 1394 specifications. should also familiar with operation pin-out Link Physical Layer used this design. pin-outs available data sheets these parts, Adobe format.
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Overview
Philips Full Duplex Evaluation Board, physical component Philips Full Duplex Link Layer 1394 Reference Design version 2.2, allows test experiment with example 1394 design. This includes testing evaluating provided example software, well implementing testing user modified software that aimed specific application. complete list features Evaluation Board follows functional description block diagram.
Functional Description
Evaluation Board consists four main functional blocks. Physical Layer connected three 1394 ports, handles physical layer transactions. Physical Layer connects Link Layer which handles link layer transactions, provides means packetizing transmitting/receiving data. section, connected Link Layer contains dual Data Simulator CPLD, generation test data, headers, facilitate connections external sources sinks data (for example, digital box, camera, VCR, etc.). Finally, 8051 flash programmed microcontroller, which handles, through software, higher network layers, connects Link Layer
Data Simulator Headers Ports
8051 Microcontroller
Link Layer
Physical Layer
Figure 2-1: Block diagram Philips 1394 Evaluation Board
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Evaluation Board Features
1394 Evaluation board following features: serial interface host that allows downloading 89C51 code flash programmable board. program space (Flash within external socketed EPROM) space data. Code compiled exactly same manner, whether executed from EPROM, flash 89C51 MCU. high speed serial link 232), operating rates 9600 Kbps, between 89C51 host (D4) show active cable connections Physical Layer User (D2) which turned time wish, software debugging/testing. dual seven-segment display provide with program number which indicates current program isochronous data generator CPLD. Link chip equipped with both encryption decryption blocks Elliptical Curve Accelerator (ECA) block node authentication. alternatively, this board equipped with Link chip having features part without blocks. Physical Layer (P21) block operates from different power source than rest card, therefore powered from 1394 cable, while rest card powered. Provision also exists power entire board directly from bus. separate LED, labeled Power, shows status Physical Layer power. fully implemented isolation barrier system between Link Layer Physical Layer enabled disabled through switches This system used demonstrate single capacitor isolation proper layer power supply design.
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Hardware Design
This section contains detailed description each sub-section Evaluation Board. also contains troubleshooting section recommendations future 1394 designs, based this reference design.
Hardware Description
description each sub-section board follows.
3.1.1 89C51 Memory
89C51 memory shows location devices that accessed through 89C51. four items 89C51 memory EPROM, SRAM, CPLD, PDI1394L41 registers. layout depends whether software being executed from (EP)ROM flash 89C51 MCU. PDI1394L41 registers always mapped start beginning last external memory. this reason, only available use, even though there physically board. memory maps follows: With code from EPROM Address (hex) 0000H (data) F7FFH F800H F9FFH FA00H FDFFH FE00H FEFFH FF00H FFFFH F7FFH F800H F9FFH FA00H FDFFH FE00H FEFFH FF00H FFFFH With code from internal flash Address (hex) 0000H (data)
LINK Registers Unused CPLD Unused
EPROM (program)
LINK Registers Unused CPLD Unused
Figure 3-1: 89C51 microcontroller memory
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3.1.2 Software Memory
Address 0000H-BFFEH BFFFH C000H-F7FFH F800H-F9FFH FFF8H-FFFCH Description Code checksum Data variables Link memory Node Unique serial number, lower bits
Table 3-1: Software Memory
3.1.3 Microcontroller Design
89C51RD microcontroller section based standard 8051 design, using latch lower eight address bits. more details this standard design, refer Data Book IC20, 8051 Based Microcontrollers. However, flash programming process used 89C51 unique explained below. 3.1.3.1 Downloading compiled program flash 89C51 (This overview process, complete programming details User's Manual) necessary start with compiled 8051 program Intel format. This program will loaded into buffer within WINISP software; buffer contents subsequently will downloaded into 89C51 microcontroller unit board. preexisting program 89C51 must erased before re-programming done. WINISP software provides this function. Programming steps: CAUTION: Flash program mode meant used ONLY with flash programmable microcontrollers labeled 89C51RD+ 89C51RD2. Please make sure your these types before proceeding. WinISP utility that combines power in-system flash programming with user friendliness graphical interface. WinISP requires Microsoft Windows later free serial port. Following
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short tutorial demonstrate program. Prepare board, make sure micro firmly inserted into socket. using Philips board, number (upper side micro) should facing EPROM socket Visually inspect board damage missing parts. Connect serial cable board your PC's serial ports. Power board. Boot your computer, start Windows WinISP software. WinISP, select chip type, clock frequency (89C51RD+ Philips board) serial port number board connected Force micro into mode. this, Place jumper position that shorts pins 1&2. (D12) will light show program mode. Press release RESET button (S2) initiate program mode. system ready. buttons left WinISP window load Intel files, program/erase/verify part, set/reset security bits etc. After been programmed, return jumper short pins 2&3. Also, please make sure that Switch (position "ON" position code from internal flash memory. micro reset time program. Please note following remarks: Boot Vector byte used pointer program. Unless custom program present elsewhere Flash memory, this value should always programmed FCh. Program Status byte execute your program after reset. back ISP, simply continue from step status byte non-zero, microcontroller will unconditionally jump address pointed Boot Vector byte after reset. program lock bits; this will disable chip access WinISP.
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3.1.3.2 Interrupts host interface interrupt (pin from Link Layer (the PDI1394L4x), connects through switch (see section 3.1.5: Evaluation Board Jumpers Switches), 89C51 INT1 (U2-15). Since this open collector output from Link this line also pulled-up with resistor. interrupts generated Link Layer multiplexed onto this line, interrupt service routine (ISR) 89C51 determine cause interrupt.
3.1.4 Data Simulator CPLD
Data Simulator CPLD. reprogrammed perform many functions factory configured generate pseudo digital video data formats, MPEG-2, DVC. data created CPLD directed either port order transmitted IEEE 1394 bus. pseudo data actually output byte counter. count starts first byte each packet, and, depending upon which mode selected, increases until terminal count MPEG-2, DVC. terminal count each case number last byte each mode, bytes MPEG, bytes DVC. beginning next packet generated count again increments from 00h. CPLD also capable generating just clock receiving node. bank switches labeled controls most functions CPLD. CPLD also connected 8051 that certain set-ups, commands, data downloaded from 8051 into CPLD. also read CPLD. Other versions CPLD code will available Philips 1394 website downloading users; website more information this subject. CPLD Philips type PZ3128, in-system-programmable using JTAG port connector labeled J11. details setup CPLD using refer Section 3.1.5, Evaluation Board Jumpers Switches, below. CAUTION: very careful when enabling transmit function Data Simulator. Enabling transmit while Link Layer port configured receiving data damage Link Layer Data Simulator.
3.1.5 Evaluation Board Jumpers Switches
1394 Evaluation board many jumpers switches which allow change certain hardware settings. Below outline board, showing location these jumpers switches.
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Figure 3-2: Locations Evaluation Board Jumpers Switches
functions these jumpers switches follows: Item Description functions This jumper connects clock output, AV1CLK, from Data Simulator CPLD, clock input Link Layer With shunt place, Simulator will drive line (when enabled). With shunt removed, clock, Link driven external source, through (see below), link's internal clock used. This jumper connects clock output, AV2CLK, from Data Simulator CPLD clock input Link Layer With shunt place, Simulator will drive line (when enabled). With shunt removed, clock connection Link driven external source, through (see below), link's internal clock used. Link Power Jumper: Used disconnect power from link chip. This jumper controls power Physical Layer (the PDI1394P11). With shunt place, (and associated circuitry) will powered from board power supply. With shunt removed, will only receive power 1394 cable, capable supplying power, attached.
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JP10
CPLD Clock Jumper: Used disconnect clock output generated from CPLD. Microcontroller programming jumper: Used microcontroller into flash programming mode. Normal operation obtained with jumper position over pins When jumper position changed short pins together, enters flash programming mode after reset button pushed released. "1995 PHY" jumper: Physical Layer chip provided with this board PDI1394P21. This conforms 1394A standard operation. this board been fitted with which conforms ONLY 1394-1995 standard, this jumper would have been shorted (with staple), telling Link chip that fitted 1995 (only) compliant part. Isolated /Non-isolated jumper block: This jumper block jumpers required) selects whether ground power domains board directly coupled link ground power domain, isolated from link ground power domain. board shipped directly coupled (nonisolated) configuration with jumper shorting pins while other shorts pins jumper block. board isolated mode, necessary short pins Flash programming voltage selector: This jumper selects either programming voltage level programming voltage used flash program MCU. factory setting this jumper (staple) shorting pins this provides programming voltage used programming 89C51RD+ type MCUs. 89CRD2 type microcontrollers require only flash programming, that type microcontroller will jumper/staple short pins
Table Jumper Descriptions
Item
Description functions Switch this pair switches controls whether 89C51 will execute code from internal (with switch off) from external EPROM (with switch marked board). Switch this reserved. This reset button board. Pressing this button will reset 89C51, causing start executing code from internal external EPROM, depending position This button also resets Link Physical Layer IC's. These switches control connectivity Host Interface, between 89C51 Link Layer that part interface controlled external source. With switches interface fully connected. wish disconnect some host interface signals, switches off, according following diagram:
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HIFD0 HIFD1 HIFD2 HIFD3 HIFD4 HIFD5 HIFD6 HIFD7 HIFA0 HIFA1 HIFA2 HIFA3
HIFA4 HIFA5 HIFA6 HIFA7 HIFA8 HIFCS HIFWR HIFRD HIFINT /RESET HIFALE HIFMUX
DIP-12
Figure 3-3: Host interface interconnectivity switches
Once lines interest have been disconnected, control them through Host Interface Header (J2). Section 3.1.7: Evaluation Board Headers Connectors more information. These switches control status bits PC3-0. into Physical Layer Which switch controls which marked above switch, board. switch position corresponds corresponds marked board. more information these bits, associated Physical Layer documentation. Switch section this switch used. This switches sets options Data Simulator CPLD. switches marked through PS9.
Switch controls receive transmit function CPLD. When this switch (LO), device will receive mode. lines will tri-stated (except clock when When this switch (HI), CPLD will transmitting mode, will send data, synchronous with clock. When active state lighted decimal point display will indicate which port CPLD sends data; this should active transmit port Link chip. Switch selects port. Switch controls MPEG-2/DVC mode. When this switch (HI), device will transmit MPEG-2 size packets (188 bytes). When this switch (LO), device transmits packets bytes. Switch directs generated packets proper port. When this switch (HI) position, packets directed AVport1. (LO) position, packets directed Avport2. position lighted decimal point display indicates which port CPLD signal directed; left port1, right port2. Switches used select clock frequency. When these switches then clock frequency 0.125, 0.25, times clock frequency; multiply input clock respectively:
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Switch
Switch
Clock Rate Data Rate (MHz) (peak) (MB/s) 20.0 10.0 5.00 2.50
Switch used supply clock (only) receiving port when placed position while receiving (LO) position. Note, switch takes precedence over when transmit (HI) position. When active state lighted decimal point display will indicate which port receive clock directed; this should active receive port Link chip. Switch selects port. Switches used this rendition CPLD program. factory programmed CPLD fitted with program indicated this display when switch position. Switch used indicate program number CPLD. further information about CPLD options, Xilinx site Internet www.xilinx.com.
WARNING: Data Simulator CPLD transmit mode, unless Link Layer port configured transmit. Enabling CPLD's transmit mode other time damage Link Layer CPLD These switches enable disable isolation barrier between Physical Link Layer ICs. Moving switches position disables isolation barrier, moving position enables barrier, marked board. Please note that switches must same position, either OFF. more information, section 3.1.10: Isolation Barrier.
Table Description Switches
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3.1.6 Default/Factory Switch Jumper Settings
(External ROM) JP6, JP10 JP11 LOW; show program number CPLD display Jumper (Non-Mux mode) fitted with jumpers Jumper (Operate) Jumper (Non-Isolated) Open, jumper
Reset (off) (enabled) (enabled) "Not Active" (ON)
Table 3-3: Default/Factory Switch Jumper Settings
3.1.7 Evaluation Board Headers Connectors
Below description headers connectors Evaluation Board. Please Figure 3-2: Evaluation Board Jumpers/Switches determine location each. Item Description This serial connector board. 9-pin connector allows standard serial cable, null-modem cable, connect board standard serial port. Note: cable included with will allow direct connection 9-pin serial port. connect 25-pin serial port, 9-pin 25-pin adapter, included kit, used. This header connects host interface Link Layer pin-out follows:
HIFD0 HIFD1 HIFD2 HIFD3 HIFD4 HIFD5 HIFD6 HIFD7 HIFCS HIFWR HIFRD HIFD8 HIFD9 HIFD10 HIFD11 HIFD12 HIFD13 HIFD14 HIFD15
HIFA0 HIFA1 HIFA2 HIFA3 HIFA4 HIFA5 HIFA6 HIFA7 HIFA8 HIFINT /RESET HIFALE HIFWAIT HIF16BIT HIFMUX 1394MODE LNKPD HEADER 20X2
Figure 3-4: Host interface header
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(cont)
this header monitor drive host interface signals. However, drive signal, must first disconnect that signal from 8051, using and/or These 1394 cable connectors. does matter many, what order they used. However, when connecting multiple boards together, sure that loop formed (i.e. there should circular path, returning board). Link-PHY Interface Test Header. Used look signals between Link chips. pin-out follows:
3.3-PHY PHYDI0 PHYDI1 PHYDI2 PHYDI3 PHYD4 PHYD5 PHYD6 PHYD7 PHYCTLI0 PHYCTLI1 LREQI SYSCLKI
HEADER 10X2
Figure 3-5: Link-PHY Interface Test Header
This connector used supply external clock Link Layer used this purpose, shunt must removed. Otherwise, this connector used monitor clock produced Data Simulator CPLD. This header connects interface Link Layer Please note that names functions board appear side header while they refer EVEN numbered pins. pin-out follows: CAUTION: Before driving signals, must ensure that particular port Link Layer configured input transmit data 1394 bus) damaged.
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AV1D0 AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7 AV1CLK AV1ERR0 AV1VALID AV1SYNC AV1ERR1 AV1ENDPCK AV1FSYNC AV1SY AV1READY AV1EMI0 AV1EMI1
HEADER 20X2
Figure 3-6: Interface Header
This connector used supply external clock Link Layer used this purpose, shunt must removed. Otherwise, this connector used monitor clock produced Data Simulator CPLD. This header connects interface Link Layer Please note that names functions board appear side header while they refer EVEN numbered pins. pin-out follows:
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AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 AV2D6 AV2D7 AV2CLK AV2ERR0 AV2VALID AV2SYNC AV2ERR1 AV2ENDPCK AV2FSYNC AV2SY AV2READY AV2EMI0 AV2EMI1
HEADER 20X2
Figure 3-7: interface header
(cont) this header monitor drive interface signals. However, wish drive signals, using this header, must first Data Simulator (U14) high-impedance state placing switch position. This Reference Design Board equipped with data simulator CPLD that erased re-programmed In-System. JTAG interface CPLD (U14) this purpose. special cable connected between printer port J11. Using software supplied Xilinx, CPLD erased re-programmed with programs written using Philips XPLA Professional XILINX CPLD programming system. Consult Xilinx Website CPLD programming instructions.
+3.3V
HEADER
Figure 3-8: JTAG Interface CPLD Programming
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This power connector (2.0mm center positive). 12VDC, unregulated power supply (provided with kit), plugged into this connector, provides power board. 8051 microcontroller replaced with 80C654, similar microcontroller, interface microcontroller accessed through this header. marked with board; connects Port which pin. connects Port which pin.
3.1.8 EPROM Socket
socket containing EPROM. EPROM shipped with EPROM, containing loader IEEE 1394 driver. However, standard 27C512 (see schematics exact pin-out) EPROM, with access time less than used (assuming 22.118 clock oscillator frequency). different EPROM used, code must compiled, linked, loaded into EPROM that starts address 0000H.
3.1.9 Processor Clock Oscillator
standard 22.118 surface mount packaged oscillator chip. However, wish board different frequencies, replace oscillator with frequency your choice, within specified limits (3.5 24MHz). oscillator speed used, long within requirements speed grade 89C51 (currently 24MHz). Please note that different frequency used, RS232 communications function properly, unless code EPROM recompiled take into account frequency. default frequency 22.118MHz chosen since divides evenly into standard serial port speeds.
3.1.10
Isolation Barrier
isolation barrier between Link Layer Physical Layer This barrier implemented placing 0.001µF capacitor series with every line that connects Link Physical Layer switches banks labeled de-activate this barrier short circuiting these capacitors. normal mode operation board with capacitors shorted (non-isolated mode). well, when switches moved, levels pins, Link Physical that isolation barrier present, changed. Therefore, switches labeled through RESET must same position, either
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toward ACTIVE disable barrier) toward ACTIVE enable barrier). Please note: There power supply considerations when using isolation, please section ISOLATION POWER when activating isolation
3.1.11
Using Galvanic Isolation
Please note: configuring board operate Galvanic isolation mode should accomplished ONLY with board power OFF. Disconnect power supply first! This board equipped with fully isolated ground power domain which used demonstrate test full Galvanic isolation mode. ground power planes link separated, that link it's Link power plane ground plane. power ground planes located under chip associated components. ground planes tied together under switch (denoted switches). link ground planes also tied together jumper also connect ground plane nonisolated 3.3v power supply). these jumpers removed link ground planes separated resistor capacitor isolation network (100 parallel with capacitor, parallel with resistor, IEEE 1394). Please schematic diagram, page provided back this manual. This network parts located under provides ground return path signals which flow between chip. Isolated power provided means isolating converter connected means jumper which also selects output ground converter ground. complete set-up isolation will necessary move switches switches "ACTIVE" (off) position. This action removes short circuits placed across isolation capacitors link-PHY interface allows them work "high pass" circuit components (See Note 2452 more details). above steps MUST done order Galvanic isolation work; omission step will cause misoperation isolation mode could possibly cause node malfunction component damage. Please refer Application Note 2452 operation isolated mode. unsure need Galvanic isolation recommend that read introductory section that application note. change board operation back direct connect mode (factory supplied mode operation) please remove power from board reverse steps indicated above.
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3.1.11.1 Overview CPLDs (U5) board performs various decoding housekeeping functions. This CPLD PZ5032, macrocell device PLCC package. fitted socket only re-programmed device programmer. handles data transfer to/from data simulator CPLD. decodes CPLD address FE00h. also used address decoder, generate chip select read/write signals SRAM, EPROM, Link Layer 3.1.11.2 Code becomes necessary modify code please contact Philips Semiconductors applications engineering department 1394@philips.com assistance.
3.1.12
LEDs
Evaluation Board several LEDs surface, inform certain conditions events. Section 3.1.5: Evaluation Board Jumpers Switches locations LEDs. function each listed here. function each also marked board, with label that quotes below. Description function User Program This will light when user program being executed 89C51 user codes 89C51 this function. user program that been downloaded through serial port WINISP software. User This controlled port 89C51. purpose simply give feedback, used your application. logic port which default after 8051 reset, will light LED. logic will turn LED. default this flashes heartbeat pattern when running smoothly, switches "Blink Code" fatal error. "Blink Codes" documented User's Manual. Link Access This lights when 89C51 accesses Link Layer through host interface. Note: these accesses short duration, sometimes difficult flash, even though accesses taking place. Cable Active This LED, beside 89C51 socket (U2), lights when active cable plugged into three 1394 ports (J3, J5). order cable active, other must plugged into live 1394 port.
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DISP
Description function light, there must also power Physical Layer section board (see below). display Multifunctional Function depends upon which program loaded into CPLD. Section 3.1.5: Jumpers Switches more information. +3.3V This lights when 3.3V power active board. 3.3V used CPLD, Link Layer associated circuitry. 3.3V also used Physical Layer however, uses different power source (see below). This lights when power active board. used 89C51 associated circuitry This lights when Physical Layer power active 3.3V power source).
Table 3-4: LEDs Descriptions
3.1.13
Test Points
There several test points card facilitate test probe connection many Physical Layer signals. Each test point plated hole, with label. following list test points. description each signal, please associated Physical Layer documentation. Test Points TP29 Labels CLK50 TPA1+ TPA1TPB1+ TPB1TPBIAS1 TPA2+ TPA2TPB2+ U11-21 Test Points TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP30 Labels TPB2TPBIAS2 TPA3+ TPA3TPB3+ TPB3TPBIAS3 HIFWAIT P3.2 CYCLEOUT Test Points TP19 TP20 TP22 TP23 TP24 TP25 TP26 TP27 TP28 Labels LINKPD PBRST PSEN U5-38 U5-39 U10-1 U10-21 U11-1
Table 3-5: Test Points Labels
3.1.14
Prototyping Area
bottom center Evaluation Board Prototype Area. holes center grid plated, connected anything. prototyping, extra components placed, soldered, this area, connected together, other parts board, external wires.
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holes bottom rail, below center grid, labeled LINK_GND connected ground planes. They used connect components prototype area. Similarly, there three power rails, +5V, +3.3V LINK +3.3V, above center grid. Care should taken connect these holes directly ground. Also, note that LINK +3.3V rail connected same voltage regulator used power Link Layer (and +3.3V LED) Physical Layer (PHY) power. power sources available, isolated non-isolated, proper supply must used dependent upon isolation not. hole pattern shown connected unused pins Data Simulator CPLD, used inputs/outputs user defined versions CPLD program. Until that time however, these holes should remain disconnected.
3.1.15
Power Issues
1394 Evaluation Board designed with different power supplies both Link Physical layer sections. this configuration, Physical Layer section powered solely from 1394 cable, acting repeater, while 89C51 Link Layer remain unpowered. Physical Layer monitors power Link Layer (through Link Power Status pin), will repeater only, 'sees' that there power Link Layer. Unfortunately, this system multiple power supplies automatically configured. When shunt place, Physical Layer power supply driven supply. This shunt must place board fully powered from supply. shunt must removed Physical Layer powered from 1394 cable, with 89C51 Link Layer operating from supply. Physical Layer power supply also contains current limiting, self-resetting, fuse (F1). current drawn Physical Layer section, other Physical Layer sections powered from that card (through 1394 cable), goes above fuse will trip. this happens, disconnect power supplies from system, wait fuse cool down, which point fuse will reset. When re-connecting boards, ensure that there smaller load placed single Physical Layer power circuit.
Troubleshooting
Problem +3.3V LEDs light. does light. Corrective Action Check that 15V-power supply properly plugged card plugged active power source. board powered from 15V-power supply, check that shunt place JP5. not, check that 1394 cable, capable supplying power, connected ports.
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CABLE ACTIVE does light.
Communications between host computer board functioning. Code being executed from user programmed EPROM.
Check that lit. Physical Layer must have power Cable Active light. Check that 1394 cable plugged ports, that other cable plugged another active 1394 device. Check that there serial cable connected between board (J1) host computer. Check that cable being used serial cable, null modem cable. cable shipped with proper cable use. Check that EPROM fully inserted (all pins socket) that (according board markings). Check that switch (meaning External PROM). Check that when code compiled, linked, loaded into EPROM, always start address 0000H.
Table 3-6: Troubleshooting Problems Corrections
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Customer Support
Philips Semiconductors committed giving you, customer, best possible technical support. your system appears functioning incorrectly, please attempt self-diagnosis with help Troubleshooting section, Chapter Software Users Manual. still having trouble, please follow these steps before contacting technical support teams: sure read relevant sections documentation. Many times answer right there. Document problem experiencing. specific can. also useful know following: board serial number; Your operating system release version; and, applicable Settings used during software compilation Settings board jumpers switches
assistance Philips Semiconductors Link Layer Controller (PDI1394L41) Physical Layer Interface (PDI1394P11A), please contact: your local Philips sales representative send email 1394@philips.com
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Glossary
various acronyms, abbreviations, special terms used frequently this manual here defined convenient reference. 1394 fast external serial standard originally developed Apple under name FireWire. Other names this technology include I-link, Lynx. standard, cost, microprocessor; 89C51 derivative part. Audio/Video Configuration Manager Capable Complex Programmable Logic Device Digital Video from camcorder Erasable Programmable Read-Only Memory programmable logic device, macrocell programmable logic device, macrocell Philips Hardware Description Language, superset computer languages used program Field Programmable Gate Arrays Programmable Logic Devices Integrated Circuit Inter-IC, developed Philips Semiconductors used connect integrated circuits. Institute Electrical Electronic Engineers Interrupt Service Routine Light Emitting Diode Megabytes second high compression isochronous format, commonly seen satellite video cameras, players. Registers PDI1394P21 3-port physical layer interface, Mbps. Identifier link chip which handles transactions between 1394 boards. PDI1394L41 Philips Semiconductors 1394 Full Duplex Content Protection Audio/Video Link Layer Controller IEEE 1394a compliant link layer controller featuring embedded layer interface. layer designed pack unpack application data packets transmission over IEEE 1394 using isochronous data transfers. runs 49.978MHz uses 3.3V power supply. Portable Document Format Random Access Memory Reference Design high speed data storage area within CPU.
8051 CPLD EPROM PZ5032 PZ3128 PHDL
IEEE MB/s MPEG-2 PDI1394L4x
Registers
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RS-232 SRAM Win32 Win9x
Read-Only Memory standard interface connecting serial devices. Static Video Cassette Recorder Microsoft Windows developing 32-bit applications. Microsoft Windows operating system.
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Appendix Bill Materials
following original Bill Materials (BOM) board. However, reasons cost availability, some parts have been substituted during manufacturing. 1394L4x Link Evaluation Board.
Item Manufacturer Part Number Mfg. Name Part Reference Description
Vendor Vendor Part
C0805C104M5UA KEMET
ECE-V1HA220UP PANASONIC C0805C102K5RA KEMET ECUPANASONIC V1H102JCX ECUPANASONIC VIH103KBG
C1,C2,C3,C4,C6,C7,C8,C 10,C11,C12,C13,C14,C15, C16,C17,C18,C19,C20,C3 9,C40,C41,C42,C43,C44, C45,C46,C47,C48,C51,C5 9,C60, C54,
Capacitor Size 0805
Newark
92F5747
Capacitor 22uF Case Electrolytic
Digikey
PCE3194CT-ND
ECE-V1HA010R
PANASONIC
ECU-V1H220JCN PANASONIC ECE-V1AA101UP PANASONIC T491D107K010AS KEMET
ECE-V1HA100P HSMS-C650 HSMG-C650 HSMY-C650 MBRS1100T3 DL4007
PANASONIC HEWLETT PACKARD HEWLETT PACKARD HEWLETT PACKARD Motorola VISHAY LITEON RAYCHEM DELEVAN
SMD075-2 8532-30LTR
C9,C23,C24,C25,C28,C29 Capacitor, ,C30,C31,C36,C65,C66,C Size 0805 67,C69,C70,C71,C72,C73 Capacitor, 10nF Size 0805 C26,C33,C37 Capacitor Size 0805 C5,C27,C34,C38 Capacitor Case Electrolytic C32,C35 Capacitor Size 0805 Capacitor Case Electrolytic C52,C53,C58 Capacitor Case Tantalum Capacitor Case Electrolytic D1,D2,D12 Surface Mount D3,D4, GREEN Surface Mount D6,D7,D8 YELLOW Surface Mount Schottky Rectifier, 403A Case General Purpose Rectifier Case MELF Resettable Fuse ).75 hold trip L1,L2,L3 Inductor Size 8532
Newark 93F2383 DIGIKEY PCC102CGCTND Digikey PCC103BNCTND
Digikey Digikey Digikey Newark
PCE2022CT-ND PCC220CNCTND PCE2039CT-ND
Digikey Newark Newark Newark Newark Digikey
PCE2033CT-ND 06F7032 06F6955 06F7123 06F9801 1N5818MCT-ND
Digikey Digikey
SMD075CT-ND DN3230CT-ND
Philips Semiconductors 2000
Page
RC11J10K0
PHILIPS
RC02H243R
PHILIPS
RC11J1K00
PHILIPS
RC02H100R
PHILIPS
RC02H392K
PHILIPS
RC02H56R2
PHILIPS
ERJ-8ENF5.11K
PANASONIC
ERJ-8ENF6.34K
PANASONIC
RC02H1M00
PHILIPS
RC11J180R
PHILIPS
ERJ-6GEYJ430
PANASONIC
ERJ-6GEYJ2.0K ERJ-6GEYJ22K RC11J4.7KR
PANASONIC PANASONIC PHILIPS
752-18-1-223-G 219-2MST B3S-1002 219-12MST 219-5MST 219-9MST PCS-044SMU11 CY74FCT573TSO DL35 6.2V +/5% MC74HCT14AD
OMRON AUGAT CYPRESS VISHAY LITEON MOTOROLA
Resistor 1/10 watt Size 0805 R10,R37,R76,R102 Resistor 1/10 Size 0805 Resistor 1/10 Size 0805 R106 Resistor 1/10 Size 0805 R22,R23,R25,R26,R28,R2 Resistor 56.2 9,R34,R35,R38,R39,R41, 1/10 Size 0805 R24,R30,R40 Resistor 5.11 1/10 Size 0805 Resistor 6.34 1/10 Size 0805 R19,R88 Resistor 1/10 Size 0805 R57,R58,R59,R60,R61,R6 Resistor 2,R63,R64,R65,R66,R67, 1/10 Size R68,R69,R70,R71,R72 0805 R4,R5,R8,R43,R73, Resistor R108,R189 1/10 Size 0805 R20,R53,R103 Resistor 1/10 Size 0805 R3,R75,R79,R80,R86,R87 Resistor 22.0 1/10 Size 0805 Resistor, 4.7K ohm, 1/10w Size 0805 RN1,RN2 Resistor Network Dual Switch circuit Surface Mount Pushbutton Switch S3,S4,S5 SOCK SOCK P10, Switch circuit Surface Mount Switch Circuit Surface Mount Switch Circuit Surface Mount PLCC Socket Octal Latch Zener Diode Schmitt Trigger Inverter Wire Staple, inch,
R1,R9,R11,R12,R13,R31, R33, R36,R44,R45,R46,R47,R4 8,R49,R50,R51,R52,R54, R55,R56,R81 R2,R6,R7,R74,R77
Resisor 1/10 watt Size 0805
Digikey
P10.0KCCT-ND
Digikey
P243CCT-ND
Digikey
P1.00KACT-ND
Digikey
P100CCT-ND
Digikey
P392KCCT-ND
Digikey
P56.2CCT-ND
Digikey
P5.11KCCT-ND
Digikey
P6.34KCCT-ND
Digikey
P1.00MCCT-ND
Digikey
P182ACT-ND
Digikey
P432CCT-ND
Digikey Digikey Digikey
P2.0KACT-ND P22KACT-ND P4.7KACT-ND
Allied Digikey Digikey Digikey Digikey Digikey Newark
745-0760 CT2192MST-ND SW416-ND CT21912MSTND CT2195MST-ND CT2199MST-ND 91F2768
Digikey Newark Newark
ZMM5234BCTND 07F6877
MAX232ACWE CY7C195-15VC
MAXIM CYPRESS
U10,U11 SOCK production units
IC149-144-045-S5 YAMAICHI
Dual RS-232 Transceiver nsec SRAM LQFP Test Socket Philips
Digikey Future
MAX232ACWEND CY7C195-15VC
Yamaichi IC149-144-045S5 Philips PDI1394P21 3128A7VQ100C SE2833CT-ND
PDI1394P21 3128A7VQ100C SG-636PCE20.000MC2
PHILIPS XYLINX EPSON
MA-506-24.576M- EPSON LDD-A512RI LUMEX
DISP
CPLD, Macrocell, XYLINX 3volt, tolerant Digikey Oscillator Surface Mount 24.576 Crystal Digikey Dual Display Digikey Green Common Anode 0.56" DE-9 Mount Newark Socket header Digikey dual header unshrouded 1394 Connector Mount Right Angle, Flat Dual Header Unshrouded Connector Mount Right Angle Jack Dual Header Unshrouded Dual Header Unshrouded Male Power Jack Closed header shunt Digikey Digikey
SE2638CT-ND 67-1456-ND
44N8882 PTC3SFAN PTC3DFAN 53462-0611
Sullins Sullins MOLEX
J3,J4,J5
44N-8882 S1212-3-ND S2212-3-ND WM17300-ND
PTC10DFAN
Sullins
Digikey
S2212-10-ND
227161-9
J7,J9
Allied
512-2179
PTC20DFAN
Sullins
Digikey
S2212-20-ND
PTC5DFAN
Sullins
Digikey
S2212-5-ND
PJ-002A PTC2SFAN
STACK Sullins
JP2,JP3,JP5,JP6 P1,P2,P3,P4,P5,P6,P7,
Digikey Digikey Digikey
CP002A-ND S1212-2-ND
XCR503210PC44C (NOT 5032C parts) LM78L12ACZ
XYLINX
2-640362-3 LM2574M-5.0
NATIONAL SEMICONDUC SOCK NATIONAL SEMICONDUC NATIONAL SEMICONDUC SGSTHOMSON PHILIPS
PZ5032 XYLINX Macrocell CPLD, 5Volt (not 5032C) 12V, 0.1A Voltage Digikey Regulator Socket Fixed SWITCHING REGULATOR Fixed switching regulator Digikey Digikey
XCR503210PC44C LM78L12ACZND A9328-ND LM2574M-5.0ND LM2574M-3.3ND NM27C512Q90ND P89C51RD+
LM2574M-3.3
U17,
Digikey
M27C512-70XF1 P89C51RD+
nsec Digikey EPROM 80C51 Microprocessor Philips PLCC FLASH
Philips Semiconductors 2000
Page
PDI1394L41/L40 None DPS150100-P5
PHILIPS Various STACK
P23,P24,P25,P26,P27
Philips Link 6-32 screw phillips panhead Regulated Power Supply Wall mount 22.118 clock oscillator Spacer, Threaded Nylon, 6-32 thread .750"lng anti static Serial Cable male female Fire wire Cable, meter long
Philips Digikey Digikey
PDI1394L41/L40 H354-ND T924-ND
SG636PCE22.118MC2 Unknown
EPSON KEYSTONE
P18,P19,P20,P21,P22
Digikey Digikey
SE2835-ND 1903DK-ND
18548 AK131-2
ASSMANN
Digikey Digikey
SCP170-ND AE1020-ND
CFWA-66-3.3
LYNN PRODUCTS
2774-SPC
HF-0787 4N36
TECHNOLOGI MURATA
QUALITY ISO3 TECHNOLOGI P6.8KE39CAGICT GENERAL SEMICONDUC ECJ-2VB2A332K PANASONIC 9.1K RESISTOR, RESISTOR, PANASONIC PANASONIC R16,R104 R14,R105
LYNN PRODU female Newark male adapter connector DC-DC Converter Murata 3.3V Optocoupler, 4N36, Digikey Transistor output Directional Transient Absorber, 600W, 0805 capacitor 9.1K Resistor, 0805 Resistor, 0805 Digikey
CFWA-66-3.3
92N5316
HF-0787 4N36QT-ND
P6KE39CAGICT PCC1988CT-ND P9.1KACT-ND P13KACT-ND
Digikey Digikey Digikey
Appendix Evaluation Board Schematics
following pages re-printed hardware schematics Evaluation Board.
Philips Semiconductors 2000
Page
P1.[4.5] AD[7.0] A[15.0]
MCUALE AD[7.0] A[15.0]
0.1uF
P3.[4.5]
TP21
TP25
EXTROM
OSC_4
PLCC socket
0.1uF
0.1uF
external internal
DIP-2
6.2V
LIGHTS WHEN PROG POWER APPLIED CHIP MCLK
EA/VPP RESET P3.2/INT0 INT1 P3.4/T0 P3.5/T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
PGMMODE
P3.2 P3.4 P3.5
/HIFINT
HEADER ONLY WITH 80C654 EQUAL)
OPEN
HEADER
P1.0 P1.1 P1.2 OUTP1_3 P1.4 P1.5 P1.6 P1.7
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN
C51-RST
74FCT573
SOIC Address latch
/PSEN
PSEN
P1.4 P1.5 P3.4 P3.5 /PSEN
MCLK /PB-RST EXTROM
74HCT14
0.1uF /PB-RST
DS2502
OPEN
PBRST
PLCC socket
Socket PLCC44 PLCC socket
B3S-1002
ELECT
CLK0 I/OA0CLK1 I/OA1 I/OA2 I/OA3 I/OA4 I/OA5 I/OA6 I/OA7 I/OA8 I/OA9 I/OA10 I/OA11 I/OA12 I/OA13 I/OA14 I/OA15
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
0.1uF
0.1uF
OUTP1_3
OUTP1_3
I/OB15 I/OB14 I/OB13 I/OB12 I/OB11 I/OB10 I/OB9 I/OB8 I/OB7 I/OB6 I/OB5 I/OB4 I/OB3 I/OB2 I/OB1 I/OB0
/RAMCE /RAMOE /ROMOE /HIFCS /RST USR-PROG CPLD-28 CPLD-93 /CNA PGMMODE C51-RST
/RAMCE /RAMOE3 /ROMOE /HIFCS /RST USR-PROG CPLD-28 CPLD-93 /CNA
PHYPD
5032
TP18 P3.2 PROGPWR PROGPWR 0.1uF
P3.2
TP20
SHRTRST
TP24
PROGRAM JUMPER
PROGRAM OPERATE PROGRAM OPERATE
0.1uF C2GND
MAX232ACWE SOIC
0.1uF 0.1uF
C1VV+
female
DB9F
P1.0
74HCT14
PLD-R/nW
0.1uF
P1.1
74HCT14
PLD-SEL
0.1uF
THIRD ANGLE PROJECTION
NOTES: UNLESS OTHERWISE SPECIFIED. RESISTORS OHMS 0805 PACKAGE. POLORIZED CAPS ELECTROLITIC EXCEPT NOTED SCHEMATIC
CONTRACT:
Board Layout DATE ENGR APVD
PHILIPS SEMICONDUCTORS
9201 AMERICAN N.E. ALBUQUERQUE 87113 1394@PHILIPS.COM
UNLESS OTHERWISE SPECIFIED
DIMENSIONS INCHES TOLERANCE ANGLES FRACTIONS -DECIMALS .XXX+/- .010 PART SHALL FREE BURRS BROKEN EDGE FILLET SURFACE ROUGHNESS
SCHEMATIC DIAGRAM,
SIZE CAGE CODE
NEXT ASSEMBLY
USED
APPLICATION
INTERPRET DRAWING ACCORDANCE WITH MIL-STD-100 ANSI Y14.5M-1982
SCALE NONE
PH000801-103
SHEET
1394 Micro. Interface Memory
2,4,6 AD[7.0]
AD[7.0]
A[15.0]
A[15.0] /ROMOE
0.1uF
EPROM 27C256 substituted
socket
/ROMOE
Socket DIP28 27C512-70
/RAMCE /RAMOE
0.1uF
CY7C195
TP26 TP27
/RAMCE /RAMOE
SRAM Usable parts:
Cypress: CY7C195, CY7C196 Paradigm: PDM41298 IDT: IDT61298 MOTOROLA: MCM6709B
/RAMCE /RAMOE
0.1uF
CY7C195
TP28 TP29
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET
1394 Link Layer
3.3-LNK 3.3-LNK decoupling close each side
3.3-LNK
3.3-LNK
752-18-1-223-J-BK
0.1uF
0.1uF
0.1uF
0.1uF
/RESET HIFCS HIFRD HIFWR HIFA0 HIFA1 HIFA2 HIFA3 HIFA4 HIFA5 HIFA6 HIFA7 HIFA8 HIFD0 HIFD1 HIFD2 HIFD3 HIFD4 HIFD5 HIFD6 HIFD7 HIFD8 HIFD9 HIFD10 HIFD11 HIFD12 HIFD13 HIFD14 HIFD15 HIFINT
ISON
CLK50
AV1VALID
AV1ERR1 AV1ERR0 AV1VALID AV1D0 AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7
SCLK CLK50
RESETN HIF_CSN HIF_RDN HIF_WRN HIF_A0 HIF_A1 HIF_A2 HIF_A3 HIF_A4 HIF_A5 HIF_A6 HIF_A7 HIF_A8 HIF_AD0 HIF_AD1 HIF_AD2 HIF_AD3 HIF_AD4 HIF_AD5 HIF_AD6 HIF_AD7 HIF_D8 HIF_D9 HIF_D10 HIF_D11 HIF_D12 HIF_D13 HIF_D14 HIF_D15 HIF_INTN CYCLEIN CYCLEOUT HIF_ALE HIF_WAIT HIF_16BIT HIF_MUX 1394MODE RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
SYSCLK
AD[7.0]
A[8.0]
DIP-12
HIFD0 HIFD1 HIFD2 HIFD3 HIFD4 HIFD5 HIFD6 HIFD7 HIFA0 HIFA1 HIFA2 HIFA3
AV1ERR1 AV1ERR0 AV1VALID AV1D0 AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7 AV1FSYNC AV1CLK AV1SYNC AV1ENDPCK AV1SY AV1READY AV1EMI0 AV1EMI1 AV2ERR1/DATINV AV2ERR0/LTLEND AV2VALID AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 CHIP AV2D6 AV2D7 AV2FSYNC AV2CLK AV2SYNC AV2ENDPCK AV2SY AV2READY AV2EMI0 AV2EMI1 PHYD0 PHYD1 PHYD2 PHYD3 PHYD4 PHYD5 PHYD6 PHYD7 PHYCTL0 PHYCTL1 LREQ LINKON TESTPIN TESTPIN TESTPIN
AV1ERR[1.0] AV1D[7.0]
AV1FSYNC AV1CLK AV1SYNC AV1ENDPCK AV1SY AV1EMI0 AV1EMI1
AV2ERR1 AV2ERR0 AV2VALID AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 AV2D6 AV2D7
AV1READY AV2ERR1 AV2ERR0 AV2VALID
/HIFCS /HIFINT /RST
/HIFCS /HIFINT /RST
/RESET
DIP-12 3.3-LNK 1995 Apply Jumper when using 1995 test card plugged Interface Header TP19
HIFA4 HIFA5 HIFA6 HIFA7 HIFA8 HIFCS HIFWR HIFRD /RESET HIFALE HIFMUX
AV2FSYNC AV2CLK AV2ENDPCK AV2SY
AV2EMI0 AV2EMI1 PHYD0 PHYD1 PHYD2 PHYD3 PHYD4 PHYD5 PHYD6 PHYD7 PHYCTL0 PHYCTL1 LREQ
AV2D[7.0] AV2SYNC AV2READY PHYD[7.0]
phyd0
AV2EMI0 AV2EMI1
TP17
HIFALE HIFWAIT HIF16BIT HIFMUX 1394MODE LNKPD
PHYCTL[0.1] LREQ LINKON
MCUALE
PULL CHIP USING MODE JUMP ACTIVE ALE/MUX JUMP NON-MUX MODE
3.3-LNK
LINK
HIFD0 HIFD1 HIFD2 HIFD3 HIFD4 HIFD5 HIFD6 HIFD7 HIFCS HIFWR HIFRD HIFD8 HIFD9 HIFD10 HIFD11 HIFD12 HIFD13 HIFD14 HIFD15
Host Interface header
HEADER 20X2
3.3-LNK
HIFA0 HIFA1 HIFA2 HIFA3 HIFA4 HIFA5 HIFA6 HIFA7 HIFA8 HIFINT /RESET HIFALE HIFWAIT HIF16BIT HIFMUX 1394MODE LNKPD
144-pin LQFP SPACING SQUARE PACKAGE
CONN
PARTS BEARING THIS MARK REQUIRED ONLY GALVANICALLY ISOLATED DESIGNS
LINK_
CONN
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET
1394 Physical Layer
POWER SUPPLY SELECTOR ISO3V ISOLATEDV
NON-ISOLATED JUMPER ISOLATED JUMPER 3.3-PHY
+15V
3.3-PHY
3.3-PHY
3.3-LNK
Lights when cable active
+15VS
PLLVDD DVDD DVDD DVDD DVDD DVDD DVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD
/CNA ISO2 4N36
3.3VP BUSPWR /RESET PHYD7 PHYD6 PHYD5 PHYD4 C49LG C47LG PHYD3 PHYD2 PHYD1 PHYD0 PHYCTL1 PHYCTL0 /RESET LNKON SYSCLK LREQ /RESETI LNKONI LPSI SYSCLKI LREQI 3.3-PHY ISO3 4N36 PHYD7I PHYD6I PHYD5I PHYD4I C49PG C47PG PHYD3I PHYD2I PHYD1I PHYD0I PHYCTL1I PHYCTL0I
ISO1 4N36
/RESETI
R106
3.3-PHY
RESET
GREEN
TPA+ TPATPB+ TPBGND CON_1394
LREQ CTL1 CTL0
SYSCLK TPA1+ TPA1TPB1+ TPB1TPBIAS1
TPA1+
PHYD[7.0] PHYCTL[0.1]
PDI1394P21
TPA2+ TPA2TPB2+ TPB2TPBIAS2
3.3-PHY
R105
TPA+ TPATPB+ TPBGND
CON_1394
TPA+ TPATPB+ TPBGND CON_1394
LINKON SYSCLK LREQ
R104 9.1K
C/LKON
TPA0+ TPA0TPB0+ TPB0TPBIAS0
BUSPWR
ACTIVE INACTIVE Label 'ISOLATION'
R103
R108 PHYPD
ISOLATION CAPACITORS (UNDER SWITCHES
PHYCTL1 PHYCTL1I PHYD2
56.2 56.2
TPBIAS1 TPB1+ TPB1-
SHIELD
56.2 56.2
5.11K
TPA1-
PHYD1
DGND DGND DGND DGND DGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND DGND PLLGND PLLGND DGND
PHYD2I
PHYD1I
TEST1 TEST0
SYSCLK
SYSCLKI PHYD3
PHYD3I
PHYCTL0
PHYCTL0I
270pF
TPA2+
C91nF
LNKON LNKONI LREQ
LREQI
*C361nF
PHYD4 PHYD4I PHYD5I PHYD6 PHYD6I
DIP-5
3.3-PHY
6.34K
TPA2-
56.2 56.2
TPBIAS2
TPB2+ TPB2-
56.2 56.2
5.11K
PHYD0
PHYD0I
PHYD5
LPSI
24.576MHz 22pF 22pF
LQFP
270pF 3.3-PHY 56.2 56.2 5.11K
C49LG C49PG C47LG
PHYD0I PHYD1I PHYD2I PHYD3I PHYD4I PHYD5I PHYD6I PHYD7I
LPSI /RESETI
C47PG
PHYD7
PHYD7I
TPA0+ 56.2 TPA0-
TPBIAS0
TPB0+ TPB0-
56.2
10nF
0.1uF
PHYCTL0I PHYCTL1I
LREQI SYSCLKI
DECOUPLING PAIR CLOSE EACH SIDE CHIP
3.3nF
3.3-PHY
3.3-PHY
270pF PHYGND
PARTS BEARING THIS MARK REQUIRED ONLY GALVANICALLY ISOLATED DESIGNS
3.3-PHY
+15V PLACE THIS HEADER NEAR LEFT EDGE BOARD
0.1uF
0.1uF
0.1uF
0.1uF
JP11
HEAVY TRACE (0.025")
TPA1+ TPA1+
TPA1+
TPA1TPA1C
TPA1-
TPB1+ TPB1+
TPB1+
TPB1TPB1C
TPB1-
TPBIAS
TPA2+
TPA2TPA2C
TPB2+ TPB2+
TPB2+
TPB2-
TPBIAS1 TPA2+ TPBIAS1
TPA2+
TPBIA TPB2- TPBIAS2
TPBIAS2
TPA0+ TPA0+
TPA0+
TPA0TPA0C
TPA0-
TPB0+ TPB0+
TPB0+
TPB0TPB0C
TPB0-
TPBI TPBIAS0
TPBIAS0
TPA2-
TPB2-
LNKONI
CONN
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET
1394 Interface
AV2VALID AV2SYNC AV2D[7.0] AV1VALID AV1SYNC AV1D[7.0]
+3.3V
CON2
CPLDAV1CLK AV1CLK
AV1CLK 0.1uF 0.1uF 0.1uF 0.1uF AV1FSYNC
decoupling close each side. Bring proto area
+3.3V
0.1uF OSC_4
20MHz
AV1ENDPCK AV1SY
CPLD
+3.3V
AV1READY
+3.3V CLKIN
PROTO-E0 PROTO-IN1 PROTO-IN2 PROTO-IN3
(CLK0) I/O-E0/CLK1 IN2-gts PROTO-E0 PROTO-IN2 PROTO-IN1 PROTO-IN3
Locate near HEADER
prototype area.
AV1D0 AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7 AV1CLK AV1ERR0 AV1VALID AV1SYNC AV1ERR1 AV1ENDPCK AV1FSYNC AV1SY AV1READY AV1EMI0 AV1EMI1
DIP-9
AD[7.0]
RD/nWR SELECT STROBE CPLD-93 LEDMSD.a LEDMSD.b LEDMSD.c LEDMSD.d LEDMSD.e LEDMSD.f LEDMSD.g LEDMSD.dp LEDLSD.a LEDLSD.b LEDLSD.c LEDLSD.d LEDLSD.e LEDLSD.f LEDLSD.g LEDLSD.dp
+3.3V
R102 AV1D0 AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7
MACROCELL CPLD
AV1D0 AV1D1 AV1D2 AV1D3 AV1D4 AV1D5 AV1D6 AV1D7 CPLDAV1CLK AV1ERR0 AV1ERR1 AV1VALID AV1ENDPCK AV1SYNC AV1FSYNC AV1SY AV1READY AV1EMI0 AV1EMI1 AV2EMI1 AV2EMI0 AV2READY AV2SY AV2SYNC AV2FSYNC AV2ENDPCK AV2VALID AV2ERR0 AV2ERR1 CPLDAV2CLK AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 AV2D6 AV2D7 100-pin TQFP SPACING SQUARE
interface header
EVEN PINS TOWARD BOARD EDGE
HEADER 20X2 AV2READY CON2
CPLDAV2CLK
AV2SY
AD[7.0] PLD-R/nW PLD-SEL CPLD-28 CPLD-93
AV1CLK AV1ERR0 AV1ERR1 AV1VALID AV1ENDPCK AV1SYNC AV1FSYNC AV1SY AV1READY AV1EMI0 AV1EMI1 AV2EMI1 AV2EMI0 AV2READY AV2SY AV2SYNC AV2FSYNC AV2ENDPCK AV2VALID AV2ERR0 AV2ERR1 AV2CLK AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 AV2D6 AV2D7
PZ3128A-S10BP
AV2CLK
AV2CLK
AV1EMI0 AV1EMI1 AV2EMI1 AV2EMI0
AV2D0 AV2D1 AV2D2 AV2D3 AV2D4 AV2D5 AV2D6 AV2D7 AV2CLK AV2ERR0 AV2VALID AV2SYNC AV2ERR1 AV2ENDPCK AV2FSYNC AV2SY AV2READY AV2EMI0 AV2EMI1
AV2FSYNC AV2ENDPCK
interface header
EVEN PINS TOWARD BOARD EDGE
+3.3V
HEADER
HEADER 20X2
AV1ERR1 AV1ERR0 AV2ERR1 AV2ERR0
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET
+3.3V
DISP1 USR-PROG
approx
74HCT14
User program active
User
OUTP1_3
approx
LDD-A512RI
74HCT14
/HIFCS
approx
74HCT14
GREEN
Lights during Link access
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET
1394 POWER
+15VS
REGULATED
ISOLATEDV APPROX 100uF ELECT YELLOW
DL4007 10uF ELECT 0.1uF
MBRS1100T3 100uF TANT
ON/OFF
MURATA CONVERTER HFP143F05031A3 THRU HOLE PART
LIGHTS WHEN ACTIVE.
LM2574M-5.0 SHIELD 0.1uF
+3.3V +3.3V 3.3-LNK
Tranzorb ON/OFF MBRS1100T3 100uF TANT
CON2
3.3-LNK
APPROX
YELLOW
22uF ELECT
LIGHTS WHEN 3.3V ACTIVE.
LM2574M-3.3
LM78L12ACZ VOUT JP10 PROGPWR
10uF ELECT
3.3-PHY
BUSPWR CON2 22uF ELECT ON/OFF APPROX YELLOW LIGHTS WHEN ACTIVE.
MBRS1100T3 100uF TANT 3.3VP
LM2574M-3.3
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET
1394 Passive Parts
Parts that sockets
SHUNT
SHUNT
SHUNT
SHUNT
SHUNT
SHUNT
SHUNT
EPROM
SOCK
SOCK
SOCK
SOCK
P89C51RD+
PZ5032
27C512-70
PDI1394L4X
proto production units)
STAPLE
STAPLE
STAPLE
STAPLE
Power Supply
Spacers (legs)
spacer
spacer
spacer
spacer
spacer
screw 6-32
screw 6-32
screw 6-32
screw 6-32
screw 6-32
anti-static
Serial cable
Firewire cable
converter
serial
1394
25to9
PHILIPS SEMICONDUTORS CONTRACT: Board Layout ALBUQUERQUE 87113 SIZE CAGE CODE
SCALE NONE
PH000801-103
SHEET

Hardware Reference Manual Copyright 2000 Philips Semiconductors.

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