NCP4302 full featured controller driver that provide control protectio
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NCP4302 Secondary Side Synchronous Flyback Controller
NCP4302 full featured controller driver that provide control protection functions necessary implementing synchronous rectifier operation flyback converter. With NCP4302, space conscious flyback applications such Adaptors, chargers, boxes achieve significant efficiency improvements minimal extra cost. addition synchronous rectifier control, incorporates accurate TL431 type shunt regulator, current monitoring circuit optocoupler driver provide single secondary solution. NCP4302 works with type flyback topology (continuous mode, Quasi-resonant mode discontinuous mode) providing high level versatility.
SO-8 SUFFIX CASE 4302x ALYW
Self-contained Control Synchronous Rectifier CCM, DCM,
Flyback Applications Interface External Signal Mode True Secondary Zero Current Detection High Gate Drive Currents (2.5 Source/Sink) High Voltage Operation Current Sense Flexibility (MOSFET RDS(on) Resistor) Accurate Voltage Reference NCP4302A 2.55 NCP4302B 1.275 Programmable Independent Secondary Side toff Delays Maximum Frequency Operation
Reference Voltage Assembly Location Wafer Year Work Week Pb-Free Package
CONFIGURATION
SYNC/CS TRIG CATH VREF (Top View) DLYADJ
Typical Applications
Notebook Adapters Adapters Consumer Appliances such DVD, Power Over Ethernet Applications phones, Wireless Access Points) Battery Chargers This Pb-Free Device
ORDERING INFORMATION
Device NCP4302ADR2G NCP4302BDR2G Package SO-8 (Pb-Free) SO-8 (Pb-Free) Shipping 2500/Tape Reel 2500/Tape Reel
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2007
April, 2007 Rev.
Publication Order Number: NCP4302/D
NCP4302
DESCRIPTION
Number Symbol SYNC/CS Description Connected flyback winding. current this sensed used turn Synchronous Rectification MOSFET (SRFET). This also used sense zero crossing MOSFET current either using RDS(on) SRFET using external current sense resistor connected between drain SRFET flyback winding. Input direct turn-off MOSFET. Typically connected signal from primary controller (for mode) signal derived from transformer (for mode). very short propagation delay output (<50 ns). Feedback compensation TL431 shunt regulator. capability sinking opto current. Output voltage feedback through resistive divider connected this pin. Regulated 1.28 (option 2.55 (option resistive divider between power supply output ground with center point tied DLYADJ input allows independent adjustment minimum toff delay time. maximum external capacitance from this ground Return controller connected output return. Drive output external MOSFET peak drive capability, internally clamped 13.5 (Maximum) Bias voltage controller. Maximum voltage
TRIG
CATH VREF DLYADJ
MAXIMUM RATINGS
Rating Power Supply Input Current Drive Voltage Current Drive Current Source Sink Analog Logic Inputs Maximum Voltage Current Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, Reference input Current, continuous Total Power Dissipation Thermal Resistance Junction-to-Ambient Symbol VDRV IDRV -2.5 TRIG, VREF, DLYADJ SYNC/CS TJmax TSmax TLmax IREF -0.3 -0.05 °C/W Value -0.3 -0.3 Unit
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. This device series contains protection exceeds following tests: 1-8: Human Body Model 2000 Mil-Std-883, Method 3015. Machine Model Method This device contains Latch-up protection exceeds ±100 JEDEC Standard JESD78
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NCP4302
Mngt. UVLO 10.4 UVLO Dlyton toff Comparators
Reset Dominant
SYNC/CS
Dlyoff
CATH Idischarge DLYADJ toff Ramp VREF
Icharge
Cdelay
TL431
Charge Enable Discharge Enable
TRIG
Figure Block Diagram
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NCP4302
+VDC
Vout
NCP1230 PFC_Vcc
Vout
SYNC/CS LYADJ TRIG VREF CATH
Figure Typical Application
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NCP4302
ELECTRICAL CHARACTERISTICS
(VCC Sync frequency kHz, VREF (IKA mA), ohms, VTRIG GND, CDRV RDLYADJ 30.1 VDLYADJ typical values 25°C, min/max values -5°C +85°C, 150°C, unless otherwise noted) Rating Start-up Threshold Stop Threshold shutdown Hysteresis Supply current after turn-on Supply current after turn-on DRIVE OUTPUT Output voltage rise-time 10-90% output signal SYNC/ -0.5 kHz, pulse, Trig 10-90% output signal SYNC/ -0.5 kHz, pulse, Trig SYNC/CS -0.5 kHz, pulse, Trig SYNC/CS -0.5 kHz, pulse, Trig VCC(on) VCC(off) no-load pin, SYNC/CS -0.5 kHz, pulse, Trig SYNC/CS -0.5 kHz, pulse, Trig VCC(on) VCC(off) VCC(HYS) ICC1 ICC2 10.4 11.2 Test Conditions Symbol Unit
Output voltage fall-time
Output source current (Note Driver high level output voltage ISOURCE SYNC/CS -0.5 kHz, pulse, Trig
IDRV(source) VDRV(H)
Output sink current (Note Driver Output level output voltage Drive voltage internal clamp ISINK SYNC/CS -0.5 kHz, pulse, Trig SYNC/CS -0.5 kHz, pulse, Trig DRVpin VCC(off) SYNC/CS -0.5 kHz, pulse, Trig
IDRV(sink) VDRV(L)
VDRV(CLMP)
Minimum drive output voltage
VDRV(MIN)
SYNC/CS total propagation delay from SYNC/CS output SYNC/CS +0.5 -0.5 kHz, pulse, (Trig V)(Refer Drive Output specifications output signal VSYNC/CS
Zero Current Detection Current Sense Offset Voltage Zero Current Level (Note SYNC/CS Leakage current
Is(zcd) VS(ZCD)
VSYNC/CS
SCSLeakage
TRIGGER SECTION Minimum Trigger pulse duration Guaranteed Design SYNC/CS -0.5 kHz, pulse, Trig trig-pw
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NCP4302
ELECTRICAL CHARACTERISTICS
(VCC Sync frequency kHz, VREF (IKA mA), ohms, VTRIG GND, CDRV RDLYADJ 30.1 VDLYADJ typical values 25°C, min/max values -5°C +85°C, 150°C, unless otherwise noted) Rating TRIGGER SECTION Trigger Pulse Voltage Gate turn-off Propagation delay from TRIG turn-off TL431 CHARACTERISTICS Reference input voltage VREF NCP4302A +25°C -5°C +85°C Reference input voltage VREF) NCP4302B +25°C -5°C +85°C IKA= ISOURCE DVKA VCCon- VREF 1.262 1.249 IRef 1.275 0.0018 1.288 1.301 mV/V VREF SYNC/CS -0.5 kHz, pulse, Trig CDRV no-load, SYNC/CS= -0.5 kHz, pulse, Trig Vtrig Test Conditions Symbol Unit
2.525 2.499
2.55
2.575 2.60
Reference Input Current Minimum CATH current regulation Reference voltage line regulation
Off-State CATH Current Dynamic impedance maximum sink current capability ADJUSTABLE TIME DELAY time delay
IOff Isinkmax 0.62
VREF (test circuit VREF grounded) VREF, DIKA (ISOURCE SYNC/CS -0.5 kHz, pulse, Trig CDLYADJ internal 30.1 75.6 23.6 32.4 (*See schematic below) maximum capacitance from ground
ton(delay)
ton(delay) range (Note maximum minimum input voltage operating range. (Note maximum minimum input operating current into DLYADJ (Note toff time delay
ton(range) 0.45 VinDLYADJ
IinDLYADJ
SYNC/CS -0.5 kHz, pulse, Trig CDLYADJ internal 30.1 23.6 32.4 (*See schematic below)
toff(delay)
toff(delay) range (Note Guaranteed Design
toff(range)
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NCP4302
TYPICAL CHARACTERISTICS
10.6 VCC(on), VOLTAGE THRESHOLD VTRIG 10.5 VCC(off), VOLTAGE THRESHOLD 9.30 9.28 9.25 9.23 9.20 9.18 9.15 9.13 9.10 VTRIG
10.4
10.3
10.2
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure VCC(on) Threshold Junction Temperature
1.25 1.23 1.21 1.19 1.17 1.15 ICC1, SUPPLY CURRENT (mA) VTRIG VCC(HYS), SHUTDOWN
Figure VCC(off) Junction Temperature
CDRV Load
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure VCC(HYS) Junction Temperature
trise, OUTPUT VOLTAGE RISE TIME (ns) ICC2, SUPPLY CURRENT (mA) CDRV
Figure Internal Current Consumption Load Junction Temperature
CDRV
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure Internal Current Consumption with Load Junction Temperature
Figure Drive Output Rise Time Junction Temperature
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NCP4302
TYPICAL CHARACTERISTICS
tfall, OUTPUT VOLTAGE FALL TIME (ns) CDRV 10.5 VDRV(H), DRIVER OUTPUT HIGH VOLTAGE 10.0
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
VDRV(L), DRIVER OUTPUT VOLTAGE
Figure Drive Output Fall-time Junction Temperature
0.24 VDRV(clmp), DRIVE VOLTAGE INTERNAL CLAMP 0.22 0.20 0.18 0.16 0.14 0.12 0.10 13.75
Figure Driver Vout High Junction Temperature
13.50 13.25 13.00 12.75 12.50 12.25
JUNCTION TEMPERATURE (°C) VDRV(min), MINIMUM DRIVE OUTPUT VOLTAGE
JUNCTION TEMPERATURE (°C)
Figure Driver Vout Junction Temperature
7.50 7.25 7.00 6.75 6.50 6.25 6.00 5.75 5.50 tp1, PROPAGATION DELAY FROM SYNC DRIVE OUTPUT (ns) VCC(off) Load 80.0 77.5 75.0 72.5 70.0 67.5 65.0 62.5 60.0
Figure Vgate Clamp Junction Temperature
CDRV
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure VOUT(min) Junction Temperature
Figure Propagation Delay, SYNC/CS DRIVE Junction Temperature
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NCP4302
TYPICAL CHARACTERISTICS
IS(zcd), ZERO CURRENT DETECTION CURRENT (mA) VTRIG, TRIGGER PULSE VOLTAGE GATE TURN-OFF
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure Zero Current Detect Isource Junction Temperature
tp2, PROPAGATION DELAY FROM TRIG TURN-OFF(ns) VREF, REFERENCE VOLTAGE 2.60 2.58 2.55 2.53 2.50 2.48 2.45 2.43 2.40
Figure Trigger Pulse Voltage Gate Turn-off Junction Temperature
IREF
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure Propagation Delay TRIG DRIVE Off, Load Junction Temperature
IREF, REFERENCE INPUT CURRENT (nA) IKA, MINIMUM CATH CURRENT REGULATION (mA)
Figure 2.55 Reference Voltage Junction Temperature
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 2.55 Reference Input Current Junction Temperature
Figure 2.55 Reference Minimum Cathode Current Regulation Junction Temperature
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NCP4302
TYPICAL CHARACTERISTICS
Ioff, OFF-STATE CATH CURRENT (mA) 2.60 VKA, REFERENCE VOLTAGE LINE REGULATION (mV/V) 11.2 11.0
2.35
10.8 10.6 10.4 10.2
2.10
1.85
1.60
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 2.55 Reference Line Regulation Junction Temperature
ZKA, DYNAMIC IMPEDANCE (mW) VREF, REFERENCE VOLTAGE 1.30
Figure 2.55 Reference Off-State Cathode Current Junction Temperature
IREF 1.29 1.28 1.27 1.26 1.25
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 2.55 Reference Dynamic Impedance Junction Temperature
1.60 ton(delay), TIME DELAY (ms) 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 toff, TIME DELAY (ms)
Figure 1.275 Reference Voltage (Option Junction Temperature
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure Delay Junction Temperature
Figure toff Delay Junction Temperature
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NCP4302
Detailed Operating Description SYNC/CS Input
NCP4302 designed operate either standalone companion primary side controller help achieve efficient synchronous rectification flyback converter systems. high current gate driver along with fast logic circuitry provide appropriately timed drive signals synchronous MOSFET used output rectification flyback converter. With novel architecture, NCP4302 enough versatility increase synchronous rectification efficiency under operating mode without requiring much complexity.
Supply Section
NCP4302 works from available bias supply that range from 10.4 (typical). This allows direct connection output voltage many adapters such notebook adapters. result, NCP4302 simplifies circuit operation compared other devices which require specific bias power supplies (e.g. high voltage capability also unique feature designed allow operation across broader range applications. prevent gate signal from operating under inadequate bias conditions, NCP4302 features UVLO circuit that turns 10.4 (VCC rising) typical turns typical (VCC falling).
Gate Drive Section
synchronous rectification application after primary side MOSFET turned-off, current secondary flyback transformer initially flows through synchronous rectification MOSFET's internal body diode. When this occurs, drain MOSFET will -0.5 -1.0 negative with respect ground (the internal body diode) NCP4302 current sense differential amplifier will output current (typical). This current detection method used NCP4302 determine when current flowing secondary transformer Synchronous Rectification MOSFET needs turned-on. zero current detection senses current with slight negative offset that switch turn-off occurs without reversal current.
Cout Vout
Current Sense Amplifier Mirror Reset Dominant Flip-Flop
NCP4302 features high current gate drivers delivering (>2.5 peak) achieve fast turn-on turn-off requirements synchronous rectifier. Having high gate drive current enables fast turn-on when SYNC/CS signal received minimize body diode conduction peak current waveform) fast turn-off when zero current TRIG signals received prevent current reversal cross conduction). higher sink current also allows MOSFET kept during instances when there high dv/dt drain. gate voltage clamped 13.5 typical prevent larger excursion gate voltage than needed when operating from output. propagation delays through logic circuits gate drivers kept minimum shown specification table.
45.0 37.5
Figure Input Current Sense
SYNC/CS input NCP4302 used Reset (through logic) input drive enable Flip Flop; refer internal block diagram NCP4302. When current flows secondary Flyback transformer parasitic inductance printed wiring board traces, component lead cause voltage SYNC/CS input ring above ground (refer Figure 26). This ringing cause controller dive output turn-off. eliminate this problem NCP4302 programmable time which blanks secondary voltage ringing adding minimum controller drive time.
Adjustable Delay
25.0
12.5 V(U1:4) Time
Figure Discontinuous Conduction Mode Drain Waveform http://onsemi.com
NCP4302
minimum time with voltage divider with resistors (refer Figure 27).
Adjustable toff Delay
Where Thevenin equivalent resistance calculated
This input current then used charge internal capacitor setting minimum time.
on(delay)
Vout Cout SYNC/CS TRIG DLYADJ VREF CATH Rlower Rupper
SYNC/CS input NCP4302 used input drive enable Flip Flop; refer internal block diagram NCP4302. Refering SPICE simulations (Figure 28), that when system operating under light load conditions transformer secondary voltage rings below ground when current reaches zero. When this occurs, amplifier output falsely triggered providing input drive Flip Flop, turning output drive. prevent controller from prematurely turning synchronous rectification MOSFET, output current sense amplifier connected logic block with programmable time delay. toff(delay) independetly programmed through DLYADJ pin.
R2)R3
off(delay) 3.35
Figure
V(U1:4) Time
Figure Discontinuous Conduction Mode Drain Waveform Trigger Input
TRIG input used turn-off synchronous MOSFET prior current reaching zero. This input required operating mode. While there several ways determine TRIG input, simplest generate pulse primary side that precedes turn-on primary MOSFET transformer couple that pulse secondary into Trig input. converters where operating mode always designed QRM,
TRIG input used. recommended ground TRIG these cases.
Voltage Amplifier Reference
NCP4302 incorporates accurate TL431 type Shunt regulator with reference voltage options. NCP4302A reference NCP4302B 1.25 reference.
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NCP4302
Cout Rbias
Figure conducting current. NCP4302 operate CCM, CRM, modes. next sections cover losses associated each three operating modes.
Rupper
Discontinuous Conduction Mode
Rcomp Ccomp
TL431 Rlower
Figure Typical Secondary Side Regulator
When TL431 being used regulate output power supply typically configured shown Figure Where output from power supply sensed divided down with resistive divider made Rupper Rlower. center point divider connected reference NCP4302. divider ratio scales down output voltage match reference voltage, 1.25
lower lower upper
basic switching waveforms Flyback converter operating shown Figure When primary side MOSFET Figure turned-on current flows transformer primary ramps from zero Ipeak. When primary side MOSFET (SP) turns-off polarity transformer reverses energy stored transformer transferred secondary. When energy transfer from transformer primary transformer secondary begins, (prior secondary side synchronous MOSFET turning-on) secondary current flows through internal body diode synchronous rectifiers MOSFETs (SS) (SSD). minimize losses SSD, propagation delay (tp1) must low. Otherwise there will high losses associated with secondary peak current forward voltage drop (NCP4302 typical propagation delay ns).
Tsecondary diode
(eq. (eq.
Rbias resistor Figure sets current through TL431, which must greater than guarantee performance under operating conditions.
Cout Vout
(eq.
Combining
(eq.
DS(on)
(eq. (eq. (eq.
diode Iout
Figure Synchronous Rectifier Using Synchronous Rectification
Where: Iout output current duty cycle RDS(on) resistance MOSFET
flyback converter operate correctly with synchronous rectification there must delay between time when primary side MOSFET Figure secondary side Synchronous rectification MOSFETs
transformer turns ratio
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NCP4302
Discontinuous Condition Mode
Ipeak IPRM
IPRM
ISEC
ISEC
SYNC
SYNC
TRIG
Figure Discontinuous Conduction Mode Waveforms
propagation delay from SYNC/CS input drive output.
Continuous Conduction Mode
Figure Continuous Conduction Mode Waveforms Tsecondary BODY_DIODE Ipk(1
(eq. (eq. (eq.
When operating continuous conduction mode (CCM) current secondary doesn't fall zero prior turning primary side MOSFET. eliminate cross conduction losses (have primary side MOSFET secondary side MOSFET same time) trigger input NCP4302 must utilized. signal which leads Primary Side (SP) MOSFET turning must coupled TRIG input NCP4302 which will turn-off MOSFET referring Figure When energy transfer begins transformer secondary, prior secondary side synchronous MOSFET turning-on, secondary current flows through synchronous rectifiers MOSFET's (SS) internal body diode (SSD). minimize power loss internal body controller propagation delay been minimized NCP4302.
Combining
SECpk*pk DS(on) SECpk*pk out(1
BODY_DIODE Iout
recovery charge internal body diode Coss MOSFET drain source capacitance transformer primary inductance
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(eq. (eq. (eq. (eq. (eq.
(eq.
NCP4302
PACKAGE DIMENSIONS
SOIC-8 SUFFIX CASE 751-07 ISSUE
0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. 751-01 THRU 751-06 OBSOLETE. STANDARD 751-07. MILLIMETERS 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 0.10 0.25 0.19 0.25 0.40 1.27 0.25 0.50 5.80 6.20 INCHES 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 0.004 0.010 0.007 0.010 0.016 0.050 0.010 0.020 0.228 0.244
0.25 (0.010)
SEATING PLANE
0.10 (0.004)
SOLDERING FOOTPRINT*
1.52 0.060
0.275
0.155
0.024
1.270 0.050
SCALE inches
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
product described herein (NCP4302), covered following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221. There other patents pending.
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
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NCP4302/D
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