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AND8188/D Board Mounting Notes NIS6111 Leadless Package (QFN)
Introduction Various Semiconductor components packaged advanced Quad Flat-Pack No-Lead Package (QFN) commonly referred Leadless Package. Because (Leadless) platform represent latest surface mount packaging technology, important that design Printed Circuit Board (PCB), well assembly process, follow suggested guidelines outlined this document. NIS6111 Package Overview platform offers versatility, which allows either single multiple semiconductor devices connected together within leadless package. this case NIS6111 Package contains multiple semiconductor devices within package. This package style chosen excellent thermal dissipation reduced electrical parasitics. When surface mounting this package onto PCB, critical issues must considered: Printed Circuit Board Design Board Mounting Process. This document will address both these critical issues. Printed Circuit Board Design Considerations
NSMD Configurations
while pads have solder mask over edge metallization, shown Figure With Pads, solder mask restricts flow solder paste metallization which prevents solder from flowing along side metal pad. This different from NSMD configuration where solder will flow around both sides metallization.
Solder Mask Opening
Solder Mask Overlay
Solderable
NSMD
Figure Comparison NSMD Pads
There different types configurations commonly used surface mount leadless style packages. These different configurations are: Non-Solder Masked Defined (NSMD) Solder Masked Defined (SMD). their titles describe, NSMD contact pads have solder mask pulled away from solderable metallization,
Typically, NSMD pads preferred over configuration since defining location size copper easier control than solder mask. This based fact that copper etching process capable tighter tolerance than solder masking process. addition, pads will inherently create stress concentration point where solder wets lead. This stress concentration point eliminated when solder allowed flow down sides leads NSMD configuration.
Semiconductor Components Industries, LLC, 2007
October, 2007 Rev.
Publication Order Number: AND8188/D
AND8188/D
NSMD Configurations
When dimensionally possible, solder mask should located least "0.076 (0.003 away from edge solderable pad. This spacing used compensate registration tolerances solder mask, well insure that solder inhibited mask reflows along sides metal pad. dimensions recommended solder stencil, copper area solder mask shown Figures
4.500 3.900 3.000 2.073 1.400 0.600 0.000
PCB's solderable pads should match those pads package shown Figures Please note that NIS6111 footprint shows smaller exposed openings compared with recommended layout. attach pads footprint were divided into smaller exposed pads help reduce risk solder voiding during surface mounting package
0.600
1.324
3.900 1.927 3.000 3.992
3.992
3.358
2.676 2.200 1.800
1.000
0.200 0.200
1.076
4.500 4.373 4.500 3.992 3.611 3.223 3.000 2.726 2.537 2.200 1.800 1.400 1.000 0.601 0.474 0.000 2.492 2.873 3.254 3.992 4.373 3.508 4.373 2.676 2.276
4.373 3.992 3.900 3.000 2.726 2.716 2.200 1.800 1.400 1.000 1.826 0.601 0.474
0.846 1.608 2.492 2.873 3.003 3.992
3.358 2.873
4.373 3.992
2.222
1.460
0.798
0.036
0.473
3.358
Figure Solder Paste Stencil
4.703
3.662
2.600
2.352
0.163
0.752 1.000
3.484
0.671
4.703
4.576
2.873 3.138 3.773
4.373
0.000 0.676 1.076 1.324 1.876
3.738
4.576 4.576 2.537 1.877 2.676 2.276 0.924 0.524 0.000 2.924 3.457 4.576
4.703 3.020 2.842 2.600 2.352 0.848 0.600 2.461 1.953 2.600 2.352 0.848 0.600 0.000 0.989 1.481 2.619 3.127 0.896 1.557 2.543 3.000 3.381 3.203 3.096 2.766 2.676 2.276
0.924 0.524
4.703
3.738 3.408
2.171
0.748
0.087
3.484
2.095 1.587
0.000
1.400 1.800
Figure NIS6111 Footprint
3.265 3.646 3.662
Figure NIS6111 Solder Mask Pattern
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3.408 3.189 3.722
1.511
AND8188/D
Thermal/Electrical Vias Solder Type
vias used area they should placed larger attach pads improve electrical thermal performance. vias required larger attach pads, recommendation filled-vias. Filled-vias will help prevent solder from flowing down into holes, thereby reducing solder volume required solder joint this attach pad. Filled-vias normally filled with some type conductive epoxy. through-hole vias used, recommend that size less than equal 0.25 mils). number vias placed over attach also critical should exceed total exposed area copper pattern. other words, excessive through-hole vias will allow solder flow down into thereby decrease solder volume needed have sufficient solder joint. NIS6111 Board Mounting Process board mounting process optimized first defining controlling following processes: Creating maintaining solderable metallization contacts Choosing proper solder paste Screening/stenciling solder paste onto Placing package onto Reflowing solder paste Final solder joint inspection. Recommendations each these processes located below.
Solderable Metallization
Solder paste such Cookson Electronics' WS3060 with Type smaller sphere size recommended. WS3060 water-soluble flux cleaning. Cookson Electronics' PNC0106A used no-clean flux preferred.
Solder Screening onto
Stencil screening solder onto board commonly used industry. recommended stencil thickness used 0.075 (0.003 sidewalls stencil openings should tapered approximately degrees facilitate release paste when stencil removed from PCB. Note: 0.127 (0.005 thick stencil used also, will require smaller stencil openings reduce amount solder applied equal amount solder applied using 0.075 thick stencil. typical edge terminal pad, stencil opening should same size size package. However, cases where soldered PCB, stencil opening must divided into smaller openings shown Figure Dividing larger pads into smaller screen openings reduces risk solder voiding allows solder joints smaller terminal pads same height larger ones.
Package Placement onto
Pick place equipment with standard tolerance "0.05 better recommended. package will tend center itself correct slight placement errors during reflow process surface tension solder.
Solder Reflow
There common plated solderable metallizations, which used surface mount devices. either case, imperative that plating uniform, conforming, free impurities insure consistent solderable system. first metallization consists Organic Solderability Preservative (OSP) coating over copper plated pad. organic coating assists reducing oxidation order preserve copper metallization soldering. second recommended solderable metallization consists plated electroless nickel over copper pad, followed immersion gold. thickness electroless nickel layer determined allowable internal material stresses temperature excursions board will subjected throughout lifetime. Even though gold metallization typically self-limiting process, thickness should least 0.05 thick, consist more than overall solder volume. Having excessive gold solder joint create gold embitterment which affect reliability joint.
Once package placed board along with solder paste, standard surface mount reflow process used mount part. Figure example standard reflow profile. exact profile will determined, available, manufacture paste since chemistry viscosity flux matrix will vary. These variations will require small changes profile order achieve optimized process.
Peak 225°C Temperature (°C) Time (sec) Less than 2°C/sec
Soak Zone
sec)
Time Above Liquidus
Figure Typical reflow profile eutectic tin/lead solder. http://onsemi.com
AND8188/D
general, temperature part should raised more than 2°C/sec during initial stages reflow profile. soak zone then occurs when part approximately 150°C should last seconds. Typically, extending time soak zone will reduce risk voiding within solder. temperature then raised will above liquidus solder seconds depending mass board. peak temperature profile should between 225°C eutectic Sn/Pb solder. required, removal residual solder flux completed using recommended procedures forth flux manufacturer.
Final Solder Inspection
should have enough solder volume with proper stand-off height that "Hour Glass" shaped connection formed shown Figure "Hour Glass" solder joints reliability concern must avoided.
Preferred Solder Joint Undesirable "Hour Glass" Solder Joint
Figure Side view NIS6111 illustrating preferred undesirable solder joints.
inspection solder joints commonly performed with X-ray inspection system. With this tool, locate defects such shorts between pads, open contacts, voids within solder well extraneous solder. addition searching defects, mounted device should rotated side inspect sides solder joints with X-ray inspection system. solder joints Standard rework systems recommended this procedure since airflow temperature gradients carefully controlled. also recommend that board placed oven 125°C hours prior heating parts remove excess moisture from packages. order control region, which will exposed reflow temperatures, board should heated 100°C conduction through backside board location NIS6111 Package. Typically, heating nozzles then used increase temperature locally. Once NIS6111's solder joints heated above their liquidus temperature, package quickly removed pads board cleaned. cleaning pads typically performed with blade-style conductive tool with de-soldering braid. clean flux used during this process order simplify procedure. Solder paste then deposited screened onto site preparation mounting device. close proximity neighboring packages most board configurations, miniature stencil individual
Rework Procedure fact that NIS6111 leadless device, entire package must removed from board there issue with solder joints. important minimize chance overheating neighboring devices during removal package since devices typically close proximity with each other. component typically required. same stencil design that originally used mount package applied mini-stencil redressing pad. small configurations NIS6111, since pads underside package, manual pick place procedure without magnification recommended. dual image optical system where underside package aligned board should used instead. Reflowing component onto board accomplished either passing board through original reflow profile, selectively heating NIS6111 package with same process that used remove benefit with subjecting entire board second reflow that packages will mounted consistently profile that already defined. disadvantage that other devices mounted with same solder type will reflowed second time. subjecting parts second either concern unacceptable specific application, than localized reflow option would recommended procedure.
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AND8188/D
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