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AND8157/D ECLinPS MAX] (SiGe) SPICE Modeling
Objective
objective this provide sufficient circuit schematic SPICE parameter information perform system level interconnect modeling devices Semiconductor's high performance ECLinPS (SiGe) logic family. family output edge rates power supply levels
intended provide information necessary perform circuit level device behavioral LOGIC modeling ECLinPS devices. Schematic Information
Table Schematics Netlist Nomenclature
Parameter Function Description LVPECL LVNECL -2.5 -3.3 LVNECL LVPECL Internally Generated Voltage (VEE 0.915 True Input BUFFER Inverted Input BUFFER True Output BUFFER Inverted Output BUFFER Internal True Input Output Buffer Internal Invert Input Output Buffer
contains representative input output schematics, netlists waveforms SPICE modeling simulating ECLinPS family devices INPUT OUTPUT structures. This application note will modified devices added. Table describes nomenclature used modeling schematic netlist ECLinPS devices.
subcircuit models, such input output buffers, package simulate only device input output paths. When used with interconnect models, complete signal path modeled shown Figure
INPUT BUFFER
OUTPUT BUFFER
PACKAGE
PACKAGE
BUFFER
INTERCONNECT
Figure Interconnect Model Template
device modeling, behavioral LOGIC gate functionality modeled (see Figure DEVICE Model Template)
Semiconductor Components Industries, LLC, 2005
February, 2005 Rev.
Publication Order Number: AND8157/D
BUFFER
AND8157/D
DEVICE INPUT BUFFER OUTPUT BUFFER
PACKAGE
Figure DEVICE Model Template Package SPICE Netlist
Models various package types have been included improve accuracy system interconnect model (Table
Table Available Package Models
Package SOIC-8 TSSOP-8 QFN-16 Model Appendix (Figure Table Appendix (Figure Table Figure
netlists organized subcircuit. each subcircuit model netlist, model name should followed list external node interconnects. When copying "SUBCKT" netlist files your text editor, Adobe® Acrobat® Reader higher ensure proper character conversion.
SPICE Parameter Information
package model represents parasitics they measured significant distance from ground pin. package models should placed external inputs input model, external outputs output model line. Since current constant, package model necessary. Note internal voltage does require package model. speed simulation process, simplified package models have been used.
Input Buffer
addition schematics netlists there listing SPICE parameters transistors diodes referenced schematics netlists found provided APPENDIX These parameters represent typical case device transistor diode. Varying typical parameters will affect performance structures recommended. Modeling device actual delay time intention this document. performance levels varied methods discussed next section. resistors referenced schematics polysilicon have negligible parasitic capacitance real circuit. schematics display only devices needed SPICE netlists.
Modeling Information
input buffer schematics netlists present various input structures ECLinPS family devices. schematics netlists include package model parasitics accuracy.
Output Buffer
Output buffer schematics netlists models provided. package model parasitics been added accuracy. output buffer models typically show internal differential inputs driven INT. Outputs should always simulated with both output lines properly terminated, even when only line single ended intended. This will balance output buffer's load. correlation, typical output waveform seen input receiver, shown Figure
bias drivers devices included they unnecessary interconnect simulations their results large increase model complexity simulation time. internal reference voltages (VBB, VCS, etc.) should modeled with ideal constant voltage sources. Output input levels ECLinPS devices generally vary ratio with power supply; remain relatively constant over temperature. Note supply always relative VEE, most negative supply. output schematics SPICE parameters include typical waveform, simulation correlation. Inclusion package models typically will about output waveform rise fall time. Simple adjustments made models permit
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PACKAGE
BUFFER
BUFFER
FUNCTIONAL LOGIC MODELED
AND8157/D
output characteristics emulate conditions near performance corners data sheet specifications. Consistent, repeatable cross-point voltages should maintained.
Adjust Rise Fall Times,
Produce desired variant rise fall times output slew rates adjusting collector load resistors. This voltage determines tail current output differential affecting output.
Adjust
INPUT BUFFERS voltage divider BIAS feeding side differential. This remains VCC/2 forcing detect threshold ratiometrically change with VCC. When left floating open, SELx inputs will forced default state internal pulldown resistor VEE, relative VCC/2 BIAS voltage other side differential. input, when left floating open, will forced default state HIGH internal pullup resistor VCC.
6L11 6L16
Adjust level together varying VCC. output levels will follow changes ratio.
Adjust
Inputs, when left floating open, will forced determined default state. Precautionary considerations needed prevent spontaneous self oscillation device.
Summary
Adjust level independently level adjusting increasing collector load resistance. Note level will also affected IBASE drop across collector load resistor. changed varying supply which will also affect gate current through current source resistor.
Device Specifics 6L239
information included this provides adequate information SPICE level system interconnect simulation. block diagram Figure illustrates typical situation, which modeled using information this kit.
exception general rule "levels relative VCC" found internal input node SELx,
Line Delay Driver Output Minimum Trace Delay Receiver Input
Figure Typical Application SPICE Modeling
Device input output models presented Table
Table ECLinPS Input/Output Buffer Selector Guide
Device NB6L11 Function Multilevel Input Differential LVNECL/LVPECL Clock Data Fanout Buffer/Translator Multilevel Input Differential LVNECL/LVPECL Clock Data Receiver/Buffer/Translator Differential Clock Differential LVPECL 1/2/4/8/16 Clock Divider NB6N239S Differential Clock LVDS 1/2/4/8 1/2/4/8, 2/4/8/16 Clock Divider INPUT OUTPUT INPUT OUTPUT SELx INPUT INPUT CLKs INPUT OUTPUT Single Ended Inputs INPUT CLKs INPUT LVDS OUTPUT Description Model INBUF_01 OBUF_01 INBUF_01 OBUF_01 EN_SEL CLK_IN OBUF_01 INBUF_01 INBUF_01 OBUF_02
NB6L16
NB6L239
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INBUF_01 INPUT BUFFER
Input Buffer Package OPEN DEFAULT BIAS
R107 R103u R105 Q101 Q102 TNSGB TNSGB R108
D101u R101 39.5m L101 753.3pH C101a 51.12f C101b 62.48f D101d
R103d 37.5
D102u R102 39.5m L102 753.3 C102a 51.12f C102b 62.48f D102d R104u 37.5 R106
R104d
Q103a TNSGB
Q103b TNSGB
LVPECL MODE OPERATION
0.025 0.025 0.475 0.025 0.025 0.475
R109
0.855
Figure INBUF_01 Input Buffer V_V1 V_V2 V_VCC 3.3Vdc V_VCS .855Vdc +PULSE 0.025n 0.025n 0.475n +PULSE 0.025n 0.025n 0.475n .SUBCKT INBUF_01 C_C101a 51.12f C_C101b 62.48f C_C102a 51.12f C_C102b 62.48f D_D101d D_D101u D_D102d D_D102u L_L101 753.3pH L_L102 753.3pH Q_Q101 TNSGB Q_Q102 TNSGB Q_Q103a TNSGB Q_Q103b TNSGB R_R101 39.5m R_R102 39.5m
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R_R103d 37.5K R_R103u R_R104d R_R104u 37.5K R_R105 R_R106 R_R107 R_R108 R_R109 .END INBUF_01
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SELx INPUT BUFFER
Input Buffer Package
D101u R101 39.5m L101 753.3pH C101b 62.48f D101d D102d D102u R103 R104 Q101 TNSGB Q102 TNSGB R105
Open Default BIAS
C101a 51.12f
R102
1.25 0.025 0.025 0.475
3.3Vdc
0.855Vdc
R106
R107
Q103 TNSGB
LVPECL MODE OPERATION
R108
BIAS
Figure SELx Input Buffer V_In V_VCC 3.3Vdc V_VCS 0.855Vdc +PULSE 1.25 0.025n 0.025n 0.475n .SUBCKT ENb_SEL C_C101a 51.12f C_C101b 62.48f D_D101d D_D101u D_D102d D_D102u L_L101 753.3pH Q_Q101 TNSGB Q_Q102 TNSGB Q_Q103 TNSGB R_R101 39.5m R_R102 R_R103 R_R104 R_R105 R_R106 R_R107 R_R108 .END ENb_SEL
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AND8157/D
INPUT BUFFER
Input Buffer Package OPEN DEFAULT BIAS
D101u R101 39.5m L101 753.3pH C101b 62.48f D101d R104 Q101 Q102 TNSGB TNSGB
R102 R103
C101a 51.12f
0.025 0.025 0.475
3.3Vdc
0.855Vdc
R106
R107
Q103a TNSGB
Q103b TNSGB
LVPECL MODE OPERATION BIAS
R108
Figure Input Buffer +PULSE 0.025n 0.025n 0.475n V_V1 V_VCC 3.3Vdc V_VCS .855Vdc .SUBCKT C_C101a 51.12f C_C101b 62.48f D_D101d D_D101u L_L101 753.3pH Q_Q101 TNSGB Q_Q102 TNSGB Q_Q103a TNSGB Q_Q103b TNSGB R_R101 39.5m R_R102 R_R103 R_R104 R_R106 R_R107 R_R108 .END .MRb
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CLKS INPUT BUFFER
Termination
Input Buffer
Package
R101 39.5m L101 753.3pH C101a 51.12f C101b 62.48f D101u D103d R102 39.5m L102 753.3pH C102b 62.48f D102u D104d
D105u R105 1600 R106 1600
R109 Q101 TNSGB Q102 TNSGB
R110
D106d R103
R104 D107u
R107 1600
R108 1600
Q103a TNSGB
C102a 51.12f
D108d
Q103b TNSGB
R111
Package
0.915Vdc
3.3Vdc 0.025 0.025 0.025 0.025 0.475 0.475
1.3Vdc
LVPECL MODE OPERATION
Figure CLKs Input Buffer +PULSE 0.025n 0.025n 0.475n +PULSE 0.025n 0.025n 0.475n V_TD 1.3Vdc V_VCC 3.3Vdc V_VCS 0.915Vdc V_VIN V_VINb .SUBCKT CLK_IN C_C101a 51.12f C_C101b 62.48f C_C102a 51.12f C_C102b 62.48f D_D101u D_D102u D_D103d
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D_D104d D_D105u D_D106d D_D107u D_D108d L_L101 753.3pH L_L102 753.3pH Q_Q101 TNSGB Q_Q102 TNSGB Q_Q103a TNSGB Q_Q103b TNSGB R_R101 39.5m R_R102 39.5m R_R103 R_R104 R_R105 1600 R_R106 1600 R_R107 1600 R_R108 1600 R_R109 R_R110 R_R111 .END CLK_IN
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AND8157/D
INBUF_01 INPUT BUFFER
Input Buffer Package OPEN DEFAULT BIAS
R107 Q101 R108 Q102
D101u R101 39.5m L101 753.3pH C101b 62.48f D101d
R103u
R105
TNSGB TNSGB
C101a 51.12f
R103d 37.5k
R102 39.5m
L102 753.3pH C102a 51.12f C102b 62.48f
D102u D102d
R104u 37.5
R106
R104d Q103a TNSGB
Q103b TNSGB
LVPECL MODE OPERATION
R109
3.3Vdc 0.025 0.025 0.025 0.025 0.475 0.475
.855Vdc
Figure INBUF01 Input Buffer V_V1 V_V2 V_VCC 3.3Vdc V_VCS .855Vdc +PULSE 0.025n 0.025n 0.475n +PULSE 0.025n 0.025n 0.475n .SUBCKT INBUF_01 C_C101a 51.12f C_C101b 62.48f C_C102a 51.12f C_C102b 62.48f D_D101d D_D101u D_D102d D_D102u L_L101 753.3pH L_L102 753.3pH Q_Q101 TNSGB Q_Q102 TNSGB Q_Q103a TNSGB Q_Q103b TNSGB R_R101 39.5m R_R102 39.5m
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R_R103d 37.5K R_R103u R_R104d R_R104u 37.5K R_R105 R_R106 R_R107 R_R108 R_R109 .END INBUF_01
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OBUF_01 OUTPUT BUFFER DRIVING 6L239 CLKS INPUT BUFFER
Output Buffer
Output
Package
TNSGC
D10u D10d 39.5m 753.3pH C10b 62.48f D111u
Termination
C10a 51.12f
TNSGC
TNSGB TNSGB
VCS1
TNSGB
D111d
39.5m
753.3pH C11b 62.48f
C11a 51.12f
Input Buffer
Package
R101 39.5m L101 753.3pH C101b 62.48f
Termination
D105u D101u D103d D102u D104d D108d VCS2 D106d R103 R104 D107u R107 1600 R108 1600 R105 1600 R106 1600
R109
R110
T101
Q101 Q102 TNSGB TNSGB
C101a 51.12f
T102
R102 39.5m
L102 753.3pH C102b 62.48f
C102a 51.12f
Q103a TNSGB
Q103b TNSGB
R111
0.025 0.025 0.475 0.025 0.025 0.475
LVPECL MODE OPERATION
VCS1 VCS2 VCS2 0.915Vdc 1.3Vdc
3.3Vdc
VCS1 0.917Vdc
1.3Vdc
Figure OBUF_01 Output Buffer driving 6L239 CLKs Input Buffer
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V_V1 V_V2 V_VCC 3.3Vdc V_VCS1 VCS1 0.917Vdc V_VCS2 VCS2 0.915Vdc V_VTD 1.3Vdc V_VTT 1.3Vdc +PULSE 0.025n 0.025n 0.475n +PULSE 0.025n 0.025n 0.475n .SUBCKT OBUF_01 C_C10a 51.12f C_C10b 62.48f C_C11a 51.12f C_C11b 62.48f D_D10d D_D10u L_L10 753.3pH L_L11 753.3pH Q_Q1 TNSGB Q_Q2 TNSGB Q_Q3 VCS1 TNSGB Q_Q4 TNSGC Q_Q5 TNSGC R_R1 R_R10 39.5m R_R11 39.5m R_R2 R_R3 R_R4 R_R5 T_T1 Z0=50 TD=80ps T_T2 Z0=50 TD=80ps .END OBUF_01 .SUBCKT CLK_INBUF C_C101a 51.12f C_C101b 62.48f C_C102a 51.12f C_C102b 62.48f D_D101u D_D102u D_D103d D_D104d D_D105u D_D106d D_D107u D_D108d D_D111d D_D111u L_L101 753.3pH L_L102 753.3pH Q_Q101 TNSGB Q_Q102 TNSGB Q_Q103a VCS2 TNSGB Q_Q103b VCS2 TNSGB R_R101 39.5m R_R102 39.5m R_R103 R_R104 R_R105 1600 R_R106 1600 R_R107 1600
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R_R108 1600 R_R109 R_R110 R_R111 T_T101 Z0=50 TD=80ps T_T102 Z0=50 TD=80ps .END CLK_INBUF
2.200
2.000
1.800
1.600 1.517 7.60 7.80 V(T101:B+) V(102) 8.00 8.20 Time 8.40 8.60 8.80
Figure Typical OBUF_01 OUTPUT Waveform driving 6L239 CLK/CLK INPUT BUFFER
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OBUF_02 OUTPUT BUFFER DRIVING STANDARD LVDS TERMINATION
Internal Nodes LVDS Output Buffer
Output
Package
TNSGB
TNSGB
TNSGB
TNSGB
D10u
39.5m
753.3 C10a 51.12f C10b 62.48f
D10d
VCS1
TNSGB
TNSGB D111u
TNSGB
39.5m
753.3 C11a 51.12f C11b 62.48f
D111d
T-Lines Delay
LVDS Termination
3.3V LVPECL MODE OPERATION 1.66
1.85 1.85 1.45 1.45 3.3Vdc VCS1 VCS1 0.931Vdc 1.3Vdc
Figure OBUF_02 Output Buffer driving standard LVDS termination
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V_V1 V_V2 V_V3 V_V4 V_VCC V_VCS1 V_VTT +PULSE +PULSE +PULSE +PULSE INDB INXB 3.3Vdc VCS1 .931Vdc 1.3Vdc 1.45 0.2n 0.2n 0.2n 1.45 0.2n 0.2n 0.2n 1.85 0.2n 0.2n 0.2n 1.85 0.2n 0.2n 0.2n
.SUBCKT OBUF_02 C_C10a N66098 51.12f C_C10b 62.48f C_C11a N09146 51.12f C_C11b 62.48f D_D10d D_D10u D_D111d D_D111u L_L10 N66098 753.3pH L_L11 N09146 753.3pH Q_Q1 TNSGB Q_Q10 TNSGB Q_Q11 VCS1 TNSGB Q_Q2 TNSGB Q_Q5 INDB N293875 TNSGB Q_Q6 INDB N293875 TNSGB Q_Q9 INXB TNSGB R_R1 R_R10 N66098 39.5m R_R11 N09146 39.5m R_R2 N293875 R_R3 R_R90 T_T1 Z0=50 TD=100ps T_T2 Z0=50 TD=100ps .END OBUF_02
1.398
1.300
1.200
1.100
1.017 10.0 V(100) V(99)
10.1
10.2
10.3
10.4 Time
10.5
10.6
10.7
10.8
10.9
Figure Typical OBUF_02 OUTPUT BUFFER Waveform driving standard LVDS termination
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APPENDIX
************* Transistor Diode Models ECLinPS ************** .MODEL TNSGB (IS=2.18e-17 BF=179 NF=1 VAF=96.5 IKF=2.42e-02 ISE=3.83e-16 NE=2.5 BR=20.4 VAR=2.76 IKR=1.98e-03 ISC=2.91e-17 NC=1.426 RB=55 IRB=1.12e-04 RBM=48 RE=6 RC=11 CJE=7.98e-15 VJE=.8867 MJE=.2868 TF=2.00e-12 ITF=0.4e-02 XTF=0.7 VTF=0.6 PTF=20 TR=0.5e-9 CJC=4.55e-15 VJC=0.632 MJC=0.301 XCJC=0.3 CJS=4.71e-15 VJS=.4193 MJS=0.256 EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9) .MODEL TNSGC (IS=1.47e-16 BF=180 NF=1 VAF=96.3 IKF=1.62e-01 ISE=2.96e-15 NE=2.5 BR=20.2 VAR=2.76 IKR=1.34e-02 ISC=2.14e-16 NC=1.426 RB=25 IRB=1.50e-03 RBM=4 RE=1 RC=7 CJE=6.34e-14 VJE=.8867 MJE=.2868 TF=2.00e-12 ITF=0.25e-01 XTF=0.7 VTF=0.35 PTF=20 TR=0.5e-9 CJC=4.08e-14 VJC=0.632 MJC=0.301 XCJC=.3 CJS=11.12e-15 VJS=.4193 MJS=0.256 EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9) .MODEL (IS=9.99E-21 CJO=6.52E-14 RS=50.1 VJ=.82
APPENDIX
0.05 1.36 0.547 0.188 0.039 1.36
M=.25
BV=35)
0.547 0.188
Figure Schematic Model SOIC Packge Table
Package: 8-Lead SOIC Component Value 0.05 1.36 .547 0.188
Figure Schematic Model TSSOP Packge Table
Package: 8-Lead TSSOP (DT) Component Value .039 1.36 .547 .188
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AND8157/D
ECLinPS trademark Semiconductor Components Industries, (SCILLC). Adobe Acrobat registered trademarks Adobe Systems Incorporated.
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
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AND8157/D

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