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AND8118/D EPT21/23/25 ECLinPS PlusTranslator output SPICE Modeling
Objective objective this provide customers with enough circuit schematic SPICE parameter information allow them perform system level interconnect modeling current devices ECLinPS Plus logic line, Semiconductor's high performance family. intended provide information necessary perform circuit level modeling ECLinPS Plus Translator devices. Schematic Information contains representative input output schematics, netlists, waveform used ECLinPS Plus Translator devices. This application note modified device input output buffers added. subcircuit models such input output buffer, package, input ESD, output interconnected subcircuits simulate specific device input output buffers structure shown Figure below. block diagram Figure illustrates typical driver receiver interconnect configuration which modeled using information this kit. There four terminals transistor models: Emitter, Base, Collector, Substrate (biased VEE). should noted that input buffer circuit would drive differentially replacing with inverted signal. Table describes nomenclature used schematics netlists.
Subcircuit Interconnects Input Pins
Board Connection Package Model Input Model Input Buffer Model
Subcircuit Interconnects Output Pins
Output Buffer Model Output Model Package Model Board Connection
Figure Input Output Pins Interconnects
Line
Typical Input
Typical Output
Figure Typical Application SPICE Modeling
Semiconductor Components Industries, LLC, 2003
August, 2003 Rev.
Publication Order Number: AND8118/D
AND8118/D
Table Schematics Netlist Nomenclature
Parameter INTA INTB *EPT25 Function Description Internal Reference Voltage (VEE -3.3 LVECL TRUE (Positive Phase) INPUT INVERTED (Negative Phase) INPUT Internal Input Node Drive Output Internal Input Node Drive Output Output (Positive Phase)
Input Buffer Typical Input Buffer schematic (see Figure Typical INBUF) netlist represents Voltage NECL configuration structure currently MC100EPT25 device this family. simulate Voltage PECL mode operation used MC100EPT21 MC100EPT23, levels except VCS, adjusted (shifted) +3.3 with respect VCC. adjusted with respect approx. This schematic requires addition models (Figures package models (see Appendix increased accuracy simulated model behavior. internal input pull-up pull-down resistor shown network, Figures unnecessary include package model pins models because intended output node voltage reference. modeled external node, usually bypassed constant voltage supply. Adding Package parameters would provide additional benefit pin. Output Buffer voltage output buffer schematic with output structure simplified package model seen Figure input output that driving being driven chip signal should include package models. When simulating output, load (resistor capacitance), package model, structure, output emitter follower unused output, should eliminated simplify system model. Package case model SOIC8 (Appendix TSSOP8 (Appendix package types included improve accuracy system model. package model represents parasitics from including pad. package model should represented each device input connecting input model, device output pins connecting output model, VCC,
VEE. package model used pin, necessary since current constant. expansion SOIC8 Package Model found Appendix When high accuracy important speed simulation process, simplified package model used, which shown Figure structure used ECLinPS Plus Translators with output found Figures MC100EPT21 MC100EPT23 devices structure, Figure Input with pull-up pull-down EPT21/23. MC100EPT25, Figure Input with Pull-down EPT25. Figure output structure. SPICE Netlists netlists organized group subcircuits. each subcircuit model netlist, model name followed list external node interconnects. Subcircuit models such Input Output Buffer, Package, Input Output should connect supplies through hierarchical, passed parameters such VCC, VEE, etc., proper simulation separately attached independent power supplies. SPICE Parameter Information addition schematics netlists listing SPICE parameters referenced transistors, TN1. These parameters represent typical device given transistor. Varying typical parameters will affect performance transistor structures, type modeling that intended this application note actual delay times necessary since they modeled. Variation device transistor parameters recommended. Some output performance levels more easily varied other methods will discussed next section. Modeling Information bias drivers devices detailed since their circuitry would result substantial increase model complexity simulation time. Instead, these internal reference voltages driven with ideal constant voltage sources. output buffer schematic netlist simulate typical output waveshape, which seen Figure LVTTL_OUT Output Waveform MHz). Simple adjustments made models allowing some output variance simulate conditions near mean typical conditions. This application note intended provide simulation data book specifications limits process corners device. Summary information included this provides adequate information SPICE level system interconnect simulation.
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AND8118/D Input Buffer
-1.33
-1.7 -0.95 -2.1 0.15 0.15 -3.3
Figure Typical INBUF
.SUBCKT TYPICAL INBUF Q_Q1 Q_Q2 Q_Q3 Q_Q4 Q_Q5 Q_Q6 Q_Q7 Q_Q8 Q_Q9 Q_Q10 Q_Q11 Q_Q12 Q_Q13 Q_Q14 Q_Q15 Q_Q16 Q_Q17 Q_Q18 Q_Q19 Q_Q20 Q_Q21 Q_Q22 R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 V_V1 -3.3Vdc V_V2 -2.1Vdc V_IN -1.33Vdc V_VCC 0Vdc V_INB +PULSE -1.7V -0.95V 0.15n 0.15n .END TYPICAL INBUF
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AND8118/D Output Buffer
0.38p
3.3Vdc INT_A 0.7n 0.7n 1.3n INT_B 0.7n 0.7n 1.3n INTA
ESDS ESDM Package Test Load
L07WB 1.287nH
0.5495nH
0.35p
ESDM ESDS
ESDM ESDM 0.193p
INTB
Figure LVTTL_OUT
.SUBCKT EPT_LVTTL_OUT_PACKAGE Q_Q1 INTA V_VCC 3.3Vdc Q_Q2 C_C5 Q_Q8 Q_Q4 D_D6 ESDS R_R1 INTB L_L07WB 1.287nH R_R5 L_L07 0.5495nH D_D2 ESDM D_D3 ESDM C_C1 0.38p Q_Q7 D_D5 ESDM R_R2 INTA Q_Q5 INTB Q_Q3 C_C07 0.193p D_D4 ESDS V_INT_A INTA +PULSE 0.7n 0.7n 1.3n D_D1 ESDM Q_Q6 V_INT_B INTB +PULSE 0.7n 0.7n 1.3n C_C2 0.35p .END EPT_LVTTL_OUT_PACKAGE
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AND8118/D
Pulldown Resistor
device data sheet
Figure Input with Pull-down EPT25 .SUBCKT IN_ESD_PD ESDM ESDM ESDM ESDM ESDS ESDM ESDS ESDM ESDS .ENDS IN_ESD_PD
Pull-up Resistor *See Figure Pull-down Resistor
Figure Input with Pull-up Pull-down EPT21/23 .SUBCKT IN_ESD_PU ESDM ESDM ESDM ESDM ESDS ESDM ESDS ESDM ESDS .ENDS IN_ESD_PU
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AND8118/D
Figure Output .SUBCKT OUT_ESD ESDM ESDM ESDM ESDS ESDM ESDS .ENDS OUT_ESD
2.41V (81.556n 1.9982) (84.43n 2.0018)
VOUT
(81.959n, 797.915m)
(83.007n, 305.321m)
TIME (ns)
Figure LVTTL_OUT Output Waveform (fin MHz)
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AND8118/D
*********** Transistor Diodes Nominal SPICE Models* *********** .MODEL (IS=6.54e-18 BF=195 NF=1 VAF=93.6 IKF=6.81e-03 ISE=3.26e-16 NE=2.5 BR=18.4 VAR=2.76 IKR=6.36e-04 ISC=1.89e-17 NC=1.426 RB=544 IRB=3.16e-05 RBM=154 RE=13 RC=61 CJE=1.45e-14 VJE=.8867 MJE=.2868 TF=8.00e-12 ITF=5.2e-03 XTF=2.8 VTF=1.4 PTF=41.56 TR=1e-9 CJC=5.68e-15 VJC=0.632 MJC=0.301 XCJC=.3 CJS=7.94e-15 VJS=.4193 MJS=0.256 EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9) .MODEL (IS=2.18e-17 BF=179 NF=1 VAF=96.5 IKF=2.42e-02 ISE=3.83e-16 NE=2.5 BR=20.4 VAR=2.76 IKR=1.98e-03 ISC=2.91e-17 NC=1.426 RB=230 IRB=1.12e-04 RBM=48 RE=6 RC=22 CJE=4.98e-14 VJE=.8867 MJE=.2868 TF=8.00e-12 ITF=1.6e-02 XTF=2.8 VTF=1.4 PTF=41.56 TR=1e-9 CJC=1.55e-14 VJC=0.632 MJC=0.301 XCJC=.3 CJS=1.71e-14 VJS=.4193 MJS=0.256 EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9) .MODEL ESDM (IS=1.55E-14 CJO=160fF RS=12 VJ=.58 M=.25 BV=9) .MODEL ESDS (IS=1.55E-14 CJO=29fF VJ=.624 M=.571) SPICE MODELS
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AND8118/D
Appendix Package: SO-8
SPICE subcircuit file coupled Transmission line model Conductor number-pin designation Conductor number lumps: FASTEST APPLICABLE EDGE RATE: COMPRESSION SUBCIRCUITS PERFORMED: Connect chip side N**I board .SUBCKT LINES N01I N01O N02I N02O N05I N05O N06I N06O N07I N07O N08I L01WB N01I N01M 1.367e-09 N01M N01O 7.794e-10 N01M 2.445e-13 L02WB N02I N02M 1.287e-09 N02M N02O 5.473e-10 N02M 1.888e-13 L03WB N03I N03M 1.287e-09 N03M N03O 5.473e-10 N03M 1.901e-13 L04WB N04I N04M 1.367e-09 N04M N04O 7.723e-10 N04M 2.443e-13 L05WB N05I N05M 1.367e-09 N05M N05O 7.710e-10 N05M 2.478e-13 L06WB N06I N06M 1.287e-09 N06M N06O 5.489e-10 N06M 1.916e-13 L07WB N07I N07M 1.287e-09 N07M N07O 5.495e-10 N07M 1.930e-13 L08WB N08I N08M 1.367e-09 N08M N08O 7.786e-10 N08M 2.451e-13 K0102 0.1687 K0102WB L01WB L02WB 0.3400 C0102 N01O N02O 3.674e-14 K0103 0.0702 K0103WB L01WB L03WB 0.1847 K0203 0.1822 K0203WB L02WB L03WB 0.3505 C0203 N02O N03O 3.521e-14 K0204 0.0682 K0204WB L02WB L04WB 0.1847 K0304 0.1694 K0304WB L03WB L04WB 0.3400 C0304 N03O N04O 3.675e-14
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AND8118/D
K0305WB L03WB L05WB 0.1847 K0405WB L04WB L05WB 0.3455 K0406WB L04WB L06WB 0.1847 K0506 0.1697 K0506WB L05WB L06WB 0.3400 C0506 N05O N06O 3.720e-14 K0507 0.0682 K0507WB L05WB L07WB 0.1847 K0607 0.1824 K0607WB L06WB L07WB 0.3505 C0607 N06O N07O 3.570e-14 K0608 0.0702 K0608WB L06WB L08WB 0.1847 K0708 0.1691 K0708WB L07WB L08WB 0.3400 C0708 N07O N08O 3.632e-14 .ENDS LINES
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AND8118/D
N01I R01WB N01W L01WB K0103WB N01C C0102 K0102WB K0104 N02I R02WB N02W L02WB K0203WB N02C N02R K0102 N02O K0103 K0102 N01R N01O
N03I R03WB
N03W L03WB
N03R N03C
N03O
N04I R04WB
N04W L04WB
N04R N04C
N04O
Figure
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AND8118/D
Appendix Package: TSSOP-8
SPICE subcircuit file coupled transmission lines Transmission line model Conductor number-pin designation cross reference: counter-clockwise Conductor number lumps: FASTEST APPLICABLE EDGE RATE: 0.048 COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 R_SHORT 0.0001 X_777 N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O PACKAGE .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O R01WB N01I N01W 4.727e-02 L01WB N01W N01R 1.158e-09 N01R N01C 9.680e-04 N01C 8.978e-14 N01C N01O 7.466e-10 R02WB N02I N02W 3.815e-02 L02WB N02W N02R 9.835e-10 N02R N02C 9.680e-04 N02C 7.711e-14 N02C N02O 7.466e-10 R03WB N03I N03W 3.815e-02 L03WB N03W N03R 9.835e-10 N03R N03C 9.680e-04 N03C 7.704e-14 N03C N03O 7.465e-10 R04WB N04I N04W 4.727e-02 L04WB N04W N04R 1.158e-09 N04R N04C 9.680e-04 N04C 8.983e-14 N04C N04O 7.460e-10 R05WB N05I N05W 4.727e-02 L05WB N05W N05R 1.158e-09 N05R N05C 9.680e-04 N05C 8.983e-14 N05C N05O 7.460e-10 R06WB N06I N06W 3.815e-02 L06WB N06W N06R 9.835e-10 N06R N06C 9.680e-04 N06C 7.704e-14 N06C N06O 7.465e-10 R07WB N07I N07W 3.815e-02 L07WB N07W N07R 9.835e-10
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AND8118/D
N07R N07C 9.680e-04 N07C 7.711e-14 N07C N07O 7.466e-10 R08WB N08I N08W 4.727e-02 L08WB N08W N08R 1.158e-09 N08R N08C 9.680e-04 N08C 8.978e-14 N08C N08O 7.466e-10 K0102 0.2481 K0102WB L01WB L02WB 0.1729 C0102 N01C N02C 2.283e-14 K0103 0.1067 K0103WB L01WB L03WB 0.0598 K0104 0.0593 K0203 0.2479 K0203WB L02WB L03WB 0.1463 C0203 N02C N03C 2.136e-14 K0204 0.1068 K0204WB L02WB L04WB 0.0598 K0304 0.2481 K0304WB L03WB L04WB 0.1729 C0304 N03C N04C 2.279e-14 K0506 0.2481 K0506WB L05WB L06WB 0.1513 C0506 N05C N06C 2.279e-14 K0507 0.1068 K0507WB L05WB L07WB 0.0615 K0508 0.0593 K0607 0.2479 K0607WB L06WB L07WB 0.1729 C0607 N06C N07C 2.136e-14 K0608 0.1067 K0608WB L06WB L08WB 0.0615 K0708 0.2481 K0708WB L07WB L08WB 0.1513 C0708 N07C N08C 2.283e-14 .ENDS PACKAGE
ECLinPS Plus trademark Semiconductor Components Industries, LLC.
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer.
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AND8118/D

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