Objective objective this provide sufficient circuit schematic SPICE pa

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AND8077/D GigaCommt (SiGe) SPICE Modeling
Objective objective this provide sufficient circuit schematic SPICE parameter information perform system level interconnect modeling devices Semiconductor's high performance GigaComm (Silicon Germanium) logic family. family have output edge rates power supply levels intended provide information necessary perform circuit level modeling GigaComm (SiGe) devices. Schematic Information contains representatives input output schematics, netlists, waveform used GigaComm family devices. This application note will modified devices added. Table describes nomenclature used modeling schematic netlist GigaComm devices. subcircuit models, such input output buffers, package simulate only device input output paths. When used with interconnect models, complete signal path modeled shown Figure
Table Schematics Netlist Nomenclature
Parameter Function Description 2.5/3.3 LVPECL LVECL -2.5/-3.3 LVPECL LVECL Output Voltage Reference (See Device Data Sheet) Internally Generated Voltage mV)* Ground True Input Inverted Input True Output Inverted Output
*Note that NBSG16VS, NBSG53A, NBSG72A, NBSG86A using modulate output amplitude (see device specifics more details).
OUTPUT BUFFER
INPUT BUFFER
PACKAGE
PACKAGE
BUFFER
INTERCONNECT
Figure Interconnect Model Template
device modeling, behavioral LOGIC gate functionality modeled (see Figure DEVICE Model Template)
Semiconductor Components Industries, LLC, 2005
February, 2005 Rev.
Publication Order Number: AND8077/D
BUFFER
AND8077/D
DEVICE INPUT BUFFER OUTPUT BUFFER
PACKAGE
Figure DEVICE Model Template
Package worst-case model various package types included improve accuracy system model (see Table package model represents parasitics they measured sizable distance from ground pin. package models should placed external inputs input model, external outputs output model line. Since current constant, package model necessary. Please note that internal voltage does require package model. shorten speed simulation process, simplified package model should used. input output buffers schematic include simplified package model (Figures
Table Available Packages
Package Model 16-FCBGA 16-QFN Page Number
Output Buffer output buffer schematics netlists modeled seen pages package models with parasitics should added better accuracy. input output that driving being driven chip signal should include package models. Open floating pins will require package models. output buffer models typically show internal differential inputs outputs should always simulated with both output lines terminated, even when only line single ended intended. This will balance output buffer's load. Example Typical Interconnect Circuit output signal buffer SG_0BUF_01 with protection structure simplified package model properly terminated, driving simplified input structure shown Figure circuit provides working schematics complete interconnect modeling. output waveform observed receiver interconnect example shown Figure SPICE Netlist netlists organized group subcircuits. each subcircuit model netlist, model name should followed list external node interconnects. When copying "SUBCKT" netlist files your text editor, Adobe® Acrobat® Reader® higher ensure proper conversion.
Input Buffer "SG_INBUF" schematic netlist representing input structures devices GigaComm family devices. schematics require addition package models accurate; otherwise functionally correct. unnecessary include Package model type pins models because type input intended internal node most applications. type input modeled external node usually bypassed because constant voltage, adding Package parameters provide additional benefit.
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PACKAGE
BUFFER
BUFFER
FUNCTIONAL LOGIC MODELED
AND8077/D
SPICE Parameter Information addition schematics netlists there listing SPICE parameters transistors referenced schematics netlists. These parameters represent typical device given transistor. Varying typical parameters will affect performance structures; type modeling intended this note, actual delay times necessary modeled, result variation device parameters meaningless. performance levels more easily varied other methods will discussed next section. resistors referenced schematics polysilicon have parasitic capacitance real circuit none required model. schematics display only devices needed SPICE netlists. Modeling Information bias drivers devices included they unnecessary interconnect simulations their results large increase model complexity simulation time. internal reference voltages (VBB, VCS, etc.) should driven with ideal constant voltage sources. GigaComm device used positive mode levels vary with power supply; constant function temperature. schematics SPICE parameters will provide typical output waveform, which seen Figures Note that package models will ps-7 rise fall time output waveform. Simple adjustments made models allowing output characteristics simulate conditions near corners data book specifications. Consistent cross-point voltages need maintained. adjust rise fall times: Produce desired rise fall times output slew rates adjusting collector load resistors change gates tail current. voltage will affect tail current output differential, which will interact with load resistor collector resistor determine output. adjust VOH: Adjust level same amount varying VCC. output levels will follow changes ratio. adjust only: Adjust level independently level increasing decreasing collector load resistance. Note that level will also change slightly IBASE drop across collector load resistor. changed varying supply, therefore gate current through current source resistor. Device Specifics
NBSG16VS
NBSG16VS differential receiver/driver with variable output amplitude which controlled voltage applied VCRTL over range These VCTRL voltages produce corresponding output amplitudes over range (see Data Sheet Figure 11). SPICE model NBSG16VS simulates seven selected swings within output amplitude range adjusting seven voltages Table Simulation tr/tf represents worst case (fastest) edges. offset must applied voltages convert LVNECL LVPECL ratio.
NBSG53A, NBSG72A, NBSG86A
NBSG53A, NBSG72A, NBSG86A multifunctional differential GigaComm devices with Output Level Select (OLS) capability. input used program peak-to-peak output amplitude between five discrete steps. When simulating output NBSG53A, NBSG72A, NBSG86A, Table value from line obtain desired output amplitude swing.
Table Required Selected Output Amplitudes NBSG16VS
Output Amplitude (mV) 0.865 0.98 1.06 1.15 1.23 1.38 1.42 1.46
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AND8077/D
Summary information included this provides adequate information SPICE level system interconnect simulation. block diagram Figure illustrates typical situation, which modeled using information this kit. Device input output models presented Table
Line Delay Driver Output
Minimum Trace Delay Receiver Input
Figure Typical Application SPICE Modeling Table GigaComm Input/Output Buffer Selector Guide
Device NB7L11M NB7L14M NB7L86M NBSG11 NBSG14 NBSG16 NBSG16VS NBSG16M NBSG53A NBSG72A NBSG86A Function 2.5/3.3 Differential Clock/Data Driver with Outputs 2.5/3.3 Differential Clock/Data Driver with Outputs 2.5/3.3 Differential Smart Gate with Outputs 2.5/3.3 Differential Clock Driver with RSECL Outputs 2.5/3.3 Differential Receiver/Driver with RSECL Outputs 2.5/3.3 Differential Receiver/Driver with RSECL Outputs 2.5/3.3 Differential Receiver/Driver with Variable Output Swing 2.5/3.3 Differential Receiver/Driver 2.5/3.3 Selectable Differential Clock Data Flip-Flop/Clock Divider with Reset 3.5/3.3 Differential Crosspoint Switch with 2.5/3.3 Differential Smart Gate with Input Model SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF SG_INBUF Output Model SG_OBUF_02 SG_OBUF_02 SG_OBUF_02 SG_OBUF_01 SG_OBUF_01 SG_OBUF_01 SG_OBUF_01* SG_0BUF_02 SG_OBUF_01* SG_OBUF_01* SG_OBUF_01*
*Note: Device Specifics Table Details.
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AND8077/D
R022 R011 TNSGB TNSGB TNSGB D01u D01d D020u D020d Input Buffer
D011u D011d 39.5m 753.3 C01a 51.12f C01b 62.48f
D02u D02d 39.5m
753.3 C02a 51.12f Package
C02b 62.48f
Input
0.025 0.025 0.075
0.025 0.025 0.075
1.18
1.18
Figure Simplified Input Circuitry SG_INBUF .SUBCKT SG_INBUF Q_Q11 TNSGB Q_Q22 TNSGB Q_Q33 TNSGB R_R011 R_R022 R_R33 R_Rb1 R_Rb2 R_R01 39.5m R_R02 39.5m L_L01 753.3pH L_L02 753.3pH D_D01d D_D011d D_D02d D_D020d D_D01u D_D011u D_D02u D_D020u C_C01a 51.12f C_C02a 51.12f C_C01b 62.48f C_C02b 62.48f V_VCC 3.3Vdc V_VCS 1.18Vdc V_VEE 0Vdc V_V1 PULSE 0.025n 0.025n 0.075n 0.2n V_V2 PULSE 0.025n 0.025n 0.075n 0.2n .END SG_INBUF
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TNSGB TNSGB Output Buffer
D10u D10d D111u D111d Output
TNSGC
D100u D100d 39.5m C10a 51.12f D11u D11d 753.3 C10b 62.48f
TNSGC
TNSGB
39.5m
C11b 62.48f
753.3 C11a 51.12f Package
Typical Termination
0.025 0.025 0.475
0.025 0.025 0.475
1.18
Figure Simplified Output Signal Buffer Circuitry SG_OBUF_01 .SUBCKT SG_OBUF_01 Q_Q1 TNSGB Q_Q2 TNSGB Q_Q3 TNSGB Q_Q4 TNSGC Q_Q5 TNSGC R_R1 R_R2 R_R3 R_R4 R_R5 R_R6 R_R10 39.5m R_R11 39.5m C_C10b 62.48f C_C11a 51.12f C_C11b 62.48f C_C10a 51.12f L_L10 753.3pH L_L11 753.3pH D_D111d D_D111u D_D100u D_D10u D_D11u D_D100d D_D10d D_D11d V_VCC 3.3Vdc V_VCS 1.18Vdc V_VTT 1.3Vdc V_VEE 0Vdc V_V1 PULSE 0.025n 0.025n 0.075n 0.2n V_V2 PULSE 0.025n 0.025n 0.075n 0.2n T_T1 Z0=50 TD=80ps T_T2 Z0=50 TD=80ps .END SG_OBUF_01
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AND8077/D
2.2980
2.2800
2.100
2.000
1.900
1.817 14.13 14.40 14.80 15.20 TIME 15.60 16.00
Figure Typical Output Waveform SG_OBUF_01 Voutpp 2.288 Vol=1.835
2.2200 2.2000
2.1000
2.0000
1.9000 1.838 15.208 15.300 15.400 TIME 15.500 15.600 15.700
Figure Typical Output Waveform SG_OBUF_01 Voutpp 2.26 1.84
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AND8077/D
Output Buffer Output Package Typical Termination 39.5m C10a 51.12f TNSGB TNSGB D111u D111d TNSGB 0.025 0.025 0.475
D10u D10d
D100u D100d 753.3 C10b 62.48f
D11u D11d
39.5m
C11b 62.48f
TNSGB
753.3 C11a 51.12f
0.025 0.025 0.475
Figure Simplified Output Signal Buffer Circuitry SG_OBUF_02 .SBUCKT SG_OBUF02 Q_Q1 TNSGB Q_Q2 TNSGB Q_Q3 TNSGB Q_Q4 TNSGB R_R1 R_R2 R_R3 R_R4 R_R10 39.5m R_R11 39.5m L_L10 753.3pH L_L11 753.3pH C_C10b 62.48f C_C10a 51.12f C_C11a 51.12f C_C11b 62.48f D_D10d D_D11d D_D111u D_D111d D_D100u D_D10u D_D11u D_D100d V_VEE 0Vdc V_VCC 3.3Vdc I_I1 16mAdc V_V1 PULSE 0.025n 0.025n 0.475n V_V2 PULSE 0.025n 0.025n 0.475n .END SG_OBUF02
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AND8077/D
3.2970
3.2800
3.1000
3.000
2.9130 28.541 29.000 29.500 30.000 TIME 30.500 31.000 31.387
Figure Typical Output Waveform SG_OBUF_02 Voutpp 3.29 2.93
3.3000
3.2000
3.1000
3.0000
2.9060 24.9 25.0 25.1 TIME 25.2 25.3 25.4
Figure Typical Output Waveform SG_OBUF_02 Voutpp 3.29 2.92
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AND8077/D
*RPU 36.5 *RPD
Pulldown Resistor
device data sheet
Figure Input .SUBCKT IN_ESD 36.5K .ENDS IN_ESD
Figure Output .SUBCKT OUT_ESD .ENDS OUT_ESD ***********Transistor Diod Models GigaComm******************** .MODEL TNSGC (IS=1.47e-16 BF=180 NF=1 VAF=96.3 IKF=1.62e-01 ISE=2.96e-15 NE=2.5 BR=20.2 VAR=2.76 IKR=1.34e-02 ISC=2.14e-16 NC=1.426 RB=25 IRB=1.50e-03 RBM=4 RE=1 RC=7 CJE=3.34e-15 VJE=.8867 MJE=.2868 TF=2.00e-12 ITF=0.25e-01 XTF=0.7 VTF=0.35 PTF=20 TR=0.5e-9 CJC=1.08e-15 VJC=0.632 MJC=0.301 XCJC=.3 CJS=8.12e-16 VJS=.4193 MJS=0.256 EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9) .MODEL TNSGB (IS=2.18e-17 BF=179 NF=1 VAF=96.5 IKF=2.42e-02 ISE=3.83e-16 NE=2.5 BR=20.4 VAR=2.76 IKR=1.98e-03 ISC=2.91e-17 NC=1.426 RB=55 IRB=1.12e-04 RBM=48 RE=6 RC=11 CJE=4.98e-16 VJE=.8867 MJE=.2868 TF=2.00e-12 ITF=0.4e-02 XTF=0.7 VTF=0.6 PTF=20 TR=0.5e-9 CJC=1.55e-16 VJC=0.632 MJC=0.301 XCJC=0.3 CJS=1.71e-16 VJS=.4193 MJS=0.256 EG=1.119 XTI=3.999 XTB=0.8826 FC=0.9) .MODEL (IS=9.99E-21 CJO=65.2E-15 RS=50.1 VJ=0.82 M=0.25
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AND8077/D
D10u D10d D111u D111d Output D100u D100d 39.5m C10a 51.12f D11u D11d 753.3 C10b 62.48f
TNSGC
TNSGB TNSGB Output Buffer TNSGB
TNSGC
39.5m
C11b 62.48f
753.3 C11a 51.12f Package
R022 R011 TNSGB TNSGB TNSGB D01u D01d
D011u D011d D020u D020d D02u D02d 39.5m 39.5m 753.3 C01a 51.12f C01b 62.48f
753.3 C02a 51.12f Package C02b 62.48f
Typical Termination
Input Buffer
Input
0.025 0.025 0.475
0.025 0.025 0.475
1.18
Figure Example Typical Interconnect Circuit
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AND8077/D
2.2000
2.0000
1.0000
13.626
14.000
14.500
15.000
15.496
TIME Figure Output Waveform Interconnect Example Shown Figure (Frequency GHz, Voutpp
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AND8077/D
Package Models Package: PBGA Model pins Note: model assume ground plane below package resistance model calculated PBGA drawing: Case Outline Conductor number-pin designation cross reference: Conductor number lumps: COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O N15I N15O N16I N16O BD_GND N01I N01C 1.640e-01 N01C BD_GND 6.333e-14 N01C N01O 8.325e-10 N02I N02C 8.500e-02 N02C BD_GND 6.275e-14 N02C N02O 4.373e-10 N03I N03C 8.500e-02 N03C BD_GND 6.016e-14 N03C N03O 4.361e-10 N04I N04C 1.640e-01 N04C BD_GND 6.660e-14 N04C N04O 8.264e-10 N05I N05C 8.600e-02 N05C BD_GND 5.632e-14 N05C N05O 4.274e-10 N06I N06C 8.600e-02 N06C BD_GND 5.457e-14 N06C N06O 3.049e-10 N07I N07C 8.600e-02 N07C BD_GND 5.036e-14 N07C N07O 3.049e-10 http://onsemi.com
AND8077/D
K0102 C0102 K0103 K0105 C0105 K0106 C0106 K0107 K0109 K0116 K0203 C0203 K0204 K0205 K0206 C0206 K0207 K0304 C0304 K0305 K0306 K0307 C0307 K0308 K0406 K0407 C0407 K0408 C0408 K0412 K0413 K0506 C0506 K0507 K0509 N08I N08C N08C N09I N09C N09C N10I N10C N10C N11I N11C N11C N12I N12C N12C N13I N13C N13C N14I N14C N14C N15I N15C N15C N16I N16C N16C N01C N01C N01C N02C N02C N03C N03C N04C N04C N05C N08C BD_GND N08O N09C BD_GND N09O N10C BD_GND N10O N11C BD_GND N11O N12C BD_GND N12O N13C BD_GND N13O N14C BD_GND N14O N15C BD_GND N15O N16C BD_GND N16O N02C N05C N06C N03C N06C N04C N07C N07C N08C N06C 8.600e-02 6.380e-14 4.280e-10 8.600e-02 6.423e-14 4.283e-10 8.600e-02 5.121e-14 3.052e-10 8.600e-02 4.875e-14 3.048e-10 8.600e-02 6.326e-14 4.274e-10 1.640e-01 6.028e-14 8.314e-10 8.500e-02 5.872e-14 4.373e-10 8.500e-02 6.334e-14 4.362e-10 1.640e-01 6.609e-14 8.292e-10 0.2743 6.160e-14 0.0734 0.2311 2.312e-14 0.1381 8.262e-14 0.0626 0.0894 -0.0521 0.2951 6.784e-14 0.0682 0.1439 0.1457 3.281e-14 0.1096 0.2694 5.694e-14 0.0515 0.1089 0.1457 3.349e-14 0.1395 0.0608 0.1369 8.300e-14 0.2289 2.259e-14 0.0932 -0.0518 0.1906 8.897e-14 0.0682 0.2806
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AND8077/D
C0509 N05C K0510 K0513 K0607 K0608 K0609 K0610 K0611 K0708 C0708 N07C K0710 K0711 K0712 K0811 K0812 C0812 N08C K0816 K0910 C0910 N09C K0911 K0913 C0913 N09C K0914 K0915 K1011 K1012 K1013 C1013 N10C K1014 C1014 N10C K1015 K1016 K1112 C1112 N11C K1113 K1114 K1115 C1115 N11C K1116 C1116 N11C K1215 K1216 C1216 N12C K1314 C1314 N13C K1315 K1415 C1415 N14C K1416 K1516 C1516 N15C .ENDS PACKAGE N09C N08C N12C N10C N13C N13C N14C N12C N15C N16C N16C N14C N15C N16C 6.387e-14 0.0534 0.0893 0.0808 0.0674 0.0536 0.0713 0.0503 0.1896 8.678e-14 0.0502 0.0718 0.0546 0.0549 0.2847 6.539e-14 0.0933 0.1903 8.903e-14 0.0679 0.2309 2.387e-14 0.1436 0.0510 0.0806 0.0675 0.1376 8.341e-14 0.1456 3.117e-14 0.1090 0.0609 0.1894 8.742e-14 0.0620 0.1089 0.1452 3.130e-14 0.1362 8.281e-14 0.1398 0.2292 2.266e-14 0.2736 5.822e-14 0.0724 0.2948 6.859e-14 0.0681 0.2704 6.064e-14
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AND8077/D
Package: Model pins Note: model assume ground plane below package model assume flag grounded model based GigaComm device 1.475mm 1.475mm Wire bond parasitics lumped with lead frame post. Lump element equivalent model valid Lead Frame drawing: ASAT Case Outline: file 16qfn3x3.LC Package: GigaComm Model pins Conductor number-pin designation cross reference: Conductor number lumps: COMPRESSION SUBCIRCUITS PERFORMED: discard ratio 0.050 .SUBCKT PACKAGE N01I N01O N02I N02O N03I N03O N04I N04O N05I N05O N06I N06O N07I N07O N08I N08O N09I N09O N10I N10O N11I N11O N12I N12O N13I N13O N14I N14O N15I N15O N16I N16O BD_GND N01I N01C 4.300e-02 C01a N01C BD_GND 6.674e-14 C01b N01O BD_GND 8.157e-14 N01C N01O 8.418e-10 N02I 3.950e-02 C02a N02C BD_GND 5.153e-14 C02b N02O BD_GND 6.298e-14 N02C N02O 7.557e-10 N03I N03C 3.950e-02 C03a N03C BD_GND 5.364e-14 C03b N03O BD_GND 6.556e-14 N03C N03O 7.550e-10 N04I N04C 4.300e-02 C04a N04C BD_GND 6.687e-14 C04b N04O BD_GND 8.173e-14 http://onsemi.com
AND8077/D
C05a C05b C06a C06b C07a C07b C08a C08b C09a C09b C10a C10b C11a C11b C12a C12b C13a C13b C14a C14b C15a C15b C16a C16b K0102 C0102a C0102b K0103 K0115 K0116 C0116a C0116b K0203 C0203a C0203b K0204 K0216 N04C N05I N05C N05O N05C N06I N06C N06O N06C N07I N07C N07O N07C N08I N08C N08O N08C N09I N09C N09O N09C N10I N10C N10O N10C N11I N11C N11O N11C N12I N12C N12O N12C N13I N13C N13O N13C 777N14I N14C N14O N14C N15I N15C N15O N15C N16I N16C N16O N16C N01C N01O N01C N01O N02C N02O N04O N05C BD_GND BD_GND N05O N06C BD_GND BD_GND N06O N07C BD_GND BD_GND N07O N08C BD_GND BD_GND N08O N09C BD_GND BD_GND N09O N10C BD_GND BD_GND N10O N11C BD_GND BD_GND N11O N12C BD_GND BD_GND N12O N13C BD_GND BD_GND N13O N14C BD_GND BD_GND N14O N15C BD_GND BD_GND N15O N16C BD_GND BD_GND N16O N02C N02O N16C N16O N03C N03O 8.427e-10 4.300e-02 6.633e-14 8.107e-14 8.451e-10 3.950e-02 5.202e-14 6.358e-14 7.560e-10 3.950e-02 5.243e-14 6.408e-14 7.551e-10 4.300e-02 6.682e-14 8.168e-14 8.432e-10 4.300e-02 6.606e-14 8.074e-14 8.418e-10 3.950e-02 5.112e-14 6.248e-14 7.533e-10 3.950e-02 5.166e-14 6.314e-14 7.524e-10 4.300e-02 6.786e-14 8.294e-14 8.415e-10 4.300e-02 6.628e-14 8.101e-14 8.426e-10 3.950e-02 5.238e-14 6.402e-14 7.536e-10 3.950e-02 5.310e-14 6.490e-14 7.514e-10 4.300e-02 6.692e-14 8.179e-14 8.412e-10 0.1711 1.740e-14 2.126e-14 0.0676 0.0549 0.1085 4.797e-15 5.863e-15 0.1574 1.622e-14 1.983e-14 0.0690 0.0555
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AND8077/D
K0304 C0304a N03C C0304b N03O K0305 K0405 C0405a N04C C0405b N04O K0406 K0506 C0506a N05C C0506b N05O K0507 K0607 C0607a N06C C0607b N06O K0608 K0708 C0708a N07C C0708b N07O K0709 K0809 C0809a N08C C0809b N08O K0810 K0910 C0910a N09C C0910b N09O K0911 K1011 C1011a N10C C1011b N10O K1012 K1112 C1112a N11C C1112b N11O K1113 K1213 C1213a N12C C1213b N12O K1214 K1314 C1314a N13C C1314b N13O K1315 K1415 C1415a N14C C1415b N14O K1416 K1516 C1516a N15C C1516b N15O .ENDS PACKAGE N04C N04O N05C N05O N06C N06O N07C N07O N08C N08O N09C N09O N10C N10O N11C N11O N12C N12O N13C N13O N14C N14O N15C N15O N16C N16O 0.1713 1.744e-14 2.131e-14 0.0563 0.1098 4.747e-15 5.803e-15 0.0560 0.1723 1.739e-14 2.125e-14 0.0695 0.1578 1.633e-14 1.996e-14 0.0676 0.1708 1.748e-14 2.136e-14 0.0551 0.1085 4.797e-15 5.863e-15 0.0555 0.1711 1.734e-14 2.119e-14 0.0684 0.1574 1.613e-14 1.972e-14 0.0673 0.1711 1.751e-14 2.139e-14 0.0558 0.1097 4.797e-15 5.863e-15 0.0561 0.1715 1.748e-14 2.136e-14 0.0678 0.1573 1.636e-14 2.000e-14 0.0682 0.1707 1.748e-14 2.137e-14
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AND8077/D
GigaComm trademark Semiconductor Components Industries, (SCILLC).` Adobe, Acrobat, Reader registered trademarks Adobe Systems Incorporated.
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AND8077/D

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