74HCT14 used level converter interfacing NMOS outputs high-speed CMOS

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74HCT14 used level converter interfacing NMOS outputs high-speed CMOS

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74HCT14 Schmitt-Trigger Inverter with LSTTL Compatible Inputs
74HCT14 used level converter interfacing NMOS outputs high-speed CMOS inputs. HCT14 useful "square slow input rise fall times. hysteresis voltage Schmitt trigger, HCT14 finds applications noisy environments.
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SOIC-14 SUFFIX CASE 751A HCT14G AWLYWW
Output Drive Capability: LSTTL Loads TTL/NMOS-Compatible Input Levels Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: Compliance With JEDEC Standard Requirements Performance: 2000 Machine Model Chip Complexity: FETs Equivalent Gates These Pb-Free Devices
TSSOP-14 SUFFIX CASE 948G ALYW
HCT14 Device Code Assembly Location Wafer Year Work Week Pb-Free Package (Note: Microdot either location)
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
Semiconductor Components Industries, LLC, 2007
March, 2007 Rev.
Publication Order Number: 74HCT14/D
74HCT14
ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Input Output
ORDERING INFORMATION
Device 74HCT14DR2G 74HCT14DTR2G Package SOIC-14 (Pb-Free) TSSOP-14* Shipping 2500 Tape Reel
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D. *This package inherently Pb-Free.
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74HCT14
MAXIMUM RATINGS
Symbol IGND TSTG VESD ILatchup Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink Current Supply Current Supply Ground Current Ground Storage Temperature Range Lead Temperature, from Case Seconds Junction Temperature under Bias Thermal Resistance Power Dissipation Still 85_C Moisture Sensitivity Flammability Rating Withstand Voltage Latchup Performance Oxygen Index: Human Body Model (Note Machine Model (Note Above Below 85_C (Note SOIC TSSOP SOIC TSSOP Parameter (Referenced GND) (Referenced GND) (Referenced GND) Value *0.5 )7.0 *0.5 )0.5 *0.5 )0.5 )150 )150 Level 0.125 >2000 >200 $300 Unit _C/W
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Tested EIA/JESD22-A114-A. Tested EIA/JESD22-A115-A. Tested EIA/JESD78. high frequency heavy load considerations, Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Supply Voltage Input Voltage, Output Voltage Operating Temperature, Package Types Input Rise Fall Time (Figure Parameter (Referenced GND) (Referenced GND) )125 (Note Unit
Limit when VCC, Unused inputs left open. inputs must tied high-logic voltage level low-logic input voltage level.
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74HCT14
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Temperature Limit Symbol VT)max VT)min VT*max VT*min Parameter Maximum Positive-Going Input Threshold Voltage Minimum Positive-Going Input Threshold Voltage Maximum Negative-Going Input Threshold Voltage Minimum Negative-Going Input Threshold Voltage Maximum Hysteresis Voltage Minimum Hysteresis Voltage Minimum High-Level Output Voltage Test Conditions |Iout| |Iout| |Iout| |Iout| |Iout| |Iout| VT*min |Iout| VT*min |Iout| Maximum Low-Level Output Voltage VT)max |Iout| VT)max |Iout| Maximum Input Leakage Current Maximum Quiescent Supply Current (per package) Iout 3.98 0.26 $0.1 3.84 0.33 $1.0 $1.0 *55_C 25_C v85_C v125_C Unit
w*55_C DICC Additional Quiescent Supply Current Input GND, Other Inputs lout
25_C 125_C
Information typical parametric values found Semiconductor High-Speed CMOS Data Book (DL129/D).
CHARACTERISTICS Input
Guaranteed Limit *55_C 25_C Symbol Parameter Test Conditions Figures v85_C v125_C Unit
tPLH, tPHL tTLH, tTHL
Maximum Propagation Delay, Input Output Maximum Output Transition Time, Output
$10% Input $10% Input
propagation delays with loads other than information typical parametric values, Semiconductor High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance, Inverter (Note
Used determine no-load dynamic power consumption: Semiconductor High-Speed CMOS Data Book (DL129/D).
load considerations,
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74HCT14
INPUT
tPLH
tPHL
OUTPUT
tTLH
tTHL
Figure Switching Waveforms
TEST POINT OUTPUT DEVICE UNDER TEST
*Includes probe capacitance.
Figure Test Circuit
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74HCT14
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE
0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7.04 0.58
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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74HCT14
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE
0.10 (0.004) 0.15 (0.006)
0.25 (0.010)
IDENT.
DETAIL
0.15 (0.006)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
SECTION
0.10 (0.004) SEATING
PLANE
DETAIL
SOLDERING FOOTPRINT*
7.06
0.36
1.26
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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0.65 PITCH
DIMENSIONS: MILLIMETERS
74HCT14
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74HCT14/D

74HCT14 used level converter interfacing NMOS outputs high-speed CMOS

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