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With LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS 7
Top Searches for this datasheet74HCT08 Quad 2-Input Gate With LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS 74HCT08 identical pinout LS08. device TTL-compatible inputs. SOIC-14 SUFFIX CASE 751A HCT08G AWLYWW Output Drive Capability: LSTTL Loads TTL/NMOS-Compatible Input Levels Outputs Directly Interface CMOS, NMOS Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance With JEDEC Standard Requirements Performance: 2000 Machine Model Chip Complexity: FETs Equivalent Gates These Pb-Free Devices LOGIC DIAGRAM TSSOP-14 SUFFIX CASE 948G ALYW HCT08 Device Code Assembly Location Wafer Year Work Week Pb-Free Package (Note: Microdot either location) FUNCTION TABLE Inputs Output Pinout: 14-Lead Packages (Top View) ORDERING INFORMATION detailed ordering shipping information package dimensions section page this data sheet. Semiconductor Components Industries, LLC, 2007 March, 2007 Rev. Publication Order Number: 74HCT08/D 74HCT08 ORDERING INFORMATION Device 74HCT08DR2G 74HCT08DTR2G Package SOIC-14 (Pb-Free) TSSOP-14* Shipping 2500/Tape Reel information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D. *This package inherently Pb-Free. MAXIMUM RATINGS Symbol Iout Tstg Vout Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Output Current, Supply Current, Pins Power Dissipation Still Air, Storage Temperature Lead Temperature, from Case Seconds SOIC TSSOP Package SOIC Package TSSOP Package This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open. Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Derating SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Vin, Vout Parameter Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure +125 1000 Unit http://onsemi.com 74HCT08 CHARACTERISTICS (Voltages Referenced GND) Symbol Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Condition Vout 0.1V |Iout| 20mA Vout 0.1V |Iout| 20mA |Iout| 20mA Maximum Low-Level Output Voltage |Iout| 20mA Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current Iout 2.4V, Input GND, Other Inputs Iout |Iout| 4.0mA |Iout| 4.0mA Guaranteed Limit 25°C 3.98 0.26 ±0.1 85°C 3.84 0.33 ±1.0 125°C 3.70 0.40 ±1.0 Unit DICC -55°C 125°C Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Total Supply Current DICC. CHARACTERISTICS 50pF, Input 6ns) Symbol tPLH, tPHL tTLH, tTHL Parameter Maximum Propagation Delay, Input Output (Figures Maximum Output Transition Time, Output (Figures Maximum Input Capacitance Guaranteed Limit 25°C 85°C 125°C Unit NOTE: propagation delays with loads other than information typical parametric values, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Buffer)* Used determine no-load dynamic power consumption: Semiconductor High-Speed CMOS Data Book (DL129/D). load considerations, Chapter http://onsemi.com 74HCT08 INPUT tPLH OUTPUT tTLH tTHL tPHL Figure Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST *Includes probe capacitance Figure Test Circuit Figure Expanded Logic Diagram (1/4 Device) http://onsemi.com 74HCT08 PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE 0.25 (0.010) NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. SEATING PLANE 0.25 (0.010) MILLIMETERS 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50 INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7.04 0.58 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 74HCT08 PACKAGE DIMENSIONS TSSOP-14 CASE 948G-01 ISSUE 0.10 (0.004) 0.15 (0.006) 0.25 (0.010) IDENT. DETAIL 0.15 (0.006) SECTION 0.10 (0.004) SEATING PLANE DETAIL SOLDERING FOOTPRINT* 7.06 0.36 1.26 *For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 0.65 PITCH DIMENSIONS: MILLIMETERS 74HCT08 Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. 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