74HC595 consists 8-bit shift register 8-bit D-type latch with three-st
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74HC595 8-Bit Serial-Input/Serial Parallel-Output Shift Register with Latched 3-State Outputs
74HC595 consists 8-bit shift register 8-bit D-type latch with three-state parallel outputs. shift register accepts serial data provides serial output. shift register also provides parallel data 8-bit latch. shift register latch have independent clock inputs. This device also asynchronous reset shift register. HC595 directly interfaces with serial data port CMOS MPUs MCUs.
SOIC-16 SUFFIX CASE 751B TSSOP-16 SUFFIX CASE 948F ALYW HC595G AWLYWW
Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Performance: 2000 Machine Model Chip Complexity: FETs Equivalent Gates Improvements over HC595 Improved Propagation Delays Lower Quiescent Power Improved Input Noise Latchup Immunity These Pb-Free Devices
HC595 Device Code Assembly Location Wafer Year Work Week Pb-Free Package (Note: Microdot either location)
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
Semiconductor Components Industries, LLC, 2007
March, 2007 Rev.
Publication Order Number: 74HC595/D
74HC595
LOGIC DIAGRAM
SERIAL DATA INPUT SHIFT REGISTER LATCH SHIFT CLOCK RESET LATCH CLOCK OUTPUT ENABLE PARALLEL DATA OUTPUTS
ASSIGNMENT
OUTPUT ENABLE LATCH CLOCK SHIFT CLOCK RESET
SERIAL DATA OUTPUT
ORDERING INFORMATION
Device 74HC595DR2G 74HC595DTR2G Package SOIC-16 (Pb-Free) TSSOP-16* Shipping 2500 Tape Reel 2500 Tape Reel
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D. *This package inherently Pb-Free.
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74HC595
MAXIMUM RATINGS
Symbol Iout Tstg Vout Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Output Current, Supply Current, Pins Power Dissipation Still Air, Storage Temperature Lead Temperature, from Case Seconds (SOIC TSSOP Package) SOIC Package TSSOP Package
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Derating SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Vin, Vout Parameter Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure 1000 Unit
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74HC595
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol Parameter Minimum High-Level Input Voltage Test Conditions Vout |Iout| |Iout| |Iout| |Iout| |Iout| |Iout| |Iout| |Iout| IIoutI IIoutIv |Iout| IIoutI IIoutIv Guaranteed Limit 25_C 3.15 1.35 2.48 3.98 5.48 0.26 0.26 0.26 2.98 3.98 5.48 0.26 0.26 0.26 ±0.1 ±0.25 85_C 3.15 1.35 2.34 3.84 5.34 0.33 0.33 0.33 2.34 3.84 5.34 0.33 0.33 0.33 ±1.0 ±2.5 125_C 3.15 1.35 ±1.0 ±2.5 Unit
Maximum Low-Level Input Voltage
Vout |Iout|
Minimum High-Level Output Voltage,
|Iout|
Maximum Low-Level Output Voltage,
|Iout|
Minimum High-Level Output Voltage,
IIoutI
Maximum Low-Level Output Voltage,
IIoutI
Maximum Input Leakage Current Maximum Three-State Leakage Current, Maximum Quiescent Supply Current (per Package)
Output High-Impedance State Vout lout
NOTE: Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC595
ELECTRICAL CHARACTERISTICS Input
Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures Guaranteed Limit 25_C 85_C 125_C Unit
tPLH, tPHL
Maximum Propagation Delay, Shift Clock (Figures
tPHL
Maximum Propagation Delay, Reset (Figures
tPLH, tPHL
Maximum Propagation Delay, Latch Clock (Figures
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable (Figures
tPZL, tPZH
Maximum Propagation Delay, Output Enable (Figures
tTLH, tTHL
Maximum Output Transition Time, (Figures
tTLH, tTHL
Maximum Output Transition Time, (Figures
Cout
Maximum Input Capacitance Maximum Three-State Output Capacitance (Output High-Impedance State),
NOTE: propagation delays with loads other than information typical parametric values, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Package)* Used determine no-load dynamic power consumption: VCC2 load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC595
TIMING REQUIREMENTS (Input
Symbol Parameter Minimum Setup Time, Serial Data Input Shift Clock (Figure Guaranteed Limit 25_C -55_C 1000 85_C 1000 125_C 1000 Unit
Minimum Setup Time, Shift Clock Latch Clock (Figure
Minimum Hold Time, Shift Clock Serial Data Input (Figure
trec
Minimum Recovery Time, Reset Inactive Shift Clock (Figure
Minimum Pulse Width, Reset (Figure
Minimum Pulse Width, Shift Clock (Figure
Minimum Pulse Width, Latch Clock (Figure
Maximum Input Rise Fall Times (Figure
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74HC595
FUNCTION TABLE
Inputs Serial Input Shift Clock Latch Clock Output Enable Shift Register Contents DSRA; SRNSRN+1 Resulting Function Latch Register Contents SRNLRN Serial Output SRGSRH Parallel Outputs
Operation Reset shift register Shift data into shift register Shift register remains unchanged Transfer shift register contents latch register Latch register remains unchanged Enable parallel outputs Force outputs into high impedance state
Reset
Low-to-High High-to-Low
Enabled
shift register contents latch register contents
data logic level remains unchanged
depends Reset Shift Clock inputs depends Latch Clock input
DESCRIPTIONS
INPUTS (Pin Output Enable (Pin
Serial Data Input. data this shifted into 8-bit serial shift register.
CONTROL INPUTS Shift Clock (Pin
Active-low Output Enable. this input allows data from latches presented outputs. high this input forces outputs (QA-QH) into high-impedance state. serial output affected this control unit.
OUTPUTS (Pins
Shift Register Clock Input. low- to-high transition this input causes data Serial Input shifted into 8-bit shift register.
Reset (Pin
Noninverted, 3-state, latch outputs.
(Pin
Active-low, Asynchronous, Shift Register Reset Input. this resets shift register portion this device only. 8-bit latch affected.
Latch Clock (Pin
Noninverted, Serial Data Output. This output eighth stage 8-bit shift register. This output does have three-state capability.
Storage Latch Clock Input. low-to-high transition this input latches shift register data.
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74HC595
SWITCHING WAVEFORMS
SHIFT CLOCK 1/fmax tPLH OUTPUT tTLH tTHL tPHL OUTPUT SHIFT CLOCK RESET tPHL trec
Figure
tPLH QA-QH OUTPUTS tTLH tTHL tPHL OUTPUT ENABLE
Figure
tPZL tPZH OUTPUT tPHZ tPLZ HIGH IMPEDANCE HIGH IMPEDANCE
LATCH CLOCK
OUTPUT
Figure
SHIFT CLOCK
Figure
LATCH CLOCK
VALID SERIAL INPUT SWITCH CLOCK
Figure
Figure
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT CONNECT WHEN TESTING tPLZ tPZL. CONNECT WHEN TESTING tPHZ tPZH.
*Includes probe capacitance
*Includes probe capacitance
Figure
Figure
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74HC595
EXPANDED LOGIC DIAGRAM
OUTPUT ENABLE LATCH CLOCK SERIAL DATA INPUT
PARALLEL DATA OUTPUTS
SHIFT CLOCK
RESET
SERIAL DATA OUTPUT
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74HC595
TIMING DIAGRAM
SHIFT CLOCK SERIAL DATA INPUT RESET LATCH CLOCK OUTPUT ENABLE SERIAL DATA OUTPUT NOTE: implies that output high-impedance state.
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74HC595
PACKAGE DIMENSIONS
SOIC-16 CASE 751B-05 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
SOLDERING FOOTPRINT*
6.40
1.12
0.58
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC595
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE
0.10 (0.004) 0.15 (0.006)
SECTION
IDENT.
0.15 (0.006)
DETAIL
0.10 (0.004) SEATING
PLANE
DETAIL
SOLDERING FOOTPRINT*
7.06
0.36
1.26
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH. PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC595
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74HC595/D
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