Download

PDF Abstract Text:

74HC138 1-of-8 Decoder / Demultiplexer

Features http://onsemi.com MARKING DIAGRAMS

74HC138 1-of-8 Decoder / Demultiplexer
High-Performance Silicon-Gate CMOS
The 74HC138 is identical in pinout to the LS138. The device inputs are compatible with standard CMOS outputs with pullup resistors, they are compatible with LSTTL outputs. The HC138 decodes a three-bit Address to one-of-eight active-low outputs. This device features three Chip Select inputs, two active-low and one active-high to facilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states.
Features http://onsemi.com MARKING DIAGRAMS
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
March, 2007 - Rev. 1
Publication Order Number: 74HC138 / D
74HC138
A0 A1 A2 CS2 CS3 CS1 Y7 GND
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
ADDRESS INPUTS
ACTIVE-LOW OUTPUTS
Figure 1. Pin Assignment
CHIP- SELECT INPUTS
CS1 CS2 CS3
Figure 2. Logic Diagram FUNCTION TABLE
ORDERING INFORMATION
Device 74HC138DR2G 74HC138DTR2G Package SOIC-16 (Pb-Free) TSSOP-16 Shipping 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011 / D. This package is inherently Pb-Free.
http://onsemi.com
74HC138
MAXIMUM RATINGS
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
http://onsemi.com
74HC138
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Output Voltage
Iin ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129 / D).
tPLH, tPHL
Maximum Propagation Delay, CS1 to Output Y (Figures 2 and 4)
tPLH, tPHL
Maximum Propagation Delay, CS2 or CS3 to Output Y (Figures 3 and 4)
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 2 and 4)
Maximum Input Capacitance
http://onsemi.com
74HC138
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
OUTPUT Y
Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
PIN DESCRIPTIONS
ADDRESS INPUTS A0, A1, A2 (Pins 1, 2, 3)
Address inputs. For any other combination of CS1, CS2, and CS3, the outputs are at a logic high.
OUTPUTS Y0 - Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Address inputs. These inputs, when the chip is selected, determine which of the eight outputs is active-low.
CONTROL INPUTS CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3 at a low level, the chip is selected and the outputs follow the
Active-low Decoded outputs. These outputs assume a low level when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not selected.
http://onsemi.com
74HC138
EXPANDED LOGIC DIAGRAM
http://onsemi.com
74HC138
PACKAGE DIMENSIONS
SOIC-16 CASE 751B-05 ISSUE K
SEATING PLANE
SOLDERING FOOTPRINT
16X 8X
1.27 PITCH 8 9
DIMENSIONS: MILLIMETERS
For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM / D.
http://onsemi.com
74HC138
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE B
16X K REF
0.10 (0.004) 0.15 (0.006) T U
SECTION N-N J N
PIN 1 IDENT. 1 8
0.15 (0.006) T U
N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
DETAIL E
SOLDERING FOOTPRINT
For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM / D.
http://onsemi.com
0.25 (0.010) M
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC138
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA / Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA / Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA / Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com / orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
74HC138 / D