74HC138 identical pinout LS138. device inputs compatible with standard

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74HC138 identical pinout LS138. device inputs compatible with standard

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74HC138 1-of-8 Decoder/ Demultiplexer
74HC138 identical pinout LS138. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. HC138 decodes three-bit Address one-of-eight active-low outputs. This device features three Chip Select inputs, active-low active-high facilitate demultiplexing, cascading, chip-selecting functions. demultiplexing function accomplished using Address inputs select desired device output; Chip Selects used data input while other Chip Selects held their active states.
SOIC-16 SUFFIX CASE 751B TSSOP-16 SUFFIX CASE 948F HC138 Device Code Assembly Location Wafer Year Work Week Pb-Free Package (Note: Microdot either location) ALYW HC138G AWLYWW
Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Performance: 2000 Machine Model Chip Complexity: FETs Equivalent Gates These Pb-Free Devices
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
Semiconductor Components Industries, LLC, 2007
March, 2007 Rev.
Publication Order Number: 74HC138/D
74HC138
ADDRESS INPUTS
ACTIVE-LOW OUTPUTS
Figure Assignment
CHIP- SELECT INPUTS
Figure Logic Diagram FUNCTION TABLE
Inputs Outputs CS1CS2
high level (steady state); level (steady state); don't care
ORDERING INFORMATION
Device 74HC138DR2G 74HC138DTR2G Package SOIC-16 (Pb-Free) TSSOP-16* Shipping 2500 Tape Reel 2500 Tape Reel
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D. *This package inherently Pb-Free.
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74HC138
MAXIMUM RATINGS
Symbol Iout Tstg Vout Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Output Current, Supply Current, Pins Power Dissipation Still Air, Storage Temperature Lead Temperature, from Case Seconds (SOIC TSSOP Package) SOIC Package TSSOP Package
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Derating SOIC Package: mW/_C from 125_C TSSOP Package: .W/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Vin, Vout Parameter Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure 1000 Unit
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74HC138
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol Parameter Minimum High-Level Input Voltage Test Conditions Vout |Iout| Guaranteed Limit -55_C 25_C 3.15 1.35 2.48 3.98 5.48 0.26 0.26 0.26 ±0.1 85_C 3.15 1.35 2.34 3.84 5.34 0.33 0.33 0.33 ±1.0 125_C 3.15 1.35 2.20 3.70 5.20 0.40 0.40 0.40 ±1.0 Unit
Maximum Low-Level Input Voltage
Vout |Iout|
Minimum High-Level Output Voltage
|Iout| |Iout| |Iout| |Iout|
Maximum Low-Level Output Voltage
|Iout| |Iout| |Iout| |Iout|
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
Iout
NOTE: Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
ELECTRICAL CHARACTERISTICS Input
Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input Output (Figures Guaranteed Limit -55_C 25_C 85_C 125_C Unit
tPLH, tPHL
Maximum Propagation Delay, Output (Figures
tPLH, tPHL
Maximum Propagation Delay, Output (Figures
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Maximum Input Capacitance
NOTE: propagation delays with loads other than information typical parametric values, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Package)* Used determine no-load dynamic power consumption: VCC2 load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC138
SWITCHING WAVEFORMS
VALID INPUT tPLH OUTPUT tPHL OUTPUT tTHL VALID INPUT tPHL tPLH
tTLH
Figure
Figure
TEST POINT INPUT CS2, tPLH DEVICE UNDER TEST OUTPUT
OUTPUT
tPHL
tTHL
tTLH
*Includes probe capacitance
Figure
Figure Test Circuit
DESCRIPTIONS
ADDRESS INPUTS (Pins
Address inputs. other combination CS1, CS2, CS3, outputs logic high.
OUTPUTS (Pins
Address inputs. These inputs, when chip selected, determine which eight outputs active-low.
CONTROL INPUTS CS1, CS2, (Pins
Chip select inputs. high level CS2, level, chip selected outputs follow
Active-low Decoded outputs. These outputs assume level when addressed chip selected. These outputs remain high when addressed chip selected.
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74HC138
EXPANDED LOGIC DIAGRAM
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74HC138
PACKAGE DIMENSIONS
SOIC-16 CASE 751B-05 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
SOLDERING FOOTPRINT*
6.40
1.12
0.58
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC138
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE
0.10 (0.004) 0.15 (0.006)
SECTION
IDENT.
0.15 (0.006)
DETAIL
0.10 (0.004) SEATING
PLANE
DETAIL
SOLDERING FOOTPRINT*
7.06
0.36
1.26
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH. PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC138
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74HC138/D

74HC138 identical pinout LS138. device inputs compatible with standard

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