This application note describes power management features Oki's ML67Q4
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ML67Q4050/Q4060 Series Power Considerations
This application note describes power management features Oki's ML67Q4050/51 ML67Q4060/61 Series devices. provides guide that shows these features maximize power consumption efficiency. Typical operating core current numbers well worst case current consumption figures parts presented under various conditions. ML67Q4050/51 ML67Q4060/61 identical except that ML67Q4050 extended interface. This additional signal block means that current consumption ML67Q4050/51 slightly higher than that ML67Q4060/61. This seen numbers presented page This application note should used conjunction with ML67Q4050/Q4060 Series User's Manual, Power Management document, sample software provided that comes with Board kit.
Contents This Application Note
Introduction ML67Q4050/Q4060 Series Power Modes Mode Typical Worst-Case Currents Peripheral Block Core Current Versus SYSCLK Frequency STOP Mode HALT Mode Current Consumption Conclusion Revision History
November, 2005
Application Note
ML67Q4050/Q4060 Series Power Considerations
ML67Q4050/Q4060 Series Power Modes
ML67Q4050/Q4060 Series devices support following three basic power modes control power dissipated devices during normal operation standby conditions. Figure depicts power management conceptualization ML67Q4050/Q4060 Series. details three modes explained following sections.
Mode STOP Mode HALT Mode Figure 1-1. ML67Q4050/Q4060 Series Power Modes
Mode
High-Speed Clock
Low-Speed Clock
Extremely Low-Speed Clock
Interrupt
HALT
STOP
Wake
HALT (CPUG) Mode
STOP Mode
Mode
flexible clock dividers used mode operating frequency considerably reduce power consumption part. some applications necessary part full speed time. mode clock dividers allows core clock reduced during times when application does require full performance processor. With help from sample software provided packaged with board, clock speeds reliably switched from Faster Slower visa versa provide more efficient system operation. Figure shows ML67Q4050/Q4060 Series clock tree, clock dividers, main blocks. Software programmable clock dividers provided both HCLK (the main clock) also clock (peripheral clock). example using APBDIV bits (CLKCNT 0xB700.0010), power conserved reducing APB_CLK operating frequency.
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November, 2005
ML67Q4050/Q4060 Series Power Considerations
Figure 2-2.
ML67Q4050/Q4060 Series Clock Architecture
Many peripheral blocks have clock dividers that used reduce power consumption when operating. example, block flexible divider that used select clock range APB_CLK/2 APB_CLK/2046. Furthermore, peripheral blocks that being used application disabled. This possible using peripheral clock control (PECLKCNT 0xB700.0000) peripheral reset control (PERSTCNT 0xB700.0004) registers. clock disabled using clock stop register (CLKSTP 0xB800.0004). Clocks PLL's turned optimize power consumption using clock control register (CLKCNT 0xB700.0010). User's Manual Chapter more details. Another power saving achieved turning (Test Interface Controller). block used testing enabled default after power Simply clock stop register (CLKSTP 0xB800.0004) disable.
Typical Worst-Case Currents
following tables show current (IDDO) ML67Q4050/51 ML67Q4060/61 devices. Table Table show typical (TYP) worst case (MAX) limits measured nominal worst case core voltages, using typical worst case silicon process indicated. Table Table show typical IDDO limits function SYSCLK frequency. measurements were taken with peripherals enabled being exercised software. This means using UART example, clock UART block enabled UART sending/receiving data generating interrupts. same applies other peripherals; they concurrently during worst case current measurements. These numbers were generated after comprehensive characterization evaluation parts guaranteed Oki.
November, 2005
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ML67Q4050/Q4060 Series Power Considerations
Table 2-1.
Mode ML67Q4050/51 Typical Maximum IDDO Current Limits (mA)
IDDO
Conditions VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, 33.333 MHz, process 25°C VDD_IO 3.6V, VDD_CORE VDD_PLL 2.75V, 33.333 MHz, process -40°C
CORE 49.90 76.00
13.78 30.00
6.56 14.00
TOTAL 70.24 120.00
Table 2-2. SYSCLK (MHz) 33.333
Mode ML67Q4050/51 Typical IDDO Current Versus Frequency IDDO Limits (mA) Conditions CORE 21.80 26.19 30.59 VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, process 25°C 34.98 39.38 43.78 49.90 4.69 6.23 7.76 9.30 10.83 12.37 13.78 3.29 3.64 4.00 4.50 5.15 5.80 5.56 TOTAL 29.78 36.06 42.35 48.78 55.36 61.94 70.23
Table 2-3.
Mode ML67Q4060/61 Typical Maximum IDDO Current Limits (mA)
IDDO
Conditions VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, 33.333 MHz, process 25°C VDD_IO 3.6V, VDD_CORE VDD_PLL 2.75V, 33.333 MHz, process -40°C
CORE 49.90 76.00
8.49 30.00
6.56 14.00
TOTAL 64.89 120.00
Table 2-4. SYSCLK (MHz) 33.333
Mode ML67Q4060/61 Typical IDDO Current Versus Frequency IDDO Limits (mA) Conditions CORE 21.80 26.19 30.59 VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, process 25°C 34.98 39.38 43.78 49.90 2.89 3.84 4.78 5.73 6.67 7.62 8.49 3.29 3.64 4.00 4.50 5.15 5.80 5.56 TOTAL 27.97 33.67 39.37 45.21 51.20 57.19 64.94
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ML67Q4050/Q4060 Series Power Considerations
Peripheral Block Core Current Versus SYSCLK Frequency
Figure shows peripheral (I/O) block core current contribution versus SYSCLK frequency. example, when clock enabled, setting appropriate PRSTCTL register, extra core current consumed order MHz. other words, enabling peripheral clock, core current increases plot data taken room temperature nominal supplies with typical silicon. Figure 2-3. Core Current Versus SYSCLK Frequency with Clock Enabled
Clock Current
UART0 TIM/FWDT
SYSCLK (MHz)
IDDcore (mA)
Figure shows peripheral block core current contribution versus SYSCLK frequency, when actual peripheral running. plot data taken room temperature nominal supplies with typical silicon. Figure 2-4. Core Current Versus SYSCLK Frequency while Transferring Data
Block Current
UART0 TIM/FSIO
SYSCLK (MHz)
IDDcore (mA)
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ML67Q4050/Q4060 Series Power Considerations
STOP Mode
STOP mode offers lowest power consumption ML67Q4050/Q4060 Series. STOP mode activated setting "STOP" clock stop register (CLKSTP 0xB800.0004). Typical core current consumption this mode order Wake from STOP mode accomplished using External Interrupt (specific GPIO's), Reset. STOP mode RTC, RINGOSC SYSCLK oscillators active. ensure lowest power consumption, disable these oscillators before entering STOP mode. This achieved clearing appropriate bits CLKSPTCNT register (0xB700.0014). Clearing bits CLKSTPCNT does disable oscillators until part into STOP mode (writing STOP CLKSTP register 0xB800.0004). When SYSCLK oscillator off, STOP current does change over frequency. leaving SYSCLK oscillator enabled during STOP mode, wake time reduced expense larger current draw. Consideration should given actual wake time block used bypassed. Application Engineering assist this area. Send eMail request advantage-support@oki.com. Figure shows cumulative contribution STOP core current when each oscillators enabled. Note difference between SYSCLK oscillator contribution case MHz. Typically oscillator contributes very little core current STOP mode uA). Figure 3-1.
core
STOP Mode Current versus SYSCLK
1150 SysClk SysClk RingOsc RingOsc
actual guaranteed STOP mode current consumption numbers given Table 3-1. table shows both typical (TYP) worst case (MAX) numbers process temperature. Table 3-1. STOP Mode ML67Q4050/Q4060 Series Typical Maximum IDDO Current Current Limits (uA) IDDO Conditions VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, 33.333 MHz, process 25°C VDD_IO 3.6V, VDD_CORE VDD_PLL 2.75V, 33.333 MHz, process -40°C CORE 10.131 485.00 0.062 10.00 0.027 5.00 TOTAL 10.220 500.00
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ML67Q4050/Q4060 Series Power Considerations
HALT Mode
HALT mode following blocks disabled:
ARM7TDMI IMEMC Internal memory controller INTRC interrupt controller DEFSLV default slave ARBITER, AHBIF, APBIF
Group contributes sizable portion current draw core. placing part HALT mode significant saving power achieved. following chart indicates peripheral contribution total power budget. largest section that consumed Group that saved when part HALT mode. Figure 4-1. Peripheral Current Contributions HALT Mode
1%1%
UART FTIM GPIO
HALT mode activated setting HALT clock stop register (CLKSTP 0xB800.0004). Wake from HALT mode accomplished using Interrupt. serial port used wake from HALT. this case baud rate maximum (230400) without adversely affecting current consumption. achieve faster wake from HALT using SIO, faster baud rate. However, achieve higher baud rates SYSCLK oscillator must faster thus more core current consumed HALT mode. following tables show core current consumption versus SYSCLK. Also shown case when during measurement.
November, 2005
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ML67Q4050/Q4060 Series Power Considerations
Table 4-1.
HALT Mode ML67Q4050/Q4060 Series Typical IDDO Current Versus Frequency (VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, process 25°C) Core Current BUAD 4800 9600 19200 38400 38400 57600 57600 115200 9600 38400 115200 APBDIV 0.148 0.291 0.579 1.160 2.305 3.434 4.584 4.586 4.732 4.733 4.733 0.138 0.272 0.539 1.083 2.154 3.210 4.283 4.283 4.422 4.422 4.422 Core Current APBDIV 0.183 0.364 0.728 1.465 2.910 4.335 5.778 5.778 5.973 5.973 5.973
Frequency (MHz)
Note that there little difference core current baud rate setting SIO. example, SYSCLK setting MHz, core current remains constant around 4.73 over baud rates 9600 115200. system requires wake event triggered over serial port, then setting baud rate higher value provides faster wake with little impact current draw. Also, SYSCLK increased core current increases proportionately, effect Baud rate much smaller. final table numbers below shows influence Divider core current HALT (and modes). Consider following: SYSCLK MHz, Baud 115200, APBDIV Core 5.97mA. SYSCLK MHz, Baud 115200, APBDIV Core 4.73mA. possible divider should when HALT mode. above example there saving greater than
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ML67Q4050/Q4060 Series Power Considerations
Current Consumption
ML67Q4050/Q4060 Series have built PLL's (PLLA PLLB) accurate clock generation. some cases PLLA used alone, other situations both PLLA PLLB used. PLLA supplies input clock PLLB. diagram below shows basic structure subsystem with different register they relate PLL. Figure 5-1.
PLLDIVA SYSCLK
Subsystem Diagram
PLLA DREFA SVCOA
DVCOA PLLB PLLDIVB DREFB SVCOB
DVCOB
PLLDIVC SYSCLK 1/PLLDIVA DVCOA/DREFA 1/PLLDIVB DVCOB/DREFB 1/PLLDIVC
Depending application, used all. example direct clock into SYSCLK pins, bypassed. When block used, section often used generate accurate Audio clock frequencies 8.192 MHz, 12.244 Careful consideration should given clock selection settings PLL. example, SYSCLK 33.33 Audio clock 8.192 MHz, both PLLA PLLB used generate necessary frequencies. estimate current this setup region using SYSCLK 32.768 Audio clock 8.192 MHz, only PLLA used, current consumption reduced Looking this example more detail, should noted that reduction MIPs performance core current reduced Table gives indication current consumption various clock settings. These numbers guidance show relative differences obtained with different settings should taken guaranteed numbers. full tables settings available from Application Engineering request. Note also, device driven external clock bypassing which will result different overall part current consumption.
November, 2005
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ML67Q4050/Q4060 Series Power Considerations
Table 5-1. SYSCLK (MHz) 8.192 16.384 32.768 19.2 33.333
Typical Current Versus Clock Settings Register Settings (Hex) CLKCNT 000B.2002 000B.2002 000B.2002 000B.2002 000B.2002 000B.2002 000B.2002 000B.2002 000B.2002 0009.1001 0009.1001 0009.1001 000B.2002 000B.2002 PLLA 2508.3108 210E.2215 310D.220F 2717.2211 2508.3310 380B.330B 2013.2311 270D.3205 250C.3308 0000.310A 0000.3105 0000.3205 3508.3104 2E11.2411 PLLB 0019.0101 0011.1301 000E.1101 0019.0301 0019.0101 0010.0101 0017.0101 0011.0101 0019.0101 0000.0A01 0000.0A01 0000.0A01 000F.0101 0015.0101 Output PLLB PLLB PLLB PLLB PLLB PLLB PLLB PLLB PLLB PLLA PLLA PLLA PLLB PLLB
(mA) 7.45 6.72 5.85 7.83 7.42 5.73 7.65 5.45 6.60 2.18 2.21 2.31 5.30 7.17
Test Conditions: VDD_IO 3.3V, VDD_CORE VDD_PLL 2.5V, process 25°C AUDIO_CLK 8.192 OFF, RING
Conclusion
ML67Q4050/Q4060 Series offers many methods reduce applications power consumption. Mechanisms such HALT STOP modes utilized well clock dividers adjust core peripheral clocks. same time these devices offer flexibility change operating frequency device on-the-fly, when more less processing power required. Many on-chip peripherals also have internal clock dividers which used blocks appropriate (lower power) speeds. allows users select operating frequency desired, noted, careful consideration this frequency help reduce current draw without affecting performance.
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November, 2005
ML67Q4050/Q4060 Series Power Considerations
Revision History
Revision Date 11/08/2005 Changes Since Last Revision This Initial Release this document.
November, 2005
Semiconductor
ML67Q4050/Q4060 Series Power Considerations
Notice
information contained herein change without notice owing product and/ technical improvements. Please make sure before using product that information referring up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When actually plan product, please ensure that outside conditions reflected actual circuit assembly designs. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters outside specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right,etc.is granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. When designing your product, please product below specified maximum ratings within specified operating ranges, including limited operating voltage, power dissipation, operating temperature. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products not, unless specifically authorized Oki, authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic control, automotive, safety, aerospace, nuclear power control, medical, including life support maintenance. Certain parts this document need governmental approval before they exported certain countries. purchaser assumes responsibility determining legality export these parts will take appropriate necessary steps, their expense, export another country. Semiconductor reserves right make changes specifications anytime without notice. This information furnished Semiconductor this publication believed accurate reliable. However, responsibility assumed Semiconductor use; infringements patents other rights third parties resulting from use. license granted under patents patent rights Oki. Trademarks: Advantage µPlat trademarks Semiconductor. ARM, ARM7TDMI, Powered Logo registered trademarks, AMBA, ARM7, Multi-ICE trademarks Advanced RISC Machines, Ltd. Copyright 2004 2005 Semiconductor
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