This application note explains need clock skew management apply OKI's

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This application note explains need clock skew management apply OKI's

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0.8µ Clock Skew Management
This application note explains need clock skew management apply OKI's clock skew management scheme. offers solution clock skew problems today's high frequency timing sensitive circuits. developed clock tree structure which guarantees skew times less than This clock skew management scheme available high-speed 0.8µm ASIC products. technology advances, operational frequency increase. clock signal becomes most timing sensitive critical signals circuit. quite common have system clock driving over 1000 flip-flops design. With traditional clock tree structure, clock skew difficult avoid. traditional tri-level clock tree structure shown Figure Imbalance routing loading each level clock tree easily contribute skew time. Although careful balancing fan-out manual placement each latch minimize skew, time consuming impractical.
SYSCLK
Figure Traditional Tri-Level Clock Tree
FEATURES
Clock skew Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Single level clock drivers Automatic branch length minimization Dynamic driver placement four clock trunks allowed
basic structure OKI's clock tree scheme shown Figure Depending loading array size, optimized number clock drivers paralleled drive main clock trunk. When connecting clock drivers paralleled configuration, loads shared among drivers, which minimizes clock skew. Sub-trunks connected main trunk, with branches connecting each clocked cell sub-trunk.
SEMICONDUCTOR
0.8µ Clock Skew Management
Clocked Cell Main Trunk Branch
Sub-Trunk
Clock Drivers
Input Buffer
Clock Tree Driver Macrocell
Figure OKI's Clock Tree Structure Latches other clocked cells within same functional logic module usually directly indirectly connected each other. auto-placement, these cells placed near each other maximize routeability. This concentration clocked cells imbalance loading clock sub-trunks.
Concentrate Area
Figure Dynamic Sub-Trunk Allocation Figure Figure show OKI's clock scheme accommodates this problem. balance skew, OKI's placement software dynamically allocates more sub-trunks clustered areas, shown inFigure addition, clock drivers also dynamically placed balance loads clustered areas, shown Figure
SEMICONDUCTOR
0.8µ Clock Skew Management
Concentrate Area
Figure Dynamic Sub-Trunk Allocation
placement process, multiple clocked cells assigned sub-trunk. Each sub-trunk assigned approximately same amount loads. OKI's placement software further improves placement each clocked cell moving each cell close possible assigned sub-trunk. Therefore, each sub-trunk well balanced with minimum branch routing. Figure Figure describe this feature.
Main Trunk
Sub-Trunk
Fan-out
Figure Automatic Sub-Trunk Load Balancing
Main Trunk Sub-Trunk
Minimizing Branch Length
Figure Automatic Branch Length Minimization
SEMICONDUCTOR
0.8µ Clock Skew Management
APPLICATION GUIDELINES
general, clock skew management scheme should applied designs whenever possibility uncontrollable clock skew exists. Some conditions that could warrant clock tree are: Less than hold-time margin timing simulations Clocks with over fan-outs Clock operation frequency above with uncontrolled placement Please note that problems clock skew design specific exist even when none above conditions apply. further guidelines contact OKI's ASIC Applications Department. Clock tree drivers physically paralleled drivers, represented single logic symbol. logic designer simply uses clock tree driver macrocell during schematic capture does have build traditional clock tree. OKI's clock tree software will automatically build clock tree. examples physical clock tree driver macrocells their logic symbols shown Figure
WDR240 Logic Symbol WDR240C Logic Symbol WDR240 Physical Structure WDR240C Physical Structure
Figure Physical Clock Tree Driver Macrocell Logic Symbol
SEMICONDUCTOR
0.8µ Clock Skew Management
list available clock tree drivers shown following table. List Available Clock Tree Driver Macrocells
Clock Tree Driver Macro WDR220(C) WDR240 WDR260 WDR280 WDR2100 WDR2120 WDR2140 WDR2160 WDR2180 WDR2200 WDR2220 WDR2240 WDR2260 WDR2280 WDR2300 WDR2320 WDR2340 WDR2360 WDR2380 WDR2400 Function Drive Clock Tree Driver (with complement output) Drive Clock Tree Driver (with complement output) Drive Clock Tree Driver (with complement output) Drive Clock Tree Driver (with complement output) 100X Drive Clock Tree Driver (with complement output) 120X Drive Clock Tree Driver (with complement output) 140X Drive Clock Tree Driver (with complement output) 160X Drive Clock Tree Driver (with complement output) 180X Drive Clock Tree Driver (with complement output) 200X Drive Clock Tree Driver (with complement output) 220X Drive Clock Tree Driver (with complement output) 240X Drive Clock Tree Driver (with complement output) 260X Drive Clock Tree Driver (with complement output) 280X Drive Clock Tree Driver (with complement output) 300X Drive Clock Tree Driver (with complement output) 320X Drive Clock Tree Driver (with complement output) 340X Drive Clock Tree Driver (with complement output) 360X Drive Clock Tree Driver (with complement output) 380X Drive Clock Tree Driver (with complement output) 400X Drive Clock Tree Driver (with complement output)
dynamic placement clock drivers, recommends input buffer internal driver drive clock tree driver macro. This will minimize wire length capacitance loading effect input terminal clock tree driver macrocell. maximum fan-out capability each clock tree driver varies, depending size chosen array. larger array, clock tree structure more extensive; therefore, larger clock tree driver should used. smaller clock tree drivers restricted smaller arrays unless floor planning utilized restrict clock tree area. this case, floorplanning must limit clock tree area number rows specified following tables. Caution should used select large clock tree driver, this adversely affect routability design. Besides array size fan-out clock signal, designer should also consider clock frequency. higher clock frequency, narrower clock pulse; hence, larger clock tree driver macrocell needed fast Maximum fan-out capabilities each array different frequency ranges listed following tables.
SEMICONDUCTOR
0.8µ Clock Skew Management
MSM10S Maximum Fan-Out
Fan-Out WDR. MSM10S 2100 2120 2140 2160 2180 2200 Frequency 50MHz 0050 0110 0210 0300 0570 0980 1250 1220 1200 1180 1130 1080
1880 1850 1800 1780 1710 1640
2510 2470 2410 2380 2290 2200
3140 3090 3020 2980 2880 2760
3770 3710 3630 3580 3460 3320
4400 4330 4240 4180 4040 3880
5030 4950 4850 4780 4620 4440
5660 5570 5460 5380 5200 5000
6290 6190 6070 5980 5790 5560
Frequency 0050 0110 0210 0300 0570 0980 1490 1450 1410 1390 1320 1250 1990 1950 1890 1860 1770 1680 2490 2440 2370 2330 2220 2110 2990 2930 2850 2800 2680 2540 3490 3420 3330 3270 3130 2970 3990 3910 3810 3740 3580 3400 4490 4400 4290 4210 4030 3830 4990 4890 4760 4680 4480 4260
Frequency 0050 0110 0210 0300 0570 0980 1290 1260 1220 1190 1130 1050 1730 1680 1630 1600 1510 1420 2160 2110 2050 2000 1900 1780 2600 2540 2460 2410 2290 2150 3030 2960 2870 2810 2670 2510 3470 3390 3290 3220 3060 2880 3900 3810 3700 3620 3450 3240 4340 4240 4110 4030 3830 3610
Note: Clock tree area must restricted rows; rows.
SEMICONDUCTOR
0.8µ Clock Skew Management
MSM10S Maximum Fan-Out (Continued)
Fan-Out WDR. MSM10S 2220 2240 2260 2280 2300 2320 2340 2360 2380 2400 Frequency 50MHz 0050 0110 0210 0300 0570 0980 6920 6810 6680 6580 6370 6120 7550 7430 7290 7180 6950 6680 8180 8050 7890 7780 7530 7240 8820 8680 8500 8390 8110 7800 9450 9300 9110 8990 8700 8360 10080 9920 9720 9590 9280 8920 10710 10540 10330 10190 9860 9480 11340 11160 10940 10790 10440 10040 11970 11780 11550 11390 11020 10600 12600 12400 12160 11990 11610 11160
Frequency 0050 0110 0210 0300 0570 0980 5490 5380 5240 5150 4930 4690 5990 5870 5720 5620 5390 5120 6490 6360 6200 6090 5840 5550 6990 6850 6680 6560 6290 5980 7490 7340 7160 7030 6740 6410 7990 7830 7640 7500 7190 6840 8490 8320 8120 7970 7650 7270 8990 8810 8590 8440 8100 7700 9490 9300 9070 8910 8550 8130 9990 9800 9550 9380 9000 8560
Frequency 0050 0110 0210 0300 0570 0980 1500 2250 4770 4660 4530 4430 4220 3970 3730 3430 5210 5090 4940 4840 4610 4340 4070 3750 5640 5510 5350 5240 4990 4700 4410 4070 6080 5940 5770 5650 5380 5070 4760 4390 6510 6370 6180 6060 5760 5430 5100 4700 6950 6790 6590 6460 6150 5800 5450 5020 7390 7220 7010 6870 6540 6160 5790 5340 7820 7640 7420 7270 6920 6530 6130 5660 8260 8070 7840 7680 7310 6890 6480 5980 8690 8490 8250 8080 7700 7260 6820 6290
SEMICONDUCTOR
0.8µ Clock Skew Management
MSM38S Maximum Fan-Out
Fan-Out WDR. MSM38S 2100 2120 2140 2160 2180 2200 Frequency 0110 0210 0300 0570 0980 1500 2250
1490 1470 1460 1420 1380 1350
1990 1970 1950 1910 1860 1810 1750
2490 2460 2440 2390 2330 2270 2200
3000 2960 2930 2870 2800 2730 2650
3500 3450 3420 3350 3270 3190 3100
4000 3950 3920 3840 3750 3660 3550
4500 4450 4410 4320 4220 4120 4000
5000 4940 4900 4800 4690 4580 4450
1300
Frequency 0110 0210 0300 0570 0980 1500 2250
1210 1190 1180 1150 1110 1070 1020
1620 1600 1580 1540 1490 1440 1380
2030 2000 1980 1930 1870 1810 1740
2440 2400 2380 2320 2250 2180 2100
2850 2810 2780 2710 2630 2550 2450
3260 3210 3180 3100 3010 2920 2810
3670 3620 3580 3490 3390 3290 3170
4080 4020 3980 3880 3770 3660 3530
Frequency 0110 0210 0300 0570 0980 1500 2250
1330 1300 1280 1240 1190 1140 1090
1660 1630 1610 1560 1500 1440 1370
2000 1960 1940 1870 1810 1740 1650
2340 2290 2260 2190 2110 2030 1940
2670 2620 2590 2510 2420 2330 2220
3010 2950 2910 2830 2730 2620 2510
3340 3280 3240 3140 3030 2920 2790
Note: Clock tree area must restricted rows; rows; rows.
SEMICONDUCTOR
0.8µ Clock Skew Management
MSM38S Maximum Fan-Out (Continued)
Fan-Out WDR. MSM38S 2220 2240 2260 2280 2300 2320 2340 2360 2380 2400 Frequency 0110 0210 0300 0570 0980 1500 2250 5500 5440 5390 5290 5160 5040 4900 6010 5930 5880 5770 5640 5500 5350 6510 6430 6380 6250 6110 5960 5800 7010 6930 6870 6730 6580 6430 6250 7510 7420 7360 7220 7050 6890 6700 8010 7920 7850 7700 7530 7350 7150 8520 8410 8340 8180 8000 7810 7600 9020 8910 8840 8670 8470 8270 8050 9520 9410 9330 9150 8940 8740 8500 10020 9900 9820 9630 9420 9200 8950
Frequency 0110 0210 0300 0570 0980 1500 2250 4490 4420 4380 4270 4150 4030 3880 4900 4830 4780 4660 4530 4400 4240 5310 5230 5180 5050 4910 4770 4600 5720 5630 5580 5440 5290 5140 4960 6130 6040 5980 5830 5670 5510 5310 6540 6440 6380 6220 6050 5870 5670 6950 6850 6780 6610 6430 6240 6030 7360 7250 7180 7010 6810 6610 6390 7770 7650 7580 7400 7190 6980 6740 8180 8060 7980 7790 7570 7350 7100
Frequency 0110 0210 0300 0570 0980 1500 2250 3680 3610 3570 3460 3340 3220 3070 4010 3940 3890 3780 3650 3510 3360 4350 4270 4220 4090 3950 3810 3640 4690 4600 4540 4410 4260 4100 3920 5020 4930 4870 4730 4570 4400 4210 5360 5260 5200 5040 4870 4690 4490 5690 5590 5520 5360 5180 4990 4780 6030 5920 5850 5680 5480 5290 5060 6370 6250 6170 5990 5790 5580 5340 6700 6580 6500 6310 6100 5880 5630
SEMICONDUCTOR
0.8µ Clock Skew Management
MSM98S Maximum Fan-Out (Frequency MHz)
Fan-Out WDR. MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104
1000
1500 1500 1490 1480 1470 1470 1460 1450 1450 1440 1430 1420 1420 1410 1400 1400 1390 1380 1370 1370 1360 1350 1350 1340 1330 1320 1320
2010 2000 1990 1980 1970 1960 1950 1950 1940 1930 1920 1910 1900 1890 1880 1870 1860 1850 1840 1840 1830 1820 1810 1800 1790 1780 1770 1760 1750
2100 2510 2500 2490 2480 2470 2460 2450 2440 2420 2410 2400 2390 2380 2370 2360 2350 2340 2320 2310 2300 2290 2280 2270 2260 2250 2240 2230 2210 2200
2120 3020 3010 2990 2980 2970 2950 2940 2930 2910 2900 2890 2880 2860 2850 2840 2820 2810 2800 2780 2770 2760 2750 2730 2720 2710 2690 2680 2670 2650
2140 3520 3510 3490 3480 3460 3450 3430 3420 3400 3390 3370 3360 3350 3330 3310 3300 3280 3270 3250 3240 3220 3210 3190 3180 3160 3150 3140 3120 3100
2160 4030 4010 4000 3980 3960 3950 3930 3910 3890 3880 3860 3840 3830 3810 3790 3770 3760 3740 3720 3710 3690 3670 3660 3640 3620 3610 3590 3570 3550
2180 4540 4510 4500 4480 4460 4440 4420 4400 4380 4360 4340 4330 4310 4290 4270 4250 4230 4210 4190 4180 4160 4140 4120 4100 4080 4060 4040 4020 4010
2200 5040 5020 5000 4980 4960 4940 4910 4890 4870 4850 4830 4810 4790 4770 4750 4730 4710 4680 4660 4640 4620 4600 4580 4560 4540 4520 4500 4480 4460
1310 1300
Note: Clock tree area must restricted rows; rows; rows.
SEMICONDUCTOR
0.8µm Clock Skew Management
MSM98S Maximum Fan-Out (Frequency MHz) (Continued)
Fan-Out WDR. MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104 2220 5550 5520 5500 5480 5450 5430 5410 5390 5360 5340 5310 5290 5270 5250 5230 5200 5180 5150 5130 5110 5090 5070 5040 5020 4990 4970 4950 4930 4910 2240 6050 6020 6000 5970 5950 5930 5900 5880 5850 5830 5800 5780 5750 5730 5700 5680 5650 5630 5600 5580 5550 5530 5500 5480 5450 5430 5410 5380 5360 2260 6560 6530 6500 6470 6450 6420 6390 6370 6340 6310 6290 6260 6240 6210 6180 6150 6130 6100 6070 6050 6020 5990 5960 5940 5910 5890 5860 5830 5810 2280 7060 7030 7000 6970 6950 6920 6890 6860 6830 6800 6770 6740 6720 6690 6660 6630 6600 6570 6540 6520 6480 6460 6430 6400 6370 6340 6310 6280 6260 2300 7570 7530 7500 7470 7440 7410 7380 7350 7320 7290 7260 7230 7200 7170 7140 7100 7070 7040 7010 6980 6950 6920 6890 6860 6830 6800 6770 6740 6710 2320 8070 8040 8010 7970 7940 7910 7870 7840 7810 7780 7740 7710 7680 7650 7610 7580 7550 7510 7480 7450 7420 7390 7350 7320 7280 7250 7220 7190 7160 2340 8580 8540 8510 8470 8440 8410 8370 8340 8300 8270 8230 8190 8160 8120 8090 8050 8020 7980 7950 7920 7880 7850 7810 7780 7740 7710 7680 7640 7610 2360 9080 9040 9010 8970 8930 8900 8860 8830 8790 8750 8710 8680 8640 8600 8570 8530 8500 8460 8420 8390 8350 8310 8270 8240 8200 8170 8130 8090 8060 2380 9590 9550 9510 9470 9430 9400 9350 9320 9280 9240 9200 9160 9130 9080 9050 9010 8970 8930 8890 8860 8810 8780 8740 8700 8660 8620 8590 8540 8510 2400 10090 10050 10010 9970 9930 9890 9850 9810 9770 9730 9680 9650 9610 9560 9530 9480 9440 9400 9360 9320 9280 9240 9200 9160 9120 9080 9040 9000 8960
SEMICONDUCTOR
0.8µm Clock Skew Management
MSM98S Maximum Fan-Out Frequency MHz)
Fan-Out WDR. MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104
1230 1220 1210 1200 1200 1190 1180 1180 1170 1160 1150 1150 1140 1130 1130 1120 1110 1100 1100 1090 1080 1080 1070 1060 1050 1050 1040
1640 1630 1620 1610 1600 1590 1580 1580 1570 1560 1550 1540 1530 1520 1510 1500 1490 1480 1480 1470 1460 1450 1440 1430 1420 1410 1400 1390 1390
2100 2050 2040 2030 2020 2010 2000 1990 1980 1960 1950 1940 1930 1920 1910 1900 1890 1880 1860 1850 1840 1830 1820 1810 1800 1790 1780 1770 1750 1740
2120 2470 2450 2440 2430 2410 2400 2390 2370 2360 2350 2330 2320 2310 2300 2280 2270 2260 2240 2230 2220 2200 2190 2180 2170 2150 2140 2130 2110 2100
2140 2880 2860 2850 2830 2820 2800 2790 2770 2760 2740 2730 2710 2700 2680 2670 2650 2640 2620 2610 2590 2580 2560 2550 2530 2520 2500 2490 2470 2460
2160 3290 3270 3260 3240 3220 3210 3190 3170 3150 3140 3120 3100 3090 3070 3050 3040 3020 3000 2990 2970 2950 2940 2920 2900 2880 2870 2850 2830 2820
2180 3710 3680 3670 3650 3630 3610 3590 3570 3550 3530 3510 3500 3480 3460 3440 3420 3400 3380 3360 3350 3330 3310 3290 3270 3250 3230 3210 3190 3170
2200 4120 4100 4080 4050 4030 4010 3990 3970 3950 3930 3910 3890 3870 3850 3830 3800 3780 3760 3740 3720 3700 3680 3660 3640 3610 3590 3580 3550 3530
1030 1030
Note: Clock tree area must restricted rows; rows; rows.
SEMICONDUCTOR
0.8µm Clock Skew Management
MSM98S Maximum Fan-Out Frequency MHz) (Continued)
Fan-Out WDR. MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104 2220 4530 4510 4480 4460 4440 4420 4390 4370 4350 4320 4300 4280 4260 4230 4210 4190 4160 4140 4120 4100 4070 4050 4030 4000 3980 3960 3940 3910 3890 2240 4940 4920 4890 4870 4840 4820 4790 4770 4740 4720 4690 4670 4650 4620 4600 4570 4550 4520 4500 4470 4450 4420 4400 4370 4350 4320 4300 4270 4250 2260 5360 5330 5300 5270 5250 5220 5190 5170 5140 5120 5090 5060 5040 5010 4980 4950 4930 4900 4870 4850 4820 4790 4770 4740 4710 4690 4660 4630 4610 2280 5770 5740 5710 5680 5650 5630 5600 5570 5540 5510 5480 5450 5430 5390 5370 5340 5310 5280 5250 5220 5190 5170 5140 5110 5080 5050 5020 4990 4960 2300 6180 6150 6120 6090 6060 6030 6000 5970 5930 5910 5870 5840 5820 5780 5750 5720 5690 5660 5630 5600 5570 5540 5500 5480 5440 5410 5380 5350 5320 2320 6600 6560 6530 6490 6460 6430 6400 6370 6330 6300 6270 6240 6200 6170 6140 6100 6070 6040 6010 5980 5940 5910 5870 5840 5810 5780 5750 5710 5680 2340 7010 6970 6940 6900 6870 6840 6800 6770 6730 6700 6660 6630 6590 6560 6520 6490 6450 6420 6380 6350 6310 6280 6240 6210 6170 6140 6110 6070 6040 2360 7420 7380 7350 7310 7270 7240 7200 7170 7130 7090 7050 7020 6980 6940 6910 6870 6840 6800 6760 6730 6690 6650 6610 6580 6540 6510 6470 6430 6400 2380 7840 7790 7760 7720 7680 7640 7600 7570 7520 7490 7450 7410 7370 7330 7300 7250 7220 7180 7140 7100 7060 7030 6980 6950 6910 6870 6830 6790 6750 2400 8250 8200 8170 8120 8080 8050 8000 7960 7920 7880 7840 7800 7760 7720 7680 7640 7600 7550 7520 7480 7430 7400 7350 7310 7270 7230 7190 7150 7110
SEMICONDUCTOR
0.8µm Clock Skew Management
MSM98S Maximum Fan-Out Frequency MHz)
Fan-Out WDR. MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104
1010 1000
1340 1330 1330 1320 1310 1300 1290 1280 1270 1260 1250 1240 1240 1230 1220 1210 1200 1190 1180 1170 1160 1150 1140 1140 1130 1120 1110 1100 1090
2100 1680 1670 1660 1650 1640 1630 1620 1610 1590 1580 1570 1560 1550 1540 1530 1520 1510 1490 1480 1470 1460 1450 1440 1430 1420 1410 1400 1380 1370
2120 2020 2010 2000 1980 1970 1960 1940 1930 1920 1910 1890 1880 1870 1850 1840 1830 1810 1800 1790 1780 1760 1750 1740 1720 1710 1700 1680 1670 1660
2140 2360 2350 2330 2320 2300 2290 2270 2260 2240 2230 2210 2200 2180 2170 2150 2140 2120 2110 2090 2080 2060 2050 2030 2020 2000 1990 1970 1960 1940
2160 2700 2680 2670 2650 2630 2620 2600 2580 2560 2550 2530 2510 2500 2480 2460 2450 2430 2410 2400 2380 2360 2350 2330 2310 2290 2280 2260 2240 2230
2180 3040 3020 3000 2980 2960 2950 2930 2910 2890 2870 2850 2830 2810 2790 2780 2760 2740 2720 2700 2680 2660 2640 2620 2610 2580 2570 2550 2530 2510
2200 3380 3360 3340 3320 3300 3280 3250 3230 3210 3190 3170 3150 3130 3110 3090 3060 3050 3020 3000 2980 2960 2940 2920 2900 2880 2860 2840 2810 2790
Note: Clock tree area must restricted rows; rows; rows.
SEMICONDUCTOR
0.8µm Clock Skew Management
MSM98S Maximum Fan-Out Frequency (Continued)
Fan-Out WDR. MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104 2220 3720 3690 3670 3650 3630 3610 3580 3560 3530 3510 3490 3470 3450 3420 3400 3370 3350 3330 3310 3290 3260 3240 3210 3190 3170 3150 3130 3100 3080 2240 4060 4030 4010 3980 3960 3940 3910 3880 3860 3830 3810 3780 3760 3730 3710 3680 3660 3630 3610 3590 3560 3540 3510 3490 3460 3440 3410 3390 3360 2260 4400 4370 4340 4310 4290 4260 4240 4210 4180 4160 4130 4100 4080 4050 4020 3990 3970 3940 3910 3890 3860 3840 3810 3780 3750 3730 3700 3670 3650 2280 4740 4710 4680 4650 4620 4590 4560 4540 4500 4480 4450 4420 4390 4360 4330 4300 4280 4250 4220 4190 4160 4130 4100 4070 4040 4020 3990 3960 3930 2300 5080 5040 5010 4980 4950 4920 4890 4860 4830 4800 4770 4740 4710 4670 4650 4610 4580 4550 4520 4490 4460 4430 4400 4370 4340 4310 4280 4240 4220 2320 5420 5380 5350 5310 5280 5250 5220 5190 5150 5120 5090 5050 5020 4990 4960 4920 4890 4860 4830 4800 4760 4730 4690 4660 4630 4600 4570 4530 4500 2340 5750 5720 5680 5650 5610 5580 5540 5510 5470 5440 5400 5370 5340 5300 5270 5230 5200 5160 5130 5100 5060 5030 4990 4960 4920 4890 4850 4820 4780 2360 6090 6050 6020 5980 5950 5910 5870 5840 5800 5760 5720 5690 5660 5620 5580 5540 5510 5470 5430 5400 5360 5320 5290 5250 5210 5180 5140 5100 5070 2380 6430 6390 6360 6310 6280 6240 6200 6160 6120 6090 6040 6010 5970 5930 5890 5850 5810 5770 5740 5700 5660 5620 5580 5540 5500 5470 5430 5390 5350 2400 6770 6730 6690 6650 6610 6570 6530 6490 6440 6410 6360 6320 6290 6240 6200 6160 6120 6080 6040 6000 5960 5920 5880 5840 5790 5760 5720 5670 5640
SEMICONDUCTOR
0.8µm Clock Skew Management
EXAMPLES
examples selecting correct clock tree driver shown below. Clock Tree Driver Selection
Function Clock frequency Fan-out Array chosen Complement output Correct clock tree driver Example MSM10S0300 Needed WDR240C Example 2300 MSM38S1500 needed WDR2120
Delay Calculation Clock tree driver delays calculated same other logic gates, using delay equation: tpd0 Where tpd0 Propagation delay time (ns) Intrinsic base delay (ns) fan-in factors macrocells being driven Interconnect capacitance loading (pF) Propagation delay constant (ns) (0.10 low-to-high propagation delays) (0.15 high-to-low propagation delays) Fan-out propagation delay factor (ns/FO) Interconnect capacitance propagation delay factor (ns/pF) Process, temperature, voltage variation factor
clock tree nets, estimated interconnect capacitance (Cnet) must calculated using formula below. Clock tree parameters Cmtx, Csthx, shown following tables. Cnet Cmtx Csthx #st] [Cspan #span] Where Cnet Cmtx Csthx Cspan Estimated capacitance clock tree (pF) Main-trunk capacitance (pF) Half-sub-trunk capacitance (pF) Number sub-trunks Span capacitance factor (pF/span) (0.027 MSM10S) (0.028 MSM38S/98S) Number spans (flip-flops)
SEMICONDUCTOR
#span
0.8µm Clock Skew Management
Array Parameters
MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104 MSM38S 0110 0210 0300 0570 0980 1500 2250 Cmtx (pF) 0.79 0.91 1.01 1.06 1.18 1.32 1.43 1.45 1.59 1.70 1.72 1.86 1.99 2.13 2.26 2.33 2.40 2.52 2.67 2.79 2.94 3.05 3.06 3.20 3.33 3.47 3.60 3.74 3.77 3.87 4.01 4.14 4.28 4.40 4.55 4.62 Csthx (pF) 0.15 0.18 0.20 0.21 0.24 0.26 0.28 0.29 0.31 0.33 0.34 0.37 0.39 0.42 0.45 0.45 0.47 0.50 0.53 0.56 0.58 0.59 0.61 0.63 0.66 0.69 0.71 0.74 0.74 0.77 0.80 0.82 0.85 0.87 0.90 0.90 MSM10S 0050 0110 0210 0300 0570 0980 Cmtx (pF) 0.67 0.96 1.36 1.61 2.22 2.90 Csthx (pF) 0.20 0.29 0.41 0.49 0.67 0.87
SEMICONDUCTOR
0.8µm Clock Skew Management
Number Trunks
WDR2100(C) WDR2120(C) WDR2140(C) WDR2160(C) WDR2180(C) WDR2200(C) WDR2220(C) WDR2240(C) WDR2260(C) WDR2280(C) WDR2300(C) WDR2320(C) WDR2340(C) WDR2360(C) WDR2380(C) WDR2400(C) Driver Name Trunks WDR220(C) WDR240(C) WDR260(C) WDR280(C)
Since placement clock drivers dynamically determined, routing clock drivers subject wide variations. recommends high-drive input buffer/driver macrocells minimize interconnect capacitance effects. Estimated minimum/maximum capacitance values input driving clock tree driver shown tables below. These values used calculate propagation delays gate preceding clock tree driver macrocell.
SEMICONDUCTOR
0.8µm Clock Skew Management
Estimated Input Capacitance Clock Tree Driver Macrocells
MSM98S 020X020 023X023 026X026 029X029 032X032 035X035 038X038 041X041 044X044 047X047 050X050 053X053 056X056 059X059 062X062 065X065 068X068 071X071 074X074 077X077 080X080 083X083 086X086 089X089 092X092 095X095 098X098 101X101 104X104 MSM38S 0110 0210 0300 0570 0980 1500 2250 (pF) 0.103 0.107 0.110 0.111 0.116 0.120 0.123 0.124 0.128 0.132 0.133 0.137 0.141 0.146 0.150 0.151 0.154 0.158 0.162 0.167 0.171 0.174 0.176 0.180 0.183 0.188 0.192 0.197 0.197 0.201 0.206 0.209 0.213 0.218 0.222 0.224 (pF) 0.623 0.727 0.797 0.837 0.941 1.051 1.121 1.151 1.265 1.335 1.365 1.479 1.579 1.694 1.793 1.833 1.903 2.007 2.117 2.222 2.331 2.401 2.436 2.546 2.645 2.760 2.859 2.974 2.974 3.073 3.188 3.288 3.397 3.502 3.612 3.641 MSM10S 0050 0110 0210 0300 0570 0980 (pF) 0.155 0.174 0.197 0.212 0.247 0.287 (pF) 0.513 0.741 1.042 1.240 1.702 2.231
SEMICONDUCTOR
0.8µm Clock Skew Management
DELAY EXAMPLE
Given: gate, 3-layer metal, design flip-flops Flip-flop type FD1A (rising edge triggered) Worst case worst case process, 4.75V, 70°C (=1.65, from MSM38S/98S Design Manual)
Using: MSM38S0980 (~66k usable gates) WDR2120 (MSM38S0980, 50-60 MHz, FO=2250, #st=24) IC4AHH input buffer (symmetrical tpLH/tpHL)
ICLK IC4AHH
FFCLK
WDR2120
FD1A (2000
FD1A
Figure Delay Example
Delay Path Example
Cell IC4AHH (Max. WDR2120 (Fan 18.7) From LH/HL tpd0 (ns) 0.628 0.849 0.5127 0.6185 (ns/FO) 0.013 0.017 0.0003 0.0007
(ns/pF) 0.159 0.209 0.0036 0.0083
above data extracted from MSM38S/98S Macrocell Library.
SEMICONDUCTOR
0.8µm Clock Skew Management
Path Delay Calculations (LH) Clock-Tree capacitance Cmtx Csthx 0.028 fan-out 3.05 0.59(2 )(24) 0.028(2000) 87.4 tpLH-IC4AHH (ICLK with maximum capacitance) tpd0[LH] [LH] [LH] tpc[LH] 0.628 0.013(18.7) 0.159(2.401) 0.10 1.353
tpLH-WDR2120 (FFCLK net) tpd0[LH] [LH] [LH] tpc[LH] 0.5127 0.0003(2000) 0.0036(87.4) 0.10 1.427 tpLH-pin-to-FF (typical) tpLH-IC4AHH tpLH-WDR2120 =1.353 1.427 2.780 tpLH-pin-to-FF (worst case) tpLH-pin-to-FF (typical) 2.780(1.65) 4.587 Assistance questions further assistance clock skew management, please contact OKI's ASIC Application Department (408) 720-1900 (west coast) (617) 279-0293 (east coast).
SEMICONDUCTOR
information contained herein change without notice owing product and/or technical improvements. Please make sure before using product that information referring up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When actually plan product, please ensure that outside conditions reflected actual circuit assembly designs. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters outside specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right,etc.is granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. When designing your product, please product below specified maximum ratings within specified operating ranges, including limited operating voltage, power dissipation, operating temperature. products listed this document intended general electronics equipment commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property death injury humans. Such applications include, limited traffic control, automotive, safety, aerospace, nuclear power control, medical, including life support maintenance. Certain parts this document need governmental approval before they exported certain countries. purchaser assumes responsibility determining legality export these parts will take appropriate necessary steps, their expense, export another country. Copyright 1995 SEMICONDUCTOR Semiconductor reserves right make changes specifications anytime without notice. This information furnished Semiconductor this publication believed accurate reliable. However, responsibility assumed Semiconductor use; infringements patents other rights third parties resulting from use. license granted under patents patent rights OKI.
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This application note explains need clock skew management apply OKI's

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