User's Manual CMOS 4-bit microcontroller SECOND EDITION
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ML63187/189B
User's Manual
CMOS 4-bit microcontroller
SECOND EDITION
ISSUE DATE: Sep. 1999
E2Y0002-29-62
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1999 Electric Industry Co., Ltd.
Printed Japan
Preface
This manual describes hardware Oki's original CMOS 4-bit microcontrollers ML63187 ML63189B. Refer "nX-4/250 Core Instruction Manual" details 4-bit core nX-4/250 which built ML63187 ML63189B. manuals related ML63187 ML63189B shown below. nX-4/250 Core Instruction Manual: Describes base architecture instruction nX-4/250 core. SASM63K User's Manual: Describes structured assembler operation assembler language specification. EASE63180 User's Manual: Describes hardware emulator. DT63K Debugger/DTS63K Simulator User's Manual: Describes debugger commands hardware simulator.
This document subject change without notice.
Notation
Classification Numeric value Notation xxh, word, byte, nibble, mega-, kilo-, kilo-, milli-, micro-, nano-, second, (lower case) Description Represents hexadecimal number. Represents binary number. word bits byte nibbles bits nibble bits 1024 1000 10-3 10-6 10-9 second kilobyte 1024 bytes megabyte bytes 1,048,576 bytes
Unit
Symbol
M187 M189B
Note:
Gives more information about mistakable items. Indicates item related ML63187. Indicates item related ML63189B. Indicates high side voltage signal levels specified electrical characteristics. Indicates side voltage signal levels specified electrical characteristics.
Terminology
level level
Register description Invalid attribute When read, value always obtained. Write operations invalid. indicates data read indicates data written.
PB1MOD PB0MOD
PBMOD0
(032H) (R/W)
name Invalid Address attribute Register name
Table Contents
Chapter Overview Overview Features Function List Block Diagram. Configuration 1.5.1 ML63187 Configuration 1.5.2 ML63189B Configuration 1-11 Descriptions 1-15 1.6.1 Descriptions Basic Functions Each 1-15 1.6.2 Descriptions Secondary Functions Each 1-19 1.6.3 Unused Processing 1-20 Basic Timing 1-21 1.7.1 Basic Timing Operation 1-21 1.7.2 Port Basic Timing 1-21 1.7.3 Interrupt Basic Timing 1-23 Chapter Memory Spaces Overview Registers 2.2.1 Accumulator 2.2.2 Flag Register 2.2.2.1 Carry Flag 2.2.2.2 Zero Flag 2.2.2.3 Flag 2.2.3 Master Interrupt Enable Flag (MIE) 2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR), Register (HL), Register (XY) 2.2.5 Program Counter (PC) 2.2.6 Registers (RA3, RA2, RA1, RA0) 2.2.7 Stack Pointer (SP) Call Stack 2.2.8 Register Stack Pointer (RSP) Register Stack Memory Spaces 2.3.1 Program Memory Space 2.3.2 Data Memory Space
Chapter Control Functions Overview System Reset Mode (RST) 3.2.1 Transfer State System Reset Mode Halt Mode. 3.3.1 Transfer State Halt Mode 3.3.2 Halt Mode Release 3.3.2.1 Release Halt Mode Interrupt 3.3.2.2 Release Halt Mode RESET 3.3.3 Melody Data Interrupt Halt Mode Release 3.3.4 Note Concerning HALT Instruction Chapter ML63187 Interrupt (INT187) Overview Interrupt Registers Interrupt Sequence 4.3.1 Interrupt Processing 4.3.2 Return from Interrupt Routine 4.3.3 Interrupt Hold Instructions Chapter ML63189B Interrupt (INT189) Overview Interrupt Registers Interrupt Sequence 5.3.1 Interrupt Processing 5.3.2 Return from Interrupt Routine 5.3.3 Interrupt Hold Instructions Chapter Clock Generator Circuit (OSC) Overview Clock Generator Circuit Configuration Low-Speed Clock Generator Circuit High-Speed Clock Generator Circuit. System Clock Control Frequency Control Register (FCON) System Clock Select Timing 5-10 5-10 4-10 4-10
Chapter Time Base Counter (TBC) Overview Time Base Counter Configuration. Time Base Counter Registers Time Base Counter Operation
Chapter Timers (TIMER) Overview Timer Configuration Timer Registers. Timer Operation 8-14 8.4.1 Timer Clock 8-14 8.4.2 Timer Data Registers 8-14 8.4.3 Timer Counter Registers 8-14 8.4.4 Timer Interrupt Requests Overflow Flags 8-15 8.4.5 Auto-Reload Mode Operation 8-16 8.4.6 Capture Mode Operation 8-18 8.4.7 Frequency Measurement Mode Operation 8-21
Chapter Timer Counter (100HzTC) Overview Timer Counter Configuration Timer Counter Registers Timer Counter Operation
Chapter Watchdog Timer (WDT) 10.1 10.2 10.3 10.4 Overview 10-1 Watchdog Timer Configuration 10-1 Watchdog Timer Control Register (WDTCON) 10-2 Watchdog Timer Operation 10-2
Chapter Ports (INPUT, PORT) 11.1 Overview 11-1 11.2 Ports List 11-1 11.3 Port (P0.0-P0.3) 11-2 11.3.1 Port Configuration 11-2 11.3.2 Port Registers 11-2 11.3.3 Port External Interrupt Functions (External Interrupt 11-5 11.4 Port Port (P9.0-P9.3, PA.0-PA.3) 11-7 11.4.1 Port Port Configuration 11-7 11.4.2 Port Port Registers 11-8 11.5 Port (PB.0-PB.3) 11-12 11.5.1 Port Configuration 11-12 11.5.2 Port Registers 11-13 11.5.3 Port External Interrupt Function (External Interrupt 11-17 11.6 Port (PE.0-PE.3) 11-18 11.6.1 Port Configuration 11-18 11.6.2 Port Registers 11-19 11.6.3 Port External Interrupt Function (External Interrupt 11-22
Chapter Melody Driver (MELODY) Overview Melody Driver Configuration Melody Driver Registers. Melody Circuit Operation 12.4.1 Tempo Data 12.4.2 Melody Data 12.4.3 Melody Circuit Application Example 12.5 Buzzer Circuit Operation Chapter Shift Register (SFT) 13.1 13.2 13.3 13.4 13.5 Overview Shift Register Configuration Shift Registers. Shift Register Operation Shift Register Application Example 13-1 13-1 13-2 13-4 13-6 12.1 12.2 12.3 12.4 12-1 12-1 12-2 12-4 12-5 12-6 12-9 12-10
Chapter Driver (LCD) 14.1 14.2 14.3 14.4 14.5 14.6 Overview Driver Configuration Driver Registers Driver Operation Bias Generator (BIAS) Driver Output Waveform 14-1 14-1 14-2 14-5 14-6 14-9
Chapter Battery Detect Circuit (BLD) 15.1 15.2 15.3 15.4 15.5 Overview Battery Detect Circuit Configuration Judgment Voltage Battery Detect Circuit Register Battery Detect Circuit Operation. 15-1 15-1 15-2 15-2 15-3
Chapter Backup Circuit (BACKUP) 16.1 Overview 16-1 16.2 Power Supply Circuit Configuration 16-2 16.2.1 Power Supply Circuit Configuration When Backup Circuit Used 16-2 16.2.2 Power Supply Circuit Configuration When Backup Circuit Used 16-3 16.3 Backup Circuit Register 16-4 16.4 Power Supply Circuit Operation 16-5
Appendixes Appendix Appendix Appendix Appendix Appendix Appendix Appendix List Special Function Registers Appendix-1 Package Dimensions Appendix-12 Input/Output Circuit Configuration Appendix-13 Peripheral Circuit Examples Appendix-15 Electrical Characteristics Appendix-17 Instruction List Appendix-30 Mask Option Appendix-52
Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter
Overview Memory Spaces Control Functions ML63187 Interrupt (INT187) ML63189B Interrupt (INT189) Clock Generator Circuit (OSC) Time Base Counter (TBC) Timers (TIMER) Timer Counter (100HzTC)
Chapter Watchdog Timer (WDT) Chapter Ports (INPUT, PORT) Chapter Melody Driver (MELODY) Chapter Shift Register (SFT) Chapter Driver (LCD) Chapter Battery Detect Circuit (BLD) Chapter Backup Circuit (BACKUP) Appendixes
Chapter
Overview
M187
M189B
ML63187/189B User's Manual Chapter Overview
Chapter Overview
Overview ML63187 ML63189B CMOS 4-bit microcontrollers that guarantee operation With internal matrix driver, these devices well suited applications having liquid-crystal display (LCD) such games, toys, watches, etc. ML63187 ML63189B masked-ROM devices belonging M6318x series OLMS-63K family with internal Oki's original core nX-4/250. Compared other products M6318x series (MSM63184A), ML63187 ML63189B have slimmer functions, more memory capacity greater number drivers. Also, reference voltage value battery detect circuit been optimized, accommodate requirements power consumption, supply current decreased compared other devices same series.
Features ML63187 ML63189B have following features. Extensive instruction instructions Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations, operations, table reference, stack operations, flag operations, jump, conditional branch, call/return, control Wide variety addressing modes Indirect addressing mode types data memory with current bank register, extra bank register, register register Data memory bank internal direct addressing mode Processing speed clocks machine cycle, with most instructions executed machine cycle Minimum instruction execution time: 32.768 system clock) system clock) Clock generation circuit Low-speed clock: Crystal oscillation oscillation selected with mask option kHz) High-speed clock: Ceramic oscillation oscillation selected with software max.) Program memory space ML63187: words ML63189B: words basic instruction length bits word. Data memory space ML63187: 1024 nibbles ML63189B: 1536 nibbles
M187 M189B
ML63187/189B User's Manual Chapter Overview Stack level ML63187 ML63189B Call stack level Register stack level
Ports Input ports: Selectable input with pull-up resistor, input with pull-down resistor high impedance input. ports: Selectable input with pull-up resistor, input with pull-down resistor high impedance input. Selectable p-channel open drain output, n-channel open drain output, high impedance output CMOS output. interfaced external devices having different power supplies. Number ports: Input ports port bits ports ports bits ports bits
ML63187 ML63189B
Melody output Melody frequency: 2979 Tone length: varieties Tempo: varieties Melody data: Stored program memory Buzzer driver signal output: driver Number segments: 1024 segments max. seg. com.) 1/16 duty bias (internal regulator) Selectable all-ON mode, all-OFF mode, power down mode, normal display mode Adjustable contrast System reset function System reset RESET System reset power-on detection System reset detection that low-speed clock stopped oscillation Battery check Function that detects battery voltage Selection judgment voltage software (LD1 settings BLDCON)
Judgment voltage 1.05 ±0.10 1.20 ±0.10 1.80 ±0.10 2.40 ±0.10 Comments 25°C 25°C 25°C 25°C
M187 M189B
ML63187/189B User's Manual Chapter Overview Power supply backup Turning backup circuit (multiplied voltage circuit) enables operation voltage Timers, counters 8-bit timer:
Watchdog timer: timer: 15-bit TBC:
channels Selectable auto-reload mode, capture mode, clock frequency measurement mode channel channel 1/100 sec. measurement possible channel Hz,128 signals read
Shift register Shift clock: Data length: Interrupt factors ML63187 ML63189B Shipping products
System clock external clock bits
External factors
Internal factors
Package ML63187 Chip 128-pin flat package (128QFP) QFP128-P-1420-0.50-K ML63189B Chip 128-pin flat package (128QFP) QFP128-P-1420-0.50-K
Product ML63187-xxx ML63187-xxxGA
ML63189B-xxx ML63189B-xxxGA indicates code number.
Operating temperature +70°C Power supply voltage When using backup:
operating frequency) (500 max. operating frequency) max. operating frequency) When using backup: max. operating frequency)
M187 M189B
ML63187/189B User's Manual Chapter Overview Function List Table shows list ML63187 ML63189B functions. solid black circles within chart indicate that product particular function.
Table Function List
Function bits) bits) STACK Call Register System reset generation circuit Interrupt ML63187 interrupt ML63189B interrupt Clock generator circuit Time base counter Timers timer counter Watchdog timer Input port Port port Port Port Port Port Melody driver Shift register driver Display register bits) Bias generator Battery detect circuit Backup circuit Symbol STACK INT187 INT189 TIMER 100HzTC INPUT PORT PORT MELODY DSPR BIAS BACKUP ML63187 16352 1024 levels levels lines lines ML63189B 32736 1536 levels levels port bits lines lines Reference page
ports bits ports bits
M187 M189B
ML63187/189B User's Manual Chapter Overview Block Diagram Block diagrams ML63187 ML63189B shown Figures 1-2, respectively. Asterisks indicate secondary function each port. Signal names enclosed chain indicate interface signals VDDI power supply system. lines
nX-4/250 TIMING CONTROL INSTRUCTION DECODER CONTROL 16KW
STACK CAL.S levels REG.S levels
1024N TIMER bits TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK*
RESET
INT187 DATA SCLK* SIN* SOUT*
TST1 TST2
OSC0 OSC1
100HzTC
MELODY
VDDH VDD1 VDD2 VDD3 VDD4 VDD5 VDDL BIAS DSPR COM1-16 SEG0-63 VDDI BACKUP PORT PB.0-PB.3 PE.0-PE.3
Figure ML63187 Block Diagram M187 M189B M187
ML63187/189B User's Manual Chapter Overview Asterisks indicate secondary function each port. Signal names enclosed chain lines indicate interface signals VDDI power supply system.
nX-4/250 TIMING CONTROL INSTRUCTION DECODER CONTROL 32KW
STACK CAL.S levels REG.S levels
1536N
DATA
TIMER bits
TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK*
RESET
INT189
SCLK* SIN* SOUT*
TST1 TST2
MELODY INPUT PORT
OSC0 OSC1
100HzTC
P0.0-P0.3
VDDH VDD1 VDD2 VDD3 VDD4 VDD5 VDDL BIAS DSPR BACKUP PORT
P9.0-P9.3 PA.0-PA.3 PB.0-PB.3 PE.0-PE.3
COM1-16 SEG0-63 VDDI
Figure ML63189B Block Diagram
M189B M187 M189B
ML63187/189B User's Manual Chapter Overview Configuration 1.5.1 ML63187 Configuration ML63187 configuration, chip configuration, coordinates shown Figures 1-3, 1-4, Table 1-2, respectively. (not connected) indicates unused that left unconnected (open).
SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37
(NC) (NC) (NC) (NC) SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PB.3 PB.2 PB.1 PB.0 PE.3 PE.2 PE.1 PE.0 VDDI (NC) (NC) (NC) (NC) (NC)
TST2 TST1 RESET OSC0 OSC1 VDDL VDDH VDD5 VDD4 VDD3 VDD2 VDD1 COM16 COM15 COM14 COM13
Figure ML63187 128-Pin Configuration (Top View)
(NC) (NC) (NC) (NC) SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 (NC) (NC) (NC) (NC)
M187 M187 M189B
ML63187/189B User's Manual Chapter Overview
TST2 TST1 RESET OSC0 OSC1 VDDL VDDH VDD5 VDD4 VDD3 VDD2 VDD1 COM16 COM15 COM14 COM13
VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11
COM12 COM11 COM10 COM9 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38
SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37
ML63187
Chip size Chip thickness Coordinate origin hole size size Minimum pitch
4.238 4.914 (280 available required) center chip
M187
Note: chip substrate voltage VSS. Figure ML63187 Chip Configuration (Top View)
M189B
ML63187/189B User's Manual Chapter Overview Table ML63187 Coordinates
name SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 (mm) -1755 -1615 -1474 -1334 -1193 -1053 -913 -772 -632 -491 -351 -211 1053 1193 1334 1474 1615 1755 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 (mm) -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2311 -2036 -1895 -1755 -1615 -1474 -1334 -1193 -1053 -913 -772 -632 -491 -351 -211 name SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL OSC1 OSC0 RESET TST1 TST2 Center chip: (mm) (mm) 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1755 1615 1474 1334 1193 1053 -211 -351 -491 -632 -772 -913 -1053 -1193 -1334 -1474 1053 1193 1334 1474 1615 1755 1895 2036 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311
M187 M187 M189B
ML63187/189B User's Manual Chapter Overview Table ML63187 Coordinates (continued)
name VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 COM1 COM2 COM3 COM4 COM5 (mm) -1615 -1755 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 (mm) 2311 2311 1895 1755 1615 1474 1334 1193 1053 name COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 Center chip: (mm) (mm) -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -211 -351 -491 -632 -772 -913 -1053 -1193 -1334 -1474 -1615 -1755 -1895 -2036
1-10 M187 M189B
ML63187/189B User's Manual Chapter Overview 1.5.2 ML63189B Configuration ML63189B configuration, chip configuration, coordinates shown Figures 1-5, 1-6, Table 1-3, respectively. (not connected) indicates unused that left unconnected (open).
SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29
(NC) SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 P0.3 P0.2 P0.1 P0.0 P9.3 P9.2 P9.1 P9.0 PA.3 PA.2 PA.1 PA.0 PB.3 PB.2 PB.1 PB.0 PE.3 PE.2 PE.1 PE.0 VDDI (NC) (NC)
TST2 TST1 RESET OSC0 OSC1 VDDL VDDH VDD5 VDD4 VDD3 VDD2 VDD1 COM16 COM15 COM14 COM13 COM12 COM11
Figure ML63189B 128-Pin Configuration (Top View)
(NC) SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 (NC)
1-11 M187 M189B
ML63187/189B User's Manual Chapter Overview
TST2 TST1 RESET OSC0 OSC1 VDDL VDDH VDD5 VDD4 VDD3 VDD2 VDD1 COM16 COM15 COM14 COM13 COM12 COM11 COM10
VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 PA.0 PA.1 PA.2 PA.3 P9.0 P9.1 P9.2 P9.3 P0.0 P0.1 P0.2 P0.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1
COM9
ML63189B
SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32
SEG31
SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
SEG2
Chip size Chip thickness Coordinate origin hole size size Minimum pitch
4.81 5.20 (280 available required) center chip
Note: chip substrate voltage VSS. Figure ML63189B Chip Configuration (Top View)
1-12 M189B M187 M189B
ML63187/189B User's Manual Chapter Overview Table ML63189B Coordinates
name SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 (mm) -2259 -1895 -1755 -1615 -1474 -1334 -1193 -1053 -913 -772 -632 -491 -351 -211 1053 1193 1334 1474 1615 1755 1895 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 (mm) -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2438 -2176 -2036 -1895 -1755 -1615 -1474 -1334 -1193 -1053 -913 name SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 VDD1 VDD2 VDD3 VDD4 VDD5 VDDH Center chip: (mm) (mm) 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 1895 1755 1615 1474 1334 1193 1053 -211 -351 -772 -632 -491 -351 -211 1053 1193 1334 1474 1615 1755 1895 2036 2176 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438
1-13 M187 M189B
ML63187/189B User's Manual Chapter Overview Table ML63189B Coordinates (continued)
name VDDL OSC1 OSC0 RESET TST1 TST2 VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 PA.0 (mm) -491 -632 -772 -913 -1053 -1193 -1334 -1474 -1615 -1755 -1895 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 (mm) 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2132 1895 1755 1615 1474 1334 1193 1053 name PA.1 PA.2 PA.3 P9.0 P9.1 P9.2 P9.3 P0.0 P0.1 P0.2 P0.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 Center chip: (mm) (mm) -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -211 -351 -491 -632 -772 -913 -1053 -1193 -1334 -1474 -1615 -1755 -1895 -2036 -2176
1-14 M189B M187 M189B
ML63187/189B User's Manual Chapter Overview Descriptions 1.6.1 Descriptions Basic Functions Each basic functions each ML63187 ML63189B listed Table 1-4. backslash ("/") name indicates that secondary function. Refer section 1.6.2, "Descriptions Secondary Functions Each Pin." column, indicates power supply pin, indicates input pin, indicates output pin, "I/O" indicates input/output pin. Table Description (Basic Functions)
Classification
name
63187 63189B 63187 63189B
Postive power supply
Function
VDD1 VDD2 VDD3 VDD4 VDD5 Power Supply VDDI VDDL VDDH OSC0 OSC1 Test TST1 TST2
Negative power supply Power supply pins bias (internally generated): Connect capacitors (0.1 between these pins VSS.
Capacitor connection pins bias generation: Connect capacitor (0.1 between
Positive power supply external interface (Power supply input ports) Positive power supply internal logic (internally generated): Connect capacitor (0.1 between VSS.
Multiplied power supply power supply backup (internally generated): Connect capacitor (1.0 between VSS. Capacitor connection pins multiplied power supply: Connect capacitor (1.0 between CB2. Low-speed clock oscillation pins: Crystal oscillation oscillation selected mask option. crystal oscillation selected, connect crystal between XT1, connect capacitor (CG) between VSS. oscillation selected, connect external oscillation resistor (ROSL) between XT1. High-speed clock oscillation pins: Connect ceramic resonator capacitors (CL0, CL1) external oscillation resistor (ROSH) these pins. Input pins testing: Pull-down resistors built-in. Reset input pin: Setting this level causes internal circuitry settings values initialized. Next, this level, execution instructions will begin from address 0000H. pull-down resistor built-in. Melody output (positive phase) Melody output (reversed phase)
Oscillator
Reset
RESET
Melody
1-15 M187 M189B
ML63187/189B User's Manual Chapter Overview Table Description (Basic Functions) (continued)
Classification
name
63187 63189B 63187 63189B
Function
P0.0/INT5 P0.1/INT5 P0.2/INT5 P0.3/INT5 P9.0 P9.1 P9.2 P9.3 PA.0 PA.1 PA.2 Port PA.3 PB.0/INT0/ TM0CAP/ TM0OVF/ PB.1/INT0/ TM1CAP/ TM1OVF PB.2/INT0/ T02CK PB.3/INT0/ T13CK PE.0/SIN PE.1/SOUT PE.2/SCLK PE.3/INT2
4-bit input port: Each selected following. Input with pull-up resistor Input with pull-down resistor High-impedance input 4-bit port: During input mode, each selected following. Input with pull-up resistor Input with pull-down resistor High-impedance input During output mode, each selected following. P-channel open drain output N-channel open drain output CMOS output High-impedance output 4-bit port: During input mode, each selected following. Input with pull-up resistor Input with pull-down resistor High-impedance input During output mode, each selected following. P-channel open drain output N-channel open drain output CMOS output High-impedance output 4-bit port: During input mode, each selected following. Input with pull-up resistor Input with pull-down resistor High-impedance input During output mode, each selected following. P-channel open drain output N-channel open drain output CMOS output High-impedance output 4-bit port: During input mode, each selected following. Input with pull-up resistor Input with pull-down resistor High-impedance input During output mode, each selected following. P-channel open drain output N-channel open drain output CMOS output High-impedance output
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ML63187/189B User's Manual Chapter Overview Table Description (Basic Functions) (continued)
Classification
name
63187 63189B 63187 63189B
Function common signal output pins (COM1 COM16)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
segment signal output pins (SEG0 SEG24)
1-17 M187 M189B
ML63187/189B User's Manual Chapter Overview Table Description (Basic Functions) (continued)
Classification
name
63187 63189B 63187 63189B
Function segment signal output pins (SEG25 SEG63)
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63
1-18 M187 M189B
ML63187/189B User's Manual Chapter Overview 1.6.2 Descriptions Secondary Functions Each secondary functions each ML63187 ML63189B listed Table 1-5.
Table Description (Secondary Functions)
Classification
name
63187 63189B 63187 63189B
Function External interrupt input pins:
PB.0/INT0 PB.1/INT0 PB.2/INT0 PB.3/INT0 External interrupt PE.3/INT2 P0.0/INT5 P0.1/INT5 P0.2/INT5 P0.3/INT5 PB.0/ Capture TM0CAP PB.1/ TM1CAP PB.0/ TM0OVF PB.1/ Timer TM1OVF PB.2/ T02CK PB.3/ T13CK
Changes input signal level cause interrupts generated. Interrupts enabled disabled each port interrupt enable register (PBIE). External interrupt input pin: Changes input signal level cause interrupts generated. External interrupt input pins: Changes input signal level cause interrupts generated. Interrupts enabled disabled each port interrupt enable register (P0IE).
Timer capture trigger input Timer capture trigger input Timer overflow flag output Timer overflow flag output Timer timer external clock input Timer timer external clock input Shift register receive data input Shift register transmit data output Shift register clock input/output pin: This should configured clock output when this device used master processor, clock input when used slave.
PE.0/SIN PE.1/SOUT Shift register PE.2/SCLK
1-19 M187 M189B
ML63187/189B User's Manual Chapter Overview 1.6.3 Unused Processing Table lists handling unused pins.
Table Unused Handling
OSC0, OSC1 CB1, VDD1, VDD3, VDD4, VDD5 TST1, TST2 P0.0-P0.3 P9.0-P9.3 PA.0-PA.3 PB.0-PB.3 PE.0-PE.3 COM1-COM16 SEG0-SEG63 Recommended handling Open Open Open Open Open Open Open Open Open Open Open Open Open
Notes:
high impedance input left unconnected, supply current become excessive. Therefore, recommended that unused input ports input/output ports inputs with either pull-down pull-up resistor. When test pins TST1 TST2 left unconnected, malfunction result there large amount external noise. Therefore, recommended permanently connect TST1 TST2 VSS. Connect capacitor (0.1 between VDD2 when drivers used.
1-20 M187 M189B
ML63187/189B User's Manual Chapter Overview Basic Timing 1.7.1 Basic Timing Operation low-speed oscillation clock from XT0/XT1 pins high-speed oscillation clock from OSC0/OSC1 pins used without frequency division system clock (CLK). system clock signal phase with signal from OSC1 pin. shown Figure 1-7, single machine cycle composed states, state interval from falling edge falling edge next CLK. Instructions processed machine cycle units each instruction executed machine cycles. Instructions classified according number machine cycles: machine cycle instructions (M1), machine cycle instructions M2), machine cycle instructions M3). Most instructions executed machine cycle.
clocks)
clocks)
clocks)
machine cycle
machine cycles
machine cycles
Figure Clock Configuration Each Machine Cycle 1.7.2 Port Basic Timing Figure shows basic timing. During execution instruction that outputs data port, setting data (data output rising edge clock state during machine cycle that instruction. During execution instruction that inputs data from port, data input (data captured internally while clock level state during machine cycle that instruction. That data transferred accumulator start next machine cycle.
1-21 M187 M189B
ML63187/189B User's Manual Chapter Overview
Output instruction
Input instruction
Instruction (example) A,obj
obj,(data
Output
(data
Input
(data
Accumulator
(data
Figure Port Basic Timing
Note:
Regarding input signals will captured internal register level input input even once Figure 1-9) during data capture interval. will captured internal register only level maintained Figure 1-9) throughout data capture interval. Therefore, noise occurs input data, implement noise reduction measures with program peripheral devices.
Input instruction Output instruction
Capture signal
Input Data
Accumulator
Figure Input Data Example
1-22 M187 M189B
ML63187/189B User's Manual Chapter Overview 1.7.3 Interrupt Basic Timing Figure 1-10 shows basic interrupt timing. shown figure, when interrupt factor generated, interrupt factor sampled falling edge interrupt request (IRQ) first half When interrupt condition established receives interrupt, interrupt routine will start beginning from next machine cycle.
Interrupt factor
Process
Main routine
Interrupt routine
interrupt address
Figure 1-10 Interrupt Basic Timing
1-23 M187 M189B
ML63187/189B User's Manual Chapter Overview
1-24 M187 M189B
Chapter
Memory Spaces
M187
M189B
ML63187/189B User's Manual Chapter Memory Spaces
Chapter Memory Spaces
Overview ML63187 ML63189B have internal Oki's original core nX-4/250 core. instruction nX-4/250 core consists types instructions. memory space consists 16-bit wide program memory space 4-bit wide data memory space. stack saving program counter during subroutine call interrupt (call stack) stack saving registers during PUSH instruction (register stack) provided separately from memory space. program memory space used program data, table data melody note data. data memory space, special function registers (SFRs) located BANK display register (DSPR) BANK data BANKS (BANKS ML63187, BANKS ML63189B).
Registers nX-4/250 core processes data mainly with accumulator register set. register programming model consisting registers that store data memory addresses, current bank register (CBR), extra bank register (EBR), register that stores program memory addresses, registers that control program flow, registers that control flags memory.
2.2.1 Accumulator accumulator central register various arithmetic operations. system reset, accumulator initialized "0". When interrupt occurs, "PUSH instruction used necessary save accumulator register stack. accumulator restored with "POP instruction.
2.2.2 Flag Register
Accumulator
flag register consists flags: carry flag (C), zero flag flag (G). When interrupt occurs, "PUSH instruction used necessary save flag register register stack. flag register restored with "POP instruction.
Flag register
2.2.2.1 Carry Flag carry flag 1-bit flag that loaded with carry during addition borrow during subtraction. system reset, carry flag initialized "0". M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces 2.2.2.2 Zero Flag zero flag 1-bit flag that when contents accumulator loaded with "0H". zero flag when contents accumulator loaded with value other than "0H". However, instruction does change zero flag. system reset, zero flag initialized "0".
2.2.2.3 Flag flag changes when registers overflow result execution post-increment register indirect addressing instruction result increment instruction registers. system reset, flag initialized "0".
2.2.3 Master Interrupt Enable Flag (MIE) MIEF 4-bit register which master interrupt enable flag (MIE). (bit MIEF) flag that disables enables interrupts except watchdog timer interrupt. "0", interrupts disabled. "1", interrupts enabled (with exception watchdog timer).
When interrupt received, cleared "0". execution return from interrupt instruction (RTI instruction). multi-level interrupt processing performed, execute instruction during interrupt processing routines. system reset, initialized "0". MIEF only supports data reference data memory through addressing instructions.
MIEF (0FFH)
Master Interrupt Enable Flag Interrupts disabled (initial value) Interrupts enabled
Note:
When setting MIE, "EI" instructions "DI" instructions
M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces 2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR), Register (HL), Register (XY) CBR, EBR, registers used indirect addressing data memory. registers indicate data memory bank. registers indicate addresses bank. also used combination with 8-bit data instruction code direct addressing within current bank. Figure shows various register combinations.
A11-A8
Instruction code 8-bit data A7-A4 A3-A0
Figure Various Register Combinations
Figure indicate data memory addresses nibbles max.). system reset, CBR, EBR, registers initialized "0". When interrupt occurs, "PUSH "PUSH instruction used necessary save CBR, EBR, registers register stack. These registers restored with "POP "POP instruction. CBR, EBR, registers assigned special function register (SFR) addresses 0F9H 0FEH.
(0FDH) (R/W) (0FCH) (R/W) (0FBH) (R/W) (0FAH) (R/W) (0F9H) (R/W)
(0FEH) (R/W)
M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces 2.2.5 Program Counter (PC) program counter (PC) counter with valid bits that specifies program memory space.
2.2.6 Registers (RA3, RA2, RA1, RA0) registers used indirect program memory addressing (ROM table reference instructions). Figure shows address configuration registers.
A15-A12
A11-A8
A7-A4
A3-A0
Figure Address Configuration Registers
Within Figure 2-2, indicate program memory addresses (32K words max.). assigned special function register (SFR) addresses 0F2H 0F5H.
(0F5H) (R/W) (0F4H) (R/W) (0F3H) (R/W) (0F2H) (R/W)
system reset, initialized "0".
Note:
When executing table reference instruction that uses registers, addresses located area transfer table data registers, otherwise indirect addressing program memory will operate properly.
M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces 2.2.7 Stack Pointer (SP) Call Stack stack pointer (SP) pointer that indicates call stack address where program counter saved when subroutine call interrupt occurs. 4-bit up/down counter that incremented during stack saves decremented during stack restores. call stack levels from address address 0FH. Because hardware requires level call stack during program execution, only levels used stack saves. contents call stack cannot read written program. Figure shows relation between call stack.
Call stack
levels
Stack pointer
bits
Figure Relation Between Call Stack
assigned special function register (SFR) address 0F7H.
(0F7H)
system reset, initialized points address "0H" call stack. read-only register writes invalid.
M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces 2.2.8 Register Stack Pointer (RSP) Register Stack register stack pointer (RSP) pointer that indicates register stack address saving various registers. 4-bit up/down counter that incremented during stack saves (execution PUSH instructions) decremented during stack restores (execution instructions). register stack levels from address address 0FH. contents register stack cannot read written program. Figure shows relation between register stack.
Register stack Register stack pointer bits levels
Figure Relation Between Register Stack
various registers shown Figure saved onto restored from register stack PUSH instructions.
"PUSH "POP instruction execution
Register stack "PUSH "POP instruction execution
Register stack
Figure Register Save/Restore Execution PUSH/POP Instructions
assigned special function register (SFR) address 0F6H.
(0F6H) (R/W) rsp3 rsp2 rsp1 rsp0
system reset, initialized points address "0H" register stack. M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces Memory Spaces 2.3.1 Program Memory Space program memory space read-only memory that stores program data. program memory space data length bits extends from address 0000H address 3FFFH ML63187 from address 0000H address 7FFFH ML63189B. addition program data, program memory also store table data melody data. Figure shows configuration program memory space.
7FFFH 7FDFH 3FFFH 3FDFH Test data area words Test data area words
Program data table data Melody data 0037H Interrupt area 0010H 0000H ML63187
16,352 words
Program data table data Melody data 0037H
32,736 words
words 0010H 0000H
Interrupt area
words
ML63189B
Figure Program Memory Space Configuration
After system reset, instruction execution begins address 0000H. interrupt area from address 0010H address 0037H contains starting addresses interrupt processing routines that executed when interrupts generated. (Refer Chapter "ML63187 Interrupt" Chapter "ML63189B Interrupt.")
table data transferred data memory table reference instructions. melody data defines tone, tone length, tone used melody circuit ML63187/189B. After instruction specifies starting address, melody data automatically transferred melody circuit when melody data interrupt occurs. (Refer Chapter "Melody Driver.") Because test data area contains program data testing, cannot used program data area. M187 M189B
ML63187/189B User's Manual Chapter Memory Spaces 2.3.2 Data Memory Space data memory space contains data special function registers (SFRs). data memory consists banks. bank unit nibbles. BANK allocated area, BANK display register, BANK following BANKS data RAM. Figure shows configuration data memory space.
7FFH
BANK7
700H 6FFH
BANK6
5FFH 600H 5FFH
BANK5
500H 4FFH 500H 4FFH
BANK5
Data area (1536 nibbles)
BANK4
400H 3FFH Data area (1024 nibbles) 400H 3FFH
BANK4
BANK3
300H 2FFH 300H 2FFH
BANK3
BANK2
200H 1FFH 200H 1FFH
BANK2
BANK1
100H 0FFH
Display register (256 nibbles) 100H 0FFH
BANK1
Display register (256 nibbles)
BANK0
000H ML63187
area (256 nibbles) 000H
BANK0
area (256 nibbles)
ML63189B
Figure Data Memory Space Configuration
M187 M189B
Chapter
Control Functions
M187
M189B
ML63187/189B User's Manual Chapter Control Functions
Chapter Control Functions
Overview Operating states, including system reset, classified follows. Normal operation mode System reset mode Halt mode Figure shows operating state transition diagram.
Normal operation mode
HALT instruction execution Halt mode Interrupt generated
RESET
RESET
Power detect System reset mode RESET Low-speed clock oscillation halt detect
Figure Operating State Transition Diagram
normal operation mode state which executes instructions sequentially. system reset mode begins when reset input causes begin system reset processing where registers pins initialized. remains this state until instruction execution begins. After system reset processing, instruction execution begins from address 0000H. halt mode state which halted (instruction execution suspended) internal peripheral functions continue operate. During halt mode, incremented. Even upon entering halt mode, port peripheral functions will change. Transfer halt mode accomplished executing "HALT" instruction. M187 M189B
ML63187/189B User's Manual Chapter Control Functions System Reset Mode (RST) 3.2.1 Transfer State System Reset Mode following three factors cause transfer system reset mode. Setting RESET level Detection power Detection that low-speed clock oscillation halted following operations performed system reset mode. initialized. Backup flag changes backup circuit changes state. Bias reference voltage supply (VR) energized. driver outputs turned outputs change level. special function registers (SFRs) initialized. However, data display registers initialized. After system reset processing, instruction execution begins from address 0000H. Figures show system reset generator circuit signals when system reset generated.
RESET
Power detect
RESET0 (Time base counter reset) RESETS (System reset)
Low-speed clock oscillation halt detect
Figure System Reset Generator Circuit
RESET0 Crystal oscillation output RESETS 62.5 Backup start 32.768
Figure Signals When System Reset Generated
Note:
System reset takes priority over other processing terminates processing that point time. Therefore, contents display registers, which initialized, cannot guaranteed after system reset. M187 M189B
ML63187/189B User's Manual Chapter Control Functions Halt Mode 3.3.1 Transfer State Halt Mode Transfer halt mode performed software when HALT instruction executed. When HALT instruction executed, enters HALT mode state HALT instruction. Oscillation time base counter operation continue while halt mode.
interrupt request occurs same time execution HALT instruction, interrupt processing priority HALT instruction will executed. After HALT instruction performs equivalent operation instruction, interrupt routine entered. When instruction used complete interrupt routine, main routine resumed beginning from instruction immediately following HALT instruction.
Figure shows timing when HALT instruction interrupt request occur simultaneously.
HALT System clock (halt flag) Interrupt request
flow main routine
HALT instruction execution (equivalent NOP) (INT)
Interrupt routine
instruction execution
(RTI)
Main routine
HALT instruction address (INT) Starting address interrupt routine (RTI) instruction address
Figure Timing Simultaneous HALT Instruction Interrupt Request
Note:
While interrupt request generated, execution HALT instruction will transfer operation halt mode.
M187 M189B
ML63187/189B User's Manual Chapter Control Functions 3.3.2 Halt Mode Release following methods available release halt mode. Release interrupt generation (transfer normal operation mode) Release RESET (transfer system reset mode) 3.3.2.1 Release Halt Mode Interrupt halt mode released interrupt, enable flag interrupt used release must prior entering halt mode. When halt mode released interrupt, operation transfers normal operation mode. Figure shows timing transferring halt mode execution HALT instruction releasing halt mode interrupt. When halt mode released interrupt request, first instruction immediately following HALT instruction executed then interrupt routine entered. When instruction used complete interrupt routine, main routine resumed beginning from second instruction after HALT instruction.
HALT System clock (halt flag) Interrupt request HALT instruction execution Halt mode
Execution instruction immediately after HALT instruction
Interrupt routine
flow main routine
(INT)
Main instruction routine execution (RTI)
HALT instruction address (INT) Starting address interrupt routine (RTI) instruction address
Figure Timing Transfer Halt Mode Release Halt Mode Interrupt
Note:
halt mode released, individual interrupt enable flags "1". individual interrupt enable flag "0", corresponding interrupt request signal cannot reset flag, regardless whether master interrupt enable flag (MIE) "1".
3.3.2.2 Release Halt Mode RESET high-level input RESET pin, released from halt mode transfers system reset mode. M187 M189B
ML63187/189B User's Manual Chapter Control Functions 3.3.3 Melody Data Interrupt Halt Mode Release halt mode released melody data interrupt. melody data interrupt different from conventional interrupt that melody data interrupt hardware processing interrupt used transfer melody data melody circuit. dependent program. When this interrupt generated, instruction immediately after HALT instruction executed, then melody data transferred melody circuit, HALT instruction executed again. This sequence indicated Figure 3-6.
HALT System Clock (halt flag) Melody data request HALT instruction execution Melody data transfer HALT instruction execution HALT
Halt mode
flow main routine
Execution instruction immediately after HALT instruction
Halt mode
(melody)
HALT instruction address (melody) Melody data address
Figure Melody Data Request Interrupt Operation
3.3.4 Note Concerning HALT Instruction described above, instruction immediately after HALT instruction executed number times. this reason, always place instruction immediately after HALT instruction.
(Example)
HALT
M187 M189B
ML63187/189B User's Manual Chapter Control Functions
M187 M189B
Chapter
ML63187 Interrupt (INT187)
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187)
Chapter ML63187 Interrupt (INT187)
Overview ML63187 supports interrupt factors: external interrupts internal interrupts. With exception watchdog timer interrupt, interrupt enable/disable controlled master interrupt enable flag (MIE) individual interrupt enable registers (IE0 IE4). Watchdog timer interrupt non-maskable interrupt. When interrupt conditions met, interrupt routine executed from interrupt start address. Table indicates list interrupt factors, Figure shows interrupt control equivalent circuit.
Table List Interrupt Factors
Priority Interrupt factor Watchdog timer interrupt Melody interrupt External interrupt 4-bit input) External interrupt (PE.3) Timer interrupt Timer interrupt Timer interrupt Timer interrupt Shift register interrupt interrupt interrupt interrupt interrupt interrupt Symbol WDTINT MDINT XI0INT XI2INT TM0INT TM1INT TM2INT TM3INT SFTINT T10HzINT 32HzINT 16HzINT 4HzINT 2HzINT Interrupt start address 0010H 0012H 0014H 0018H 0020H 0022H 0024H 0026H 002CH 002EH 0030H 0032H 0034H 0036H
multiple interrupts detected simultaneously, lowest interrupt start address given priority. details interrupt operation, refer Chapter (Time Base Counter), Chapter (Timers), Chapter (100 Timer Counter), Chapter (Watchdog Timer), Chapter (Ports), Chapter (Melody Driver), Chapter (Shift Register).
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187)
Master interrupt enable flag Interrupt request signals Interrupt request registers IRQ0 IRQ0.0 QWDT MDINT XI0INT IRQ0.1 IRQ0.2 QXI0 IE0.1 IE0.2 EXI0 IE1.0 EXI2 Interrupt enable registers
WDTINT
XI2INT
IRQ1 IRQ1.0 QXI2
TM0INT TM1INT TM2INT TM3INT
IRQ2 IRQ2.0 QTM0 IRQ2.1 IRQ2.2 IRQ2.3 QTM1 QTM2 QTM3
IE2.0 IE2.1 IE2.2 IE2.3 ETM0
Interrupt request
Priority encoder
ETM1 ETM2 ETM3
Interrupt vector address
SFTINT T10HzINT
IRQ3 IRQ3.2 IRQ3.3
QSFT Q10Hz
IE3.2 IE3.3
ESFT E10Hz
32HzINT 16HzINT 4HzINT 2HzINT
IRQ4 IRQ4.0 Q32Hz IRQ4.1 IRQ4.2 IRQ4.3 Q16Hz Q4Hz Q2Hz
IE4.0 IE4.1 IE4.2 IE4.3 E32Hz E16Hz E4Hz E2Hz
Figure ML63187 Interrupt Control Equivalent Circuit
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187) Interrupt Registers following three types registers used control interrupts. Master interrupt enable register (MIEF) Interrupt enable registers (IE0 IE4) Interrupt request registers (IRQ0 IRQ4) These registers described below. Master interrupt enable register (MIEF) MIEF 4-bit register which master interrupt enable flag (MIE). (bit MIEF) flag that disables enables interrupts except watchdog timer interrupt. "0", interrupts disabled. "1", interrupts enabled (with exception watchdog timer). When interrupt received, cleared "0". execution return from interrupt instruction (RTI instruction). multi-level interrupt processing performed, execute instruction during interrupt processing routines. system reset, initialized "0". MIEF only supports data reference data memory through addressing instructions.
MIEF (0FFH) Master Interrupt Enable Flag Interrupts disabled (initial value) Interrupts enabled
Note:
When setting MIE, "EI" instructions "DI" instructions
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187) Interrupt enable registers (IE0 IE4) IE0, IE1, IE2, IE3, registers that consist bits each. logical corresponding bits interrupt enable register (IE0 IE4) interrupt request register (IRQ0 IRQ4) determines whether each interrupt request issued CPU. watchdog timer interrupt non-maskable, therefore dependent upon interrupt enable registers (IE0 IE4) master interrupt enable register (MIEF). multiple interrupts request same time, shown Table 4-1, interrupts accepted order highest priority priority interrupts placed hold. When interrupt received, master interrupt enable flag (MIE) cleared "0". corresponding bits interrupt enable registers (IE0 IE4) change. system reset, each through initialized "0".
(050H) (R/W) External interrupt enable flag Disable (initial value) Enable Melody interrupt enable flag Disable (initial value) Enable (051H) (R/W) External interrupt enable flag Disable (initial value) Enable (052H) (R/W) Timer interrupt enable flag Disable (initial value) Enable Timer interrupt enable flag Disable (initial value) Enable Timer interrupt enable flag Disable (initial value) Enable Timer interrupt enable flag Disable (initial value) Enable ETM3 ETM2 ETM1 ETM0 EXI2 EXI0
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187)
(053H) (R/W) interrupt enable flag Disable (initial value) Enable Shift register interrupt enable flag Disable (initial value) Enable
E10Hz
ESFT
E4Hz E16Hz E32Hz
(054H) (R/W) interrupt enable flag Disable (initial value) Enable interrupt enable flag Disable (initial value) Enable interrupt enable flag Disable (initial value) Enable interrupt enable flag Disable (initial value) Enable
E2Hz
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187) Interrupt request registers (IRQ0 IRQ4) IRQ0, IRQ1, IRQ2, IRQ3 IRQ4 registers that consist bits each. When interrupt request generated, corresponding interrupt request register first half state next instruction. that receive interrupt requests, master interrupt enable flag (MIE) appropriate flag corresponding interrupt enable register (IE0 IE4) "1". watchdog timer interrupt non-maskable does depend upon interrupt enable register master interrupt enable register (MIE). Setting appropriate bits interrupt request register allows software interrupts generated. When interrupt request received, corresponding bits IRQ0 IRQ4 cleared "0". system reset, each IRQ0 through IRQ4 initialized "0".
IRQ0 (055H) (R/W) External interrupt request flag request (initial value) Request Melody interrupt request flag request (initial value) Request Watchdog timer interrupt request flag request (initial value) Request QXI0 QWDT
QXI0 (reQuest eXternal Interrupt external interrupt request flag. external interrupt assigned secondary function each port (PB.0 PB.3). External interrupt requests generated 4-bit ORed input. (reQuest Melody Driver) Melody interrupt request flag. Melody interrupts generated when melody driver outputs note data (END "1"). QWDT (reQuest WatchDog Timer) Watchdog timer interrupt request flag. When watchdog timer started then overflow occurs, interrupt requested. watchdog timer interrupt non-maskable does depend upon interrupt enable registers master interrupt enable register (MIE). M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187)
IRQ1 (056H) (R/W) External interrupt request flag request (initial value) Request
QXI2
QXI2 (reQuest eXternal Interrupt External interrupt request flag. external interrupt assigned secondary function port (PE.3). Generation external interrupt triggered falling edge output time base counter.
IRQ2 (057H) (R/W) Timer interrupt request flag request (initial value) Request Timer interrupt request flag request (initial value) Request Timer interrupt request flag request (initial value) Request Timer interrupt request flag request (initial value) Request QTM3 QTM2 QTM1 QTM0
QTM3 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. QTM2 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. QTM1 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. QTM0 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187)
IRQ3 (058H) (R/W) interrupt request flag request (initial value) Request Shift register interrupt request flag request (initial value) Request
Q10Hz
QSFT
Q10Hz (reQuest interrupt request flag. interrupt request generated whenever carry generated timer counter output. QSFT (reQuest ShiFT register) Shift register interrupt request flag. shift register interrupt generated when 8-bit data transfer shift register completed.
IRQ4 (059H) (R/W) interrupt request flag request (initial value) Request interrupt request flag request (initial value) Request interrupt request flag request (initial value) Request interrupt request flag request (initial value) Request Q2Hz Q4Hz Q16Hz Q32Hz
Q2Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. Q4Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. bit1: Q16Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. Q32Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187) Interrupt Sequence 4.3.1 Interrupt Processing While "1", operation transfers interrupt processing when individual interrupt factors generated. watchdog timer interrupt non-maskable regardless flag status, operation will shift interrupt processing when watchdog timer interrupt factor generated. following processes performed when interrupt generated. corresponding interrupt request flag cleared "0". program counter (PC) saved call stack. call stack pointer (SP) incremented starting address interrupt routine loaded into program counter (PC). Interrupt processing performed machine cycles. Figure shows stack contents after interrupt generated.
position before interrupt position after interrupt
PC13- PC12
PC3-PC0
PC11-PC8
PC7-PC4
Figure Call Stack Contents after Interrupt Generation
M187
ML63187/189B User's Manual Chapter ML63187 Interrupt (INT187) 4.3.2 Return from Interrupt Routine Return from watchdog timer interrupt routine performed with "RTNMI" instruction. Return from other interrupt routines performed with "RTI" instruction. Execution "RTI" "RTNMI" instructions both require machine cycle. When returning from interrupt routine, performs following processes. call stack pointer (SP) decremented (when "RTNMI" instruction used, restored state prior interrupt). added call stack contents that value loaded into program counter (PC).
Notes:
While flag (interrupt disabled state), watchdog timer interrupt processed "RTI" instruction executed, flag will interrupts enabled. "RTNMI" instructions return from watchdog timer interrupts only. "RTI" instructions normal interrupts.
4.3.3 Interrupt Hold Instructions Interrupt requests received during execution following instructions. These instructions processed with priority, interrupt processing delayed until completion instruction. table reference instructions Stack operation instructions Jump instructions Conditional branch instructions Call/return instructions "EI" (set flag) instructions, "DI" (clear flag) instructions "MSA cadr15" (start melody output) instructions within control instructions
Note:
above instructions used consecutively, even interrupt generated, that interrupt hold considerable amount time before interrupt routine begins.
4-10 M187
Chapter
ML63189B Interrupt (INT189)
M189B
ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189)
Chapter ML63189B Interrupt (INT189)
Overview ML63189B supports interrupt factors: external interrupts internal interrupts. With exception watchdog timer interrupt, interrupt enable/disable controlled master interrupt enable flag (MIE) individual interrupt enable registers (IE0 IE4). Watchdog timer interrupt non-maskable interrupt. When interrupt conditions met, interrupt routine executed from interrupt start address. Table indicates list interrupt factors, Figure shows interrupt control equivalent circuit.
Table List Interrupt Factors
Priority Interrupt factor Watchdog timer interrupt Melody interrupt External interrupt 4-bit input) External interrupt (PE.3) External interrupt 4-bit input) Timer interrupt Timer interrupt Timer interrupt Timer interrupt Shift register interrupt interrupt interrupt interrupt interrupt interrupt Symbol WDTINT MDINT XI0INT XI2INT XI5INT TM0INT TM1INT TM2INT TM3INT SFTINT T10HzINT 32HzINT 16HzINT 4HzINT 2HzINT Interrupt start address 0010H 0012H 0014H 0018H 001EH 0020H 0022H 0024H 0026H 002CH 002EH 0030H 0032H 0034H 0036H
multiple interrupts detected simultaneously, lowest interrupt start address given priority. details interrupt operation, refer Chapter (Time Base Counter), Chapter (Timers), Chapter (100 Timer Counter), Chapter (Watchdog Timer), Chapter (Ports), Chapter (Melody Driver), Chapter (Shift Register).
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ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189)
Master interrupt enable flag Interrupt request signals Interrupt request registers IRQ0 IRQ0.0 QWDT MDINT XI0INT IRQ0.1 IRQ0.2 QXI0 IE0.1 IE0.2 EXI0 IE1.0 IE1.3 EXI2 EXI5 Interrupt enable registers
WDTINT
XI2INT XI5INT
IRQ1 IRQ1.0 QXI2 IRQ1.3 QXI5
TM0INT TM1INT TM2INT TM3INT
IRQ2 IRQ2.0 QTM0 IRQ2.1 IRQ2.2 IRQ2.3 QTM1 QTM2 QTM3
IE2.0 IE2.1 IE2.2 IE2.3 ETM0
Priority encoder
Interrupt request
ETM1 ETM2 ETM3
Interrupt vector address
SFTINT T10HzINT
IRQ3 IRQ3.2 IRQ3.3
QSFT Q10Hz
IE3.2 IE3.3
ESFT E10Hz
32HzINT 16HzINT 4HzINT 2HzINT
IRQ4 IRQ4.0 Q32Hz IRQ4.1 IRQ4.2 IRQ4.3 Q16Hz Q4Hz Q2Hz
IE4.0 IE4.1 IE4.2 IE4.3 E32Hz E16Hz E4Hz E2Hz
Figure ML63189B Interrupt Control Equivalent Circuit
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ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189) Interrupt Registers following three types registers used control interrupts. Master interrupt enable register (MIEF) Interrupt enable registers (IE0 IE4) Interrupt request registers (IRQ0 IRQ4) These registers described below. Master interrupt enable register (MIEF) MIEF 4-bit register which master interrupt enable flag (MIE). (bit MIEF) flag that disables enables interrupts except watchdog timer interrupt. "0", interrupts disabled. "1", interrupts enabled (with exception watchdog timer). When interrupt received, cleared "0". execution return from interrupt instruction (RTI instruction). multi-level interrupt processing performed, execute instruction during interrupt processing routines. system reset, initialized "0". MIEF only supports data reference data memory through addressing instructions.
MIEF (0FFH) Master Interrupt Enable Flag Interrupts disabled (initial value) Interrupts enabled
Note:
When setting MIE, "EI" instructions "DI" instructions
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ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189) Interrupt enable registers (IE0 IE4) IE0, IE1, IE2, IE3, registers that consist bits each. logical corresponding bits interrupt enable register (IE0 IE4) interrupt request register (IRQ0 IRQ4) determines whether each interrupt request issued CPU. watchdog timer interrupt non-maskable, therefore dependent upon interrupt enable registers (IE0 IE4) master interrupt enable register (MIEF). multiple interrupts request same time, shown Table 5-1, interrupts accepted order highest priority priority interrupts placed hold. When interrupt received, master interrupt enable flag (MIE) cleared "0". corresponding bits interrupt enable registers (IE0 IE4) change. system reset, each through initialized "0".
(050H) (R/W) External interrupt enable flag Disable (initial value) Enable Melody interrupt enable flag Disable (initial value) Enable (051H) (R/W) External interrupt enable flag Disable (initial value) Enable External interrupt enable flag Disable (initial value) Enable EXI5 EXI2 EXI0
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ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189)
(052H) (R/W) Timer interrupt enable flag Disable (initial value) Enable Timer interrupt enable flag Disable (initial value) Enable Timer interrupt enable flag Disable (initial value) Enable Timer interrupt enable flag Disable (initial value) Enable E10Hz ETM3
ETM2
ETM1
ETM0
(053H) (R/W) interrupt enable flag Disable (initial value) Enable Shift register interrupt enable flag Disable (initial value) Enable
ESFT
(054H) (R/W) interrupt enable flag Disable (initial value) Enable interrupt enable flag Disable (initial value) Enable interrupt enable flag Disable (initial value) Enable interrupt enable flag Disable (initial value) Enable E2Hz
E4Hz
E16Hz
E32Hz
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ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189) Interrupt request registers (IRQ0 IRQ4) IRQ0, IRQ1, IRQ2, IRQ3 IRQ4 registers that consist bits each. When interrupt request generated, corresponding interrupt request register first half state next instruction. that receive interrupt requests, master interrupt enable flag (MIE) appropriate flag corresponding interrupt enable register (IE0 IE4) "1". watchdog timer interrupt non-maskable does depend upon interrupt enable register master interrupt enable register (MIE). Setting appropriate bits interrupt request register allows software interrupts generated. When interrupt request received, corresponding bits IRQ0 IRQ4 cleared "0". system reset, each IRQ0 through IRQ4 initialized "0".
IRQ0 (055H) (R/W) External interrupt request flag request (initial value) Request Melody interrupt request flag request (initial value) Request Watchdog timer interrupt request flag request (initial value) Request QXI0 QWDT
QXI0 (reQuest eXternal Interrupt external interrupt request flag. external interrupt assigned secondary function each port (PB.0 PB.3). External interrupt requests generated 4-bit ORed input. (reQuest Melody Driver) Melody interrupt request flag. Melody interrupts generated when melody driver outputs note data (END "1"). QWDT (reQuest WatchDog Timer) Watchdog timer interrupt request flag. When watchdog timer started then overflow occurs, interrupt requested. watchdog timer interrupt non-maskable does depend upon interrupt enable registers master interrupt enable register (MIE). M189B
ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189)
IRQ1 (056H) (R/W) External interrupt request flag request (initial value) Request External interrupt request flag request (initial value) Request
OXI5
OXI2
QXI5 (reQuest eXternal Interrupt External interrupt request flag. external interrupt assigned secondary function each (P0.0 0.3) port external interrupt request generated through 4-bit ORed input. QXI2 (reQuest eXternal Interrupt External interrupt request flag. external interrupt assigned secondary function port (PE.3). Generation external interrupt triggered falling edge output time base counter.
IRQ2 (057H) (R/W) Timer interrupt request flag request (initial value) Request Timer interrupt request flag request (initial value) Request Timer interrupt request flag request (initial value) Request Timer interrupt request flag request (initial value) Request QTM3 QTM2 QTM1 QTM0
QTM3 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. QTM2 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. QTM1 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. QTM0 (reQuest TiMer Timer interrupt request flag. timer interrupt request generated whenever timer overflows. M189B
ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189)
IRQ3 (058H) (R/W) interrupt request flag request (initial value) Request Shift register interrupt request flag request (initial value) Request
Q10Hz
QSFT
Q10Hz (reQuest interrupt request flag. interrupt request generated whenever carry generated timer counter output. QSFT (reQuest ShiFT register) Shift register interrupt request flag. shift register interrupt generated when 8-bit data transfer shift register completed.
IRQ4 (059H) (R/W) interrupt request flag request (initial value) Request interrupt request flag request (initial value) Request interrupt request flag request (initial value) Request interrupt request flag request (initial value) Request Q2Hz Q4Hz Q16Hz Q32Hz
Q2Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. Q4Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. bit1: Q16Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. Q32Hz (reQuest interrupt request flag. interrupt request generated every falling edge output time base counter. M189B
ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189) Interrupt Sequence 5.3.1 Interrupt Processing While "1", operation transfers interrupt processing when individual interrupt factors generated. watchdog timer interrupt non-maskable regardless flag status, operation will shift interrupt processing when watchdog timer interrupt factor generated. following processes performed when interrupt generated. corresponding interrupt request flag cleared "0". program counter (PC) saved call stack. call stack pointer (SP) incremented starting address interrupt routine loaded into program counter (PC). Interrupt processing performed machine cycles. Figure shows stack contents after interrupt generated.
position before interrupt position after interrupt
PC13- PC12
PC3-PC0
PC11-PC8
PC7-PC4
Figure Call Stack Contents after Interrupt Generation
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ML63187/189B User's Manual Chapter ML63189B Interrupt (INT189) 5.3.2 Return from Interrupt Routine Return from watchdog timer interrupt routine performed with "RTNMI" instruction. Return from other interrupt routines performed with "RTI" instruction. Execution "RTI" "RTNMI" instructions both require machine cycle. When returning from interrupt routine, performs following processes. call stack pointer (SP) decremented (when "RTNMI" instruction used, restored state prior interrupt). added call stack contents that value loaded into program counter (PC).
Notes:
While flag (interrupt disabled state), watchdog timer interrupt processed "RTI" instruction executed, flag will interrupts enabled. "RTNMI" instructions return from watchdog timer interrupts only. "RTI" instructions normal interrupts.
5.3.3 Interrupt Hold Instructions Interrupt requests received during execution following instructions. These instructions processed with priority, interrupt processing delayed until completion instruction. table reference instructions Stack operation instructions Jump instructions Conditional branch instructions Call/return instructions "EI" (set flag) instructions, "DI" (clear flag) instructions "MSA cadr15" (start melody output) instructions within control instructions
Note:
above instructions used consecutively, even interrupt generated, that interrupt hold considerable amount time before interrupt routine begins.
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Chapter
Clock Generator Circuit (OSC)
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC)
Chapter Clock Generator Circuit (OSC)
Overview clock generator circuit (OSC) consists low-speed clock generator circuit, highspeed clock generator circuit clock controller unit. clock generator circuit generates system clock (CLK), time base clock (TBCCLK) high-speed clock (HSCLK). following modes selected low-speed clock generator circuit highspeed clock generator circuit. Low-speed clock generator circuit: crystal oscillation mode oscillation mode (mask option selection) High-speed clock generator circuit: ceramic oscillation mode oscillation mode (software selection)
system clock basic operation clock CPU. time base clock basic operation clock time base counter. Depending contents frequency control register (FCON), system clock frequency switched either output low-speed clock oscillation circuit (TBCCLK) output high-speed clock oscillation circuit (HSCLK). frequency control register (FCON) also controls modes high-speed clock oscillation circuit. Clock Generator Circuit Configuration Figure shows block diagram clock generator circuit.
VDDL Low-speed clock output
External circuit
Time base clock (TBCCLK)
Low-speed clock oscillation circuit
VDDH OSC1 High-speed clock output
External circuit
TBCCLK HSCLK System clock (CLK) High-speed clock (HSCLK)
RC/ceramic oscillation select
Clock select control
OSC0
Oscillation enable High-speed clock oscillation circuit FCON WRITE FCON Data
Figure Clock Generator Circuit Configuration M187 M189B
ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) Low-Speed Clock Generator Circuit low-speed clock generator circuit modes that selected mask option, oscillation mode crystal oscillation mode. oscillation frequency kHz. oscillation mode, attach external resistor, ROSL, shown Figure 6-2(a). crystal oscillation mode, attach external crystal unit capacitor, shown Figure 6-2(b).
VDDL
Low-speed clock output
ROSL
Inside External Circuit Oscillation Mode VDDL
Low-speed clock output
Crystal
Inside
External Circuit Crystal Oscillation Mode
Figure External Circuits Low-Speed Clock Oscillation
Note:
convenience, descriptions this manual assume that 32.768 crystal unit used low-speed clock oscillation circuit. method specifying mask options low-speed clock oscillation circuit, "Appendix Mask Option."
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) Table lists typical values oscillation frequency when low-speed side oscillation mode selected. Table shows example external component attached when low-speed side crystal oscillation mode selected.
Table Typical Oscillation Frequencies Low-Speed Side Oscillation Mode
ROSL fROSL ±30% ±30% ±30%
Table Example External Component Low-Speed Side Crystal Oscillation Mode
32.768
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) High-Speed Clock Generator Circuit high-speed clock generator circuit modes, oscillation mode ceramic oscillation mode. Oscillation modes OSCSEL (bit FCON). maximum oscillation frequency MHz. OSCSEL oscillation mode OSCSEL ceramic oscillation mode
high-speed clock used, leave OSC0 OSC1 pins open (unconnected). oscillation mode, attach external resistor, ROSH, shown Figure 6-3(a). ceramic oscillation mode, attach external ceramic unit capacitors shown Figure 6-3(b).
OSC1 VDDH ROSH VDDH Oscillation enable High-speed clock output
OSC0
External Circuit Oscillation Mode Ceramic resonator
OSC1 VDDH VDDH
OSC0 High-speed clock output Oscillation enable External Circuit Ceramic Oscillation Mode
Figure External Circuits High-Speed Clock Oscillation
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) Table lists typical values oscillation frequency when high-speed side oscillation mode selected. Table lists example external components attached when highspeed side ceramic oscillation mode selected.
Table Typical Oscillation Frequencies High-Speed Side Oscillation Mode
ROSH (kW) Backup flag fROSH ±30% ±30% ±30% ±30% ±30% 1.35 ±30% ±30%
Table Example External Components High-Speed Side Ceramic Oscillation Mode
(pF) (pF) Ceramic unit CSB200D (200 kHz)* CSB300D (300 kHz)* CSB500E (500 kHz)* CSB1000J MHz)* CSA2.00MG MHz)*
Ceramic unit manufactured Murata MFG. Co., Ltd.
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) System Clock Control system clock basic operation clock CPU. clock selected follows with CPUCLK (bit FCON) setting. CPUCLK (initial value) output low-speed clock generator circuit (TBCCLK) system clock. CPUCLK output high-speed clock generator circuit (HSCLK) system clock. When HSCLK selected system clock, high-speed clock must oscillating state (ENOSC "1"). crystal generator circuit will continue oscillate even when high-speed generator circuit selected.
reduce total power consumption applications that high-speed clock generator circuit, following clock controls generally implemented software. During normal operation, output low-speed clock generator circuit (CPUCLK "0") should system clock. Only when high-speed operation necessary should high-speed clock oscillate (ENOSC "1") output high-speed clock generator circuit (CPUCLK "1") should selected.
details system clock select timing, refer section 6.7, "System Clock Select Timing."
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) Frequency Control Register (FCON) FCON special function register (SFR) that selects system clock.
FCON (062H) (R/W) OSCSEL ENOSC CPUCLK
oscillation/ceramic oscillation mode select oscillation mode (initial value) Ceramic oscillation mode High-speed clock oscillation start/stop select Oscillation stop (initial value) Oscillation start System clock select Low-speed clock oscillation output (initial value) High-speed clock oscillation output
OSCSEL This selects oscillation mode ceramic oscillation mode highspeed clock generator circuit. system reset, this cleared "0", selecting oscillation mode.
ENOSC This starts stops oscillation high-speed clock generator circuit. system reset, this cleared "0", stopping oscillation high-speed clock generator circuit.
CPUCLK This selects system clock, basic operation clock CPU. system reset, this cleared "0", selecting output low-speed clock generator circuit (TBCCLK).
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) System Clock Select Timing After system reset, system clock TBCCLK. When high-speed operation necessary, switch system clock HSCLK. flowchart system clock operation shown below.
System clock status TBCCLK (Low-speed clock generator circuit output) Software processing After system reset, lowspeed clock generator output system clock.
Software processing High-speed clock oscillation mode select OSCSEL (bit FCON) setting OSCSEL oscillation mode (initial value) OSCSEL Ceramic oscillation mode
High-speed clock oscillation stop ENOSC (bit FCON) ENOSC Stop high-speed clock oscillation (initial value) ENOSC Start high-speed clock oscillation Low-speed clock oscillation output select CPUCLK (bit FCON) CPUCLK Low-speed clock oscillation output (initial value) CPUCLK High-speed clock oscillation output
High-speed clock oscillation start ENOSC (bit FCON) ENOSC Stop high-speed clock oscillation (initial value) ENOSC Start high-speed clock oscillation Wait: When oscillation mode selected: more When ceramic oscillation mode selected: more High-speed clock oscillation output select CPUCLK (bit FCON) CPUCLK Low-speed clock oscillation output (initial value) CPUCLK High-speed clock oscillation output
HSCLK (High-speed clock generator circuit output)
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC) When ENOSC (bit FCON) "1", oscillation starts mode selected OSCSEL. same time, internal logic power supply (VDDL) switches from constant voltage circuit output level (approx. VDDH level. Next, CPUCLK "1", system clock switches from crystal oscillation output (TBCCLK) high-speed clock output (HSCLK).
Figure shows system clock select timing status internal logic power supply (VDDL).
ENOSC CPUCLK OSC1
TWAIT
System clock Low-speed clock
High-speed clock
Low-speed clock
Internal logic power supply VDDL
high-speed clocks
low-speed clocks VDDH Approx. (typ.)
Figure System Clock Select Timing
ceramic oscillation mode, required from time when ENOSC until high-speed clock generator circuit enters oscillating state. Therefore, this mode, when switching CPUCLK high-speed setting, wait interval least TWAIT after rising edge ENOSC.
oscillation mode, oscillation begins soon after setting ENOSC "1". When switching CPUCLK high-speed setting, wait interval least TWAIT after rising edge ENOSC.
When switching from high-speed mode low-speed mode, CPUCLK "0", sometime after next instruction, ENOSC "0". details regarding constant voltage circuit internal logic power supply, refer Chapter "Backup Circuit."
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ML63187/189B User's Manual Chapter Clock Generator Circuit (OSC)
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Chapter
Time Base Counter (TBC)
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ML63187/189B User's Manual Chapter Time Base Counter (TBC)
Chapter Time Base Counter (TBC)
Overview time base counter (TBC) 15-bit internal counter, which generates clock supplied internal peripheral functions. clock time base clock (TBCCLK). outputs used functions such time base interrupts various other circuits. TBC8-11 TBC12-15 read/reset software. generates interrupt request falling edge Hz/16 Hz/4 Hz/2 output. initialized 0000H system reset.
Time Base Counter Configuration configuration time base counter (TBC) shown Figure 7-1.
TBCR0 READ TBCR1 READ TBCR1 WRITE TBCR0 WRITE 2HzINT 4HzINT TBC15 TBC14 TBC13 TBC12
Data
TBC11 TBC10 TBC9 TBC8
(128
16HzINT 32HzINT (1/32768TBC) (1/16384TBC) (1/8192TBC) (1/4096TBC) (1/2048TBC) (1/1024TBC) (1/512TBC) (1/256TBC) (1/128TBC) (1/64TBC) (1/32TBC) (1/16TBC) (1/8TBC) (1/4TBC) (1/2TBC)
TBC7 TBC6 TBC5 RESET0 TBC4 TBC3 TBC2 TBCCLK (32.768 kHz) TBC1
(256 (512 kHz) kHz) kHz) kHz) kHz)
Figure Time Base Counter (TBC) Configuration (when 32.768 crystal used low-speed clock oscillation) M187 M189B
ML63187/189B User's Manual Chapter Time Base Counter (TBC) Time Base Counter Registers Time base counter register (TBCR0), time base counter register (TBCR1) These 4-bit special function registers (SFRs) used read outputs time base counter. write operation TBCR0 sets both outputs "0", write operation TBCR1 sets output "0".
TBCR0 (060H) (R/W) TBCR1 (061H) (R/W)
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ML63187/189B User's Manual Chapter Time Base Counter (TBC) Time Base Counter Operation After system reset time base counter (TBC) begins count from 0000H. count incremented falling edge TBCCLK. Hz/16 Hz/4 Hz/2 outputs used time base interrupts. each output falling edge, four bits interrupt request register (IRQ4) "1", namely (Q32Hz), (Q16Hz), (Q4Hz) (Q2Hz), requesting interrupt CPU. outputs also used clocks various circuits. output output read through time base counter register (TBCR0/TBCR1). write operation TBCR1 sets output counter "0", write operation TBCR0 sets both output counters "0". write data these write operations significance. example, "MOV TBCR0, instruction used write, dependent accumulator content way. When write executed TBCR0 TBCR1 counters reset, interrupt requests generated Hz/16 Hz/4 Hz/2 outputs have been "1". disable these interrupts, first master interrupt enable flag (MIE) interrupt enable register (IE4) "0", execute write operation TBCR 0/1, interrupt request flag (IRQ4) "0". Figure shows interrupt generation timing time base counter output reset timing writing TBCR0 TBCR1.
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ML63187/189B User's Manual Chapter Time Base Counter (TBC)
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Write TBCR0 Write TBCR1
second -1/16 -1/256 second Shows interrupt timing
Figure Interrupt Timing Reset Timing Writing TBCR0, TBCR1
Chapter
Timers (TIMER)
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ML63187/189B User's Manual Chapter Timers (TIMER)
Chapter Timers (TIMER)
Overview ML63187/189B have four internal 8-bit timers Timers timers used tandem 16-bit timer. Timers have three operation modes: auto-reload mode, capture mode frequency measurement mode. Timers have modes: auto-reload frequency measurement. Timer clock time base clock (TBCCLK: 32.768 kHz), high-speed clock (HSCLK), external clock. When using timers 16-bit timer, overflow signals timers used clocks timers respectively. addition pulse generation time measurement, timers also used.
Timer 8-bit timer 16-bit timer (Timer overflow signal used clock timer Clock Auto-reload mode Capture mode Frequency measurement mode (Timer overflow signal used clock timer Timer Timer Timer
TBCCLK HSCLK External clock (T02CK, T13CK)
Timer Configuration Figures through show configuration timers
Data TBCCLK HSCLK PB.2/T02CK 437C PB.0/TM0CAP TM0CK Control circuit TM0CL Capture
Frequency measurement control circuit
TM0CH Reload TM0CK TM0DH RESETS PB.0/TM0OVF overflow TM0INT
TM0DL
Capture control circuit
TM0CAP
437C
Figure Timer Configuration M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER)
Data TBCCLK HSCLK PB.3/T13CK overflow Control circuit TM1CK TM1CL Capture PB.1/TM1CAP
Capture control circuit
TM1CH Reload overflow TM1INT
TM1CK
TM1DL
TM1DH
PB.1/TM1OVF
TM1CAP
RESETS
Figure Timer Configuration
Data TBCCLK HSCLK PB.2/T02CLK TM2CK Control circuit TM2CL TM2CH Reload 437C
Frequency measurement control circuit
overflow TM2INT
TM2CK TM2DH RESETS TM2OVF
TM2DL
Figure Timer Configuration
Data TBCCLK HSCLK PB.3/T13CK overflow Control circuit TM3CK TM3CL TM3CH Reload TM3DL TM3DH RESETS TM3OVF TM3CK TM3INT
Figure Timer Configuration
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ML63187/189B User's Manual Chapter Timers (TIMER) Timer Registers following four registers used timer control. Timer data registers (TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL, TM3DH) Timer counter registers (TM0CL, TM0CH, TM1CL, TM1CH, TM2CL, TM2CH, TM3CL, TM3CH) Timer control registers (TM0CON0, TM0CON1, TM1CON0, TM1CON1, TM2CON0, TM2CON1, TM3CON0, TM3CON1) Timer status registers (TM0STAT, TM1STAT, TM2STAT, TM3STAT) Each register described below. Timer data registers (TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL, TM3DH) During auto-reload mode, timer data registers store reload values. During capture mode, timer data registers store capture data. Writing timer data register causes contents timer counter register transferred timer data register. system reset, valid bits cleared "0". Note regarding register values: Writing timer counter register causes same value also written timer data register. However, when writing timer data register, same value written timer counter register.
Timer Registers
TM0DL (Timer lower) (068H) (R/W) T0D3 T0D2 T0D1 T0D0
TM0DH (Timer upper) (069H) (R/W) T0D7
T0D6
T0D5
T0D4
Timer Registers
TM1DL (Timer lower) (06AH) (R/W) T1D3 T1D2 T1D1 T1D0
TM1DH (Timer upper) (06BH) (R/W) T1D7
T1D6
T1D5
T1D4
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ML63187/189B User's Manual Chapter Timers (TIMER) Timer Registers
TM2DL (Timer lower) (076H) (R/W) T2D3 T2D2 T2D1 T2D0
TM2DH (Timer upper) (077H) (R/W) T2D7
T2D6
T2D5
T2D4
Timer Registers
TM3DL (Timer lower) (078H) (R/W) T3D3 T3D2 T3D1 T3D0
TM3DH (Timer upper) (079H) (R/W) T3D7
T3D6
T3D5
T3D4
Timer counter registers (TM0CL, TM0CH, TM1CL, TM1CH, TM2CL, TM2CH, TM3CL, TM3CH) 8-bit binary counter operation system reset, valid bits cleared "0". Note regarding register values: Writing timer counter register causes same value also written timer data register. However, when writing timer data register, same value written timer counter register.
Timer Registers
TM0CL (Timer lower) (06CH) (R/W) T0C3 T0C2 T0C1 T0C0
TM0CH (Timer upper) (06DH) (R/W) T0C7
T0C6
T0C5
T0C4
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ML63187/189B User's Manual Chapter Timers (TIMER) Timer Registers
TM1CL (Timer lower) (06EH) (R/W) T1C3 T1C2 T1C1 T1C0
TM1CH (Timer upper) (06FH) (R/W) T1C7
T1C6
T1C5
T1C4
Timer Registers
TM2CL (Timer lower) (07AH) (R/W) T2C3 T2C2 T2C1 T2C0
TM2CH (Timer upper) (07BH) (R/W) T2C7 T2C6 T2C5 T2C4
Timer Registers
TM3CL (Timer lower) (07CH) (R/W) T3C3 T3C2 T3C1 T3C0
TM3CH (Timer upper) (07DH) (R/W) T3C7
T3C6
T3C5
T3C4
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ML63187/189B User's Manual Chapter Timers (TIMER) Timer control registers (TM0CON0, TM0CON1, TM1CON0, TM1CON1, TM2CON0, TM2CON1, TM3CON0, TM3CON1) Timer control registers select operation mode clock each timer. system reset, valid bits cleared "0". Note regarding register values: Writing timer counter register causes same value also written timer data register. However, when writing timer data register, same value written timer counter register.
Timer Registers timer combination 16-bit timer, timer control registers TM1CON0 TM1CON1.
TM0CON0 (070H) (R/W) Timer mode select FMEAS0 TM0ECAP TM0RUN
Auto-reload mode stop (initial value) Auto-reload mode operation Capture mode stop Capture mode operation Frequency measurement mode operation used used used
FMEAS0, TM0ECAP, TM0RUN These bits select timer operation mode. timer operation mode selected auto-reload mode, capture mode, frequency measurement mode.
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ML63187/189B User's Manual Chapter Timers (TIMER)
TM0CON1 (071H) (R/W)
TM0CL1
TM0CL0
Timer clock select TBCCLK (initial value) HSCLK (high-speed clock) External clock used
TM0CL1, TM0CL0 These bits select timer clock. timer clock selected TBCCLK (low-speed clock), HSCLK (highspeed clock), external clock (T02CK: secondary function PB.2).
Note:
HSCLK used clock, after ENOSC (bit FCON) "1", wait following time interval before starting timer operation. Wait least when using ceramic oscillation. Wait least when using oscillation.
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ML63187/189B User's Manual Chapter Timers (TIMER) Timer Registers
TM1CON0 (072H) (R/W) TM1ECAP TM1RUN
Timer mode select Auto-reload mode stop 16-bit timer mode (initial value) Auto-reload mode operation Capture mode stop Capture mode operation
TM1ECAP, TM1RUN These bits select timer operation mode. timer operation mode selected auto-reload mode, capture mode, 16-bit timer mode.
TM1CON1 (073H) (R/W) TM1CL1 TM1CL0
Timer clock select TBCCLK (initial value) HSCLK External clock Timer overflow (16-bit timer mode)
TM1CL1, TM1CL0 These bits select timer clock. timer clock selected TBCCLK (low-speed clock), HSCLK (highspeed clock), external clock (T13CK: secondary function PB.2), timer overflow flag. When using 16-bit timer, select timer overflow clock.
Note:
HSCLK used clock, after ENOSC (bit FCON) "1", wait following time interval before starting timer operation. Wait least when using ceramic oscillation. Wait least when using oscillation.
M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) Timer Registers timer combination 16-bit timer, timer control registers TM3CON0 TM3CON1.
TM2CON0 (07EH) (R/W) FMEAS2 TM2RUN
Timer mode select Auto-reload mode stop (initial value) Auto-reload mode operation Frequency measurement mode operation used
FMEAS2, TM2RUN These bits select timer operation mode. timer operation mode selected auto-reload mode frequency measurement mode.
TM2CON1 (07FH) (R/W) TM2CL1 TM2CL0
Timer clock select TBCCLK (initial value) HSCLK External clock used
TM2CL1, TM2CL0 These bits select timer clock. timer clock selected TBCCLK (low-speed clock), HSCLK (highspeed clock), external clock (T02CK: secondary function PB.2).
Note:
HSCLK used clock, after ENOSC (bit FCON) "1", wait following time interval before starting timer operation. Wait least when using ceramic oscillation. Wait least when using oscillation.
M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) Timer Registers
TM3CON0 (080H) (R/W) TM3RUN
Timer mode select Auto-reload mode stop 16-bit timer mode (initial value) Auto-reload mode operation
TM3RUN This selects timer operation mode. timer operation mode selected auto-reload mode 16-bit timer mode.
TM3CON1 (081H) (R/W) TM3CL1 TM3CL0
Timer clock select TBCCLK (initial value) HSCLK External clock Timer overflow (16-bit timer mode)
TM3CL1, TM3CL0 These bits select timer clock. timer clock selected TBCCLK (low-speed clock), HSCLK (highspeed clock), external clock (T13CK: secondary function PB.3), timer overflow flag. When using 16-bit timer, select timer overflow clock.
Note:
HSCLK used clock, after ENOSC (bit FCON) "1", wait following time interval before starting timer operation. Wait least when using ceramic oscillation. Wait least when using oscillation.
8-10 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) Timer status registers (TM0STAT, TM1STAT, TM2STAT, TM3STAT) Timer status registers read status each timer. system reset, valid bits cleared "0".
Timer Registers
TM0STAT (074H) TM0CAP TM0OVF
Timer capture flag capture data (initial value) capture data Timer overflow flag Initial value Toggles between each time timer counter register overflows.
TM0CAP (TiMer0 CAPture) This indicates whether capture data present. When TM0CAP "0": value indicates that there been capture data since system reset since last time TM0CAP read. When TM0CAP "1": value indicates that there capture data since system reset since last time TM0CAP read. Additional captures disabled. system reset, TM0CAP cleared "0". capture mode, level capture input (PB.0/TM0CAP) changes capture generated, TM0CAP automatically "1". TM0STAT read, TM0CAP automatically cleared "0". TM0OVF (TiMer0 OVerFlow) This indicates that timer counter register overflowed. This toggles between whenever overflow occurs. system reset, TM0OVF cleared "0". Timer Registers
TM1STAT (075H) TM1CAP TM1OVF
Timer capture flag capture data (initial value) capture data Timer overflow flag Initial value Toggles between each time timer counter register overflows.
8-11 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) TM1CAP (TiMer1 CAPture) This indicates whether capture data present. When TM1CAP "0": value indicates that there been capture data since system reset since last time TM1CAP read. When TM1CAP "1": value indicates that there capture data since system reset since last time TM0CAP read. Additional captures disabled. system reset, TM1CAP cleared "0". capture mode, level capture input (PB.1/TM1CAP) changes capture generated, TM1CAP automatically "1". TM1STAT read, TM1CAP automatically cleared "0". TM1OVF (TiMer1 OVerFlow) This indicates that timer counter register overflowed. This toggles between whenever overflow occurs. system reset, TM1OVF cleared "0". Timer Register
TM2STAT (082H) TM2OVF
Timer overflow flag Initial value Toggles between each time timer counter register overflows.
TM2OVF (TiMer2 OVerFlow) This indicates that timer counter register overflowed. This toggles between whenever overflow occurs. system reset, TM2OVF cleared "0". Timer Register
TM3STAT (083H) TM3OVF
Timer overflow flag Initial value Toggles between each time timer counter register overflows.
TM3OVF (TiMer3 OVerFlow) This indicates that timer counter register overflowed. This toggles between whenever overflow occurs. system reset, TM3OVF cleared "0". 8-12 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) [Supplement] List Timer Registers
Timer Registers
Name Timer data register Timer data register Timer counter register Timer counter register Timer control register Timer control register Timer status register Symbol TM0DL TM0DH TM0CL TM0CH TM0CON0 TM0CON1 TM0STAT Address 068H 069H 06CH 06DH 070H 071H 074H Initial value
Timer Registers
Name Timer data register Timer data register Timer counter register Timer counter register Timer control register Timer control register Timer status register Symbol TM1DL TM1DH TM1CL TM1CH TM1CON0 TM1CON1 TM1STAT Address 06AH 06BH 06EH 06FH 072H 073H 075H Initial value
Timer Registers
Name Timer data register Timer data register Timer counter register Timer counter register Timer control register Timer control register Timer status register Symbol TM2DL TM2DH TM2CL TM2CH TM2CON0 TM2CON1 TM2STAT Address 076H 077H 07AH 07BH 07EH 07FH 082H Initial value
Timer Registers
Name Timer data register Timer data register Timer counter register Timer counter register Timer control register Timer control register Timer status register Symbol TM3DL TM3DH TM3CL TM3CH TM3CON0 TM3CON1 TM3STAT Address 078H 079H 07CH 07DH 080H 081H 083H Initial value
8-13 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) Timer Operation 8.4.1 Timer Clock timer clock selected TBCCLK (low-speed clock: 32.768 kHz), HSCLK (highspeed clock), external clock. using timer timer overflow signals clocks timer timer respectively, timers used pairs 16-bit timers. high-speed clock (HSCLK) used, after setting (ENOSC) frequency control register (FCON), wait least ceramic oscillation mode oscillation mode before operating timer. external clock input port assigned secondary function port. case timers PB.2/T02CK used input external clock. case timers PB.3/T13CK used input external clock. Since external clock sampled system clock (CLK), high- low-levels external clock should longer than cycle system clock (CLK).
8.4.2 Timer Data Registers TM0DL, TM0DH, TM1DL, TM1DH, TM2DL, TM2DH, TM3DL TM3DH 4-bit registers. auto-reload mode, timer data registers save values that reloaded into timer counter registers when timer counter registers overflow. capture mode, timer data registers save value timer counter registers when capture signal input. Each timer data register read/written software. Writing timer data registers does change contents timer counter registers.
8.4.3 Timer Counter Registers TM0CL TM0CH, TM1CL TM1CH, TM2CL TM2CH, TM3CL TM3CH 8-bit binary counters that incremented falling edge timer clock. Each timer counter register read/written software. However, clock timer clock different, values that read written during count operation cannot guaranteed. external clock used timer clock, reading/writing always possible. When value written timer counter register, same value also written corresponding timer data register.
8-14 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) 8.4.4 Timer Interrupt Requests Overflow Flags Timers generate timer interrupt requests when timer counter register overflows. overflow flag toggles between each overflow. output overflow flag timers output secondary port functions PB.0/TM0OVF PB.1/TM1OVF pins. Figure indicates operation timing timer counter register overflow. Table lists timer interrupts.
Timer clock TM0CH, TM0CL TM0DH, TM0DL TM0INT TM0OVF
Figure Timer Counter Register Overflow Timing (for Timer
Table List Timer Interrupts
Interrupt factor Timer interrupt Timer interrupt Timer interrupt Timer interrupt Symbol TM0INT TM1INT TM2INT TM3INT flag (IRQ2) QTM0 QTM1 QTM2 QTM3 flag (IE2) ETM0 ETM1 ETM2 ETM3 Interrupt vector address 0020H 0022H 0024H 0026H
When master interrupt enable flag (MIE) with interrupt enable flags (ETM0- "1", timer overflow occurs, interrupt request generated.
8-15 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) 8.4.5 Auto-Reload Mode Operation Timers used auto-reload mode timers. setup method follows. Timer FMEAS0 (bit TM0CON0) "0", TM0ECAP (bit TM0CON0) "0". Timer TM1ECAP (bit TM1CON0) "0". Timer FMEAS2 (bit TM2CON0) "0". Timer setup needed.
auto-reload mode, each time timer counter register overflows, timer data register value reloaded into timer counter register, counting begins from value. Setting bits (TM0RUN, TM1RUN, TM2RUN, TM3RUN) each timer control register will restart count, resetting stops count. 16-bit timer mode timers TM1RUN disabled, start/stop controlled with TM0RUN bit. 16-bit timer mode timers TM3RUN disabled, start/stop controlled with TM2RUN bit.
Figure shows auto-reload mode timing pulse generation when timers used 16-bit timer.
FFFF BFFF 534F 0000 TM1DH, TM1DL TM0DH ,TM0DL TM0RUN TM1INT
TM1CH, TM1CL TM0CH, TM0CL
534F
BFFFH
534F
BFFFH
TM1OVF (PB.1 output)
Figure Auto-Reload Mode Timing
8-16 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) operation procedures follows. PB.1 output mode (TM1OVF) secondary function. Write 534FH timer data timer counter registers. TM1DH TM1CH (bits 15-12) TM1DL TM1CL (bits 11-8) TM0DH TM0CH (bits 7-4) TM0DL TM0CL (bits 3-0) TM0CON TM1CON auto-reload mode TM0RUN "1", timer counter register will start count from 534FH. Before timer counter register overflows, write next reload value BFFFH timer data register. When timer counter register overflows, BFFFH timer counter register, timer interrupt TM1INT generated timer overflow flag TM1OVF toggles. timer counter register continues count from BFFFH. Before timer counter register overflows, write next reload value 534FH timer data register. When timer counter register overflows, 534FH timer counter register, timer interrupt TM1INT generated timer overflow flag TM1OVF toggles. timer counter register resumes counting from address 534FH. Repeat steps through This allows user-defined pulse output from PB.1/TM1OVF. Halt count resetting TM0RUN "0". Figure shows TM0RUN count start/halt timing.
Selected clock TM0RUN
Timer clock Timer counter register
Figure TM0RUN Count Start/Halt Timing
When TM0RUN "1", timer counter starts count from second falling edge selected clock. When TM0RUN reset "0", counter stops counting falling edge selected clock which appears immediately after TM0RUN falling edge.
8-17 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) 8.4.6 Capture Mode Operation Timer timer used capture mode timers. capture operation, change capture input (PB.0/TM0CAP, PB.1/TM1CAP) level during operation timer counter register triggers loading value timer counter register into timer data register. Methods capture mode each timer listed below. Timer TM0ECAP (bit TM0CON0) "1", FMEAS0 (bit TM0CON0) "0". Timer TM1ECAP (bit TM1CON0) "1".
capture mode, reloading timer data register data into timer counter register inhibited, when timer counter register overflows, counting restarted from 00H.
When capture occurs, capture flags (TM0CAP, TM1CAP) timer status registers (TM0STAT, TM1STAT) "1". Additional captures disabled while capture flags "1". capture flags assigned timer status registers, automatically cleared when timer status registers read. both TM1CL1 TM1CL0 bits timer control register (TM1CON1) timer overflow selected clock, 16-bit capture mode will set. this case, PB.0/TM0CAP capture trigger input.
Figure shows timer capture mode timing pulse width measurement.
TM0CH, TM0CL TM0DH, TM0DL TM0RUN TM0ECAP TM0INT PB.0/TM0CAP input TM0CAP XI0INT
Figure Capture Mode Timing
8-18 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) operation procedure listed below.
PB.0/TM0CAP input mode, enable XI0INT TM0INT. Clear bits timer counter registers timer data registers zero. TM0CON0 capture mode, TM0RUN begin upward counting. PB.0/TM0CAP input changes, TM0CH/TM0CL value captured TM0DH/TM0DL TM0CAP (first capture). detects this through XI0INT reads values TM0DH/TM0DL. After TM0DH/TM0DL read complete, TM0CAP cleared wait next capture. PB.0/TM0CAP input changes, repeat operations (second capture). high-level pulse width PB.0 input determined follows. (F0H 50H) tCLK tCLK: TMCLK cycle
TM0INT generated when timer counter register overflows. When overflow occurs, timer counter register changes from continues upward counting. PB.0/TM0CAP input changes, repeat operations (third capture). Because counter overflows once during interval between second capture third capture, low-level pulse width PB.0 input determined follows. (60H 100H) tCLK While TM0CAP "1", there capture even when PB.0/TM0CAP changes.
Figure shows capture timing Figure 8-10 shows capture signal (CAPT) generator circuit.
Timer clock PB.0/TM0CAP input TM0CH, TM0CL TM0DH, TM0DL Capture signal (CAPT) TM0CAP TM0STAT READ
Figure Capture Timing
8-19 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER)
CAPT PB.0/TM0CAP input
Timer clock TM0ECAP TM0CAP
Figure 8-10 Capture Signal (CAPT) Generator Circuit
Note:
maximum delay from PB.0/TM0CAP input level change until capture cycle timer clock.
8-20 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) 8.4.7 Frequency Measurement Mode Operation frequency measurement mode used measure frequency oscillator clock, which wide product variation. Timers timers used frequency measurement mode. These timers follows frequency measurement mode: Timer Timer Timer Timer FMEAS0 (bit TM0CON0) "1", TM0ECAP (bit TM0CON0) TM0RUN (bit TM0CON0) "0". TM1ECAP (bit TM1CON0) TM1RUN (bit TM1CON0) "0". FMEAS2 (bit TM2CON0) "1", TM2RUN (bit TM2CON0) "0". TM3RUN (bit TM3CON0) "0".
Figure 8-11 indicates frequency measurement mode timing when timers used 16-bit timer.
FFFF TM3CH TM3CL TM2CH TM2CL 0000 TM3DH, TM3DL TM2DH, TM2DL 437C FMEAS2 437/32768
Figure 8-11 Frequency Measurement Mode Timing operation sequence Figure 8-11 follows. Timer control registers (TM3CON0, TM3CON1) 16-bit timer mode, timer counter timer data register cleared "0". Enable high-speed clock frequency control register (FCON) timer clock HSCLK. Wait more ceramic oscillation mode more oscillation mode after starting high-speed clock FMEAS2 enter frequency measurement mode. When FMEAS2 "1", counter starts falling edge. When 437C signal "1", FMEAS2 reset "0", counter stops falling edge next clock. 437C signal pulse signal which rises 437/ 32768 seconds after falling edge. Timer counter register value read.
8-21 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) Assuming that ceramic oscillation clock exactly MHz, value read from timer counter register
2000000 437/32768 26672 (decimal) 6380 (hexadecimal) 0110 1000 0011 0000 (binary) (truncated)
Because 437/32768 seconds equivalent clocks 9600 (more precisely, 9598 Hz), division count provides frequency ratio (N2) between 9600 Because that determined merely truncating righthand seven digits (binary), yielding.
26672/128 011010000 (binary) (hexadecimal) (decimal)
This indicates that 9600 about times cycle MHz, which means that timer data register should FF30H that counter overflows every counts clock auto-reload mode. result, overflow produces TM3INT cycle tTM3INT tTM3INT 1/2000000 0.104 (9615 same way, assuming that oscillation clock manufacturing variation,
600000 437/32768 8001 (decimal) 1F41 (hexadecimal) 0001 1111 0100 0001 (binary) (truncated)
Truncating righthand seven digits (binary),
8001/128 000111110 (binary) (hexadecimal) (decimal)
timer data register FFC2H that counter overflows every counts clock auto-reload mode. result, overflow produces TM3INT cycle tTM3INT
tTM3INT 1/600000 0.10333 (9677
this frequency measurement mode applied generate TM3INT signals with precision cycles.
8-22 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER) Figure 8-12 illustrates operation timer interrupt oscillator clock frequency kHz.
FFFF FFC2 TM3CH TM3CL TM2CH TM2CL
0000 TM3DH, TM3DL TM2DH, TM2DL TM3INT (9677 FFC2
0.10333
Figure 8-12 Timer Interrupt (TM3INT) Generation
8-23 M187 M189B
ML63187/189B User's Manual Chapter Timers (TIMER)
8-24 M187 M189B
Chapter
Timer Counter (100HzTC)
M187
M189B
ML63187/189B User's Manual Chapter Timer Counter (100HzTC)
Chapter Timer Counter (100HzTC)
Overview timer counter circuit that divides TBC6 output (512 time base counter generate interrupt. timer consists 5/6-base counter decimal counters.
Timer Counter Configuration Figure indicates configuration timer counter.
T10HzINT T100CR ECNT 5/6-base counter decimal counter T10CR decimal counter
T10CR WRITE T100CR WRITE
Data
4-bit latch T10CR READ
T100CR READ
Figure Timer Counter Configuration
M187 M189B
ML63187/189B User's Manual Chapter Timer Counter (100HzTC) Timer Counter Registers timer counter control register (T100CON) This 4-bit special function register (SFR) controlling timer counter.
T100CON (066H) (R/W) Count start/stop select Count stop (initial value) Count start ECNT
ECNT This controls count start/stop timer counter internal counter. Count starts when "1". system reset value reset counting stopped.
counter register (T100CR) This 4-bit special function register (SFR) read counter timer counter. content T100CR latched 4-bit latch T10CR read operation, value T100CR must always read after reading T10CR. When data written T100CR, both T100CR T10CR reset "0".
T100CR (064H) (R/W) 100C3
100C2
100C1
100C0
counter register (T10CR) 4-bit special function register (SFR) read counter timer counter. When data written T10CR, both T100CR T10CR reset "0".
T10CR (065H) (R/W) 10C3 10C2 10C1 10C0
M187 M189B
ML63187/189B User's Manual Chapter Timer Counter (100HzTC) Timer Counter Operation timer counter begins counting when (ECNT) timer counter control register (T100CON) "1". output time base counter divided into 5/6-base counter. signal input counter (T100CR) carry output that counter input counter (T10CR). 10HzINT signal, which carry output T100CR counter also generates interrupt request, setting (Q10Hz) inter
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