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Diversity Receiver Chipset CLC5526, CLC5956, CLC5902 General Desc
Top Searches for this datasheetDiversity Receiver Chipset CLC5526, CLC5956, CLC5902 Diversity Receiver Chipset CLC5526, CLC5956, CLC5902 General Description Diversity Receiver Chipset (DRCS) five-chip narrowband receiver solution requiring less than square inches board area. five chips include CLC5526 Digitally-Controlled Variable Gain Amplifiers (DVGAs), CLC5956 12-bit 65MSPS Analog-to-Digital Converters (ADCs), CLC5902 Dual Digital Tuner/AGC. inputs 300MHz produce digital quadrature symbols baseband. Either channel diversity independent channel operation supported DRCS. This Diversity Receiver Chipset been designed support software configurable narrowband receivers. Direct IF-sampling removes need second mixer, associated channel filters. subsequent tuning channel filtering performed digitally CLC5902. Tuning accomplished quadrature mixing digital input signal with programmable digital signal. quadrature mixer outputs then channel-filtered sets programmable filters. ADC's 62dB SINAD Nyquist bandwidth, 150MHz input) enhanced DVGA digital processing provide 120dB dynamic range 216kHz bandwidth. DVGA compresses input dynamic range prior under control processor. Gain adjustment from -12dB +30dB allows 42dB compression. compressed signal optionally expanded digital domain provide extended linear output range. System noise sets realizable dynamic range 120dBFS GSM. Features 52MSPS Operation Independent Channels Wide Dynamic Range: >120dB User Programmable Direct Sampling 300MHz Channel Filters include Fourth Order followed 21-tap 63-tap Symmetric FIRs Flexible output formats include Floating Point Fixed Point Serial Parallel output ports JTAG Boundary Scan Shutdown/Stand-by Capability Meets GSM, EDGE, PCS, DCS, AMPS, DAMPS, requirements Small Footprint Cost DVGA Dual Digital Tuner/AGC DVGA SerialOutA/B SerialOutB RDY/ACK ParallelOut POutEnable ParallelSelect CLC5526 ©1999 National Semiconductor Corporation CLC5956 CLC5902 Rev. 1999 Operation Three modes operation provided including Inhibit, Free Run, Burst. Burst mode allows pre-determined time before going into hold condition. This mode could used TDMA system track power ramp then hold peak value. operation based envelope detection absolute value circuit followed digital lowpass filter. filtered signal applied programmable look-up table allow complete flexibility setting threshold (attack point) deadband (hysteresis). output integrated resulting error signal drives DVGAs. Integrator gain programmable that loop time constant adjusted. integrator output read written allowing DVGAs initialized specific value TDMA systems. division sample rate (decimation ratio). system esired output symbo rate 270.83kHz. channel filter coefficients should bandwidth approximately times symbol rate 216kHz. this case, noise will reduced factor 52MHz/216kHz 23.7dB. greater ratio sample rate channel filter bandwidth better system noise performance. CLC5902 accepts inputs 14-bits. operation generates 3-bit exponent which scale 14-bit input words into 21-bit internal word width. output final filter bits either bits this data selected output. output words available standard serial formats 16-bit parallel words. DVGAs CLC5902 configured provide compressed dynamic range full linear dynamic range more than 120dBFS. input signal increases, DVGA will attenuate input signal steps. output scaled steps maintain linear input output relationship. representative example expanded dynamic range Diversity Receiver Chipset shown figure below. 42dB gain range DVGA clearly seen difference between output CLC5902 output. zero SINAD point seen where -120dBFS. Dynamic Range Diversity Receiver Chipset dynamic range determined following component contributions. Component CLC5526 DVGA CLC5526 DVGA CLC5956 CLC5902 Processing Gain Total Input Dynamic Range (GSM) 42dB Gain Range -7.2dB Noise Contribution 62dBFS SINAD 150MHz, 52MHz) 23.7dB (10*log(52MHz/216kHz)) 120dBFS System operation CLC5956 requires low-jitter PECL clock which must converted clock CLC5902. This clock divided CLC5902 generate desired output sample rate channel filter bandwidth. System power requirements include 1.85W 0.75W +3.3V. Shutdown/stand-by modes available DVGAs ADCs. CLC5902 power requirements reduced when input clock stopped. Processing gain comes from reduction output bandwidth provided channel filters. channel filter bandwidth output symbol rate controlled DRCS Measured SINAD Output SINAD (dB) 26MHz Output Output (dBFS) SINAD -120 -100 -120 -100 (dBFS) Rev. 1999 ©1999 National Semiconductor Corporation Diversity Receiver Chipset Measured Data: DRCS Eval. Board Large Signal Response 52MHz, Decimation 155.85MHz +5dBm, DVGA Gain -12dB Output -16.5dBFS, SINAD 59.5dB Input (dBm) -100 -120 -140 -160 0.0E+00 1.0E+04 2.0E+04 3.0E+04 4.0E+04 5.0E+04 6.0E+04 7.0E+04 8.0E+04 9.0E+04 1.0E+05 1.1E+05 1.2E+05 1.3E+05 1.3E+05 1.3E+05 Frequency DRCS Eval. Board Small Signal Response Fs=52MHz, Decimation=192 Fin=155.85MHz -95dBm, DVGA Gain 30dB Output -116.2dBFS, SINAD=6.9dB Input (dBm) -100 -120 -140 -160 0.0E+00 1.0E+04 2.0E+04 3.0E+04 4.0E+04 5.0E+04 6.0E+04 7.0E+04 8.0E+04 9.0E+04 1.0E+05 1.1E+05 1.2E+05 Frequency DRCS Eval. Board Blocker Response 52MHz, Decimation 155.85MHz -77dBm, DVGA Gain 24dB Blocker 153.0MHz -29dBm, DVGA Gain 24dB Output -98.9dBFS, SINAD 17.1dB Input (dBm) -100 -120 -140 -160 0.0E+00 1.0E+04 2.0E+04 3.0E+04 4.0E+04 5.0E+04 6.0E+04 7.0E+04 8.0E+04 9.0E+04 1.0E+05 1.1E+05 1.2E+05 Frequency ©1999 National Semiconductor Corporation Rev. 1999 1.4E+05 1.4E+05 1.4E+05 Dynamic Performance (GSM Burst): 30µsec 70dB power ramp output, 52MSPS, 150MHz operation during burst does impair equalizer/demodulator operation. Rising Ramp Falling Ramp 0.75 0.375 0.25 Mixer Output 0.25 Mixer Output 1.0E+00 5.0E+02 1.0E+03 1.5E+03 2.0E+03 2.5E+03 3.0E+03 3.5E+03 4.0E+03 4.5E+03 5.0E+03 5.5E+03 6.0E+03 0.125 -0.25 -0.125 -0.5 -0.25 -0.75 -0.375 -0.5 1.0E+00 5.0E+02 1.0E+03 1.5E+03 2.0E+03 2.5E+03 3.0E+03 3.5E+03 4.0E+03 4.5E+03 5.0E+03 5.5E+03 6.0E+03 Sample Sample Diversity Receiver Chipset Constellation: Code constellation; Vin(dBFS)= -20.1, BER= 30-Oct-1998 Code constellation; Vin(dBFS)= -100, BER= 1.4057e-007 30-Oct-1998 -0.8 -0.6 -0.4 -0.2 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -0.8 -0.6 -0.4 -0.2 Rev. 1999 ©1999 National Semiconductor Corporation Diversity Receiver Chipset CLC5526, CLC5956, CLC5902 Customer Design Applications Support National Semiconductor committed design excellence. sales, literature technical support, call National Semiconductor Customer Response Group 1-800-272-9959 1-800-737-7018. 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National Semiconductor® trademarks National Semiconductor Corporation. other trademarks property their respective companies. http://www.national.com Rev. 1999 Other recent searchesVLMB40L1M2-34 - VLMB40L1M2-34 VLMB40L1M2-34 Datasheet TSF0455-02 - TSF0455-02 TSF0455-02 Datasheet TA8182FN - TA8182FN TA8182FN Datasheet NJU26220 - NJU26220 NJU26220 Datasheet NJU26220R - NJU26220R NJU26220R Datasheet NJU26220TVPCAV - NJU26220TVPCAV NJU26220TVPCAV Datasheet NJU26220FN2 - NJU26220FN2 NJU26220FN2 Datasheet LM3622 - LM3622 LM3622 Datasheet HER1601G - HER1601G HER1601G Datasheet HER1608G - HER1608G HER1608G Datasheet ECS-300C - ECS-300C ECS-300C Datasheet ADS8345 - ADS8345 ADS8345 Datasheet
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