Revision 1/05/2000 Copyright 1996, 1997, 1998, 1999, 2000 Nationa
|
|
|
Top Searches for this datasheet
Design Rules Physical Layout Temperature Co-Fired Ceramic Modules
Revision 1/05/2000
Copyright 1996, 1997, 1998, 1999, 2000 National Semiconductor Corporation Unpublished Work Rights Reserved. part this work reproduced utilized form means electronic mechanical, including photocopying, recording information storage retrieval system, without prior permission writing from: National Semiconductor Corporation Studebaker Irvine, 92618
Version 01/05/2000 Page
CONTENTS
INTRODUCTION 1.1. Scope 1.2. Design Basis. 1.3. Materials System 1.4. UNITS 1.4.1. Unit Conversion table Part Size Tolerances. 2.1. Part Size. 2.1.1. Number Table 2.2. Part Size Tolerance (outside dimensional tolerances). 2.3. Fired Part Thickness. 2.3.1. Part Thickness Table. 2.4. Conductor Pattern Feature Feature Accuracy 2.5. Conductor Pattern Feature Part Edge Accuracy. Part Pattern Spacing Tolerance Summary Figure 2.6. Flatness Tolerance VIAS 3.1. Size. 3.2. Catch Pads. 3.2.1. Catch Sizes Mils. 3.3. Spacing 3.4. Part Edge Spacing. 3.4.1. Part Edge Figure 3.4.2. Edge Spacig Table 3.5. Layer Layer Connections 3.5.1. Exposed Vias 3.5.1.1. Typical stack connecting buried vias. 3.5.2. Buried Vias. 3.5.2.1. Size Stagger CONDUCTORS 4.1. Line Space Width 4.1.1. Allowable Line Space 4.2. Standard Surface Conductors. 4.3. Close Edge Technology (CTTE) 4.4. Buried Line edge. 4.5. Direction 4.6. Line Line Connections 4.7. Line Edge Spacing. 4.7.1. Line Edge Spacing Table. 4.7.2. Square Corner Curved Corner. 4.7.3. styles mitered corners. 4.8. FineLine Process. 4.8.1. Continuity Narrow Lines FineLine Higher Yield Absolute Resistance Lines FineLine Always Lower. Conductors Blockier than Thick Film Interface Vias Well 4.8.4. Spaces Between Conductors Free Silver, X-ray 4.8.5. Clean Sharp Lines. 4.8.6. Interdigitated Caps Show Great Improvement 4.9. Line Construction.
Version 01/05/2000 Page
4.10. Line Connections. 4.11. Conductor Distribution Issues. 4.12. Axis Distribution Issues 4.13. Large Area Planes. 4.13.1. Construction 4.13.2. Pass Through 4.13.3. Conductor Traces Grid Plane Layers CERAMIC MATERIAL PROPERTIES. 5.1. Ceramic Materials. CONDUCTOR PROPERTIES. 6.1. Conductor Properties Tape System 6.2. Conductor Properties Tape System 6.3. Mixing Gold Silver 6.4. Thickness Profile 6.4.1. 6142 Cross Section micron thickness. 6.4.2. 6145 Cross Section micron thickness. 6.4.3. 6146N connecting 6141 6142 ceramic thickness. LAYOUT CONSIDERATIONS ELECTRICAL FEATURES. 7.1. Inductors. 7.1.1. Inductor Shapes 7.2. Capacitors 7.2.1. Maximum Percent Coverage. 7.2.2. Best practice capacitor plate design STYLES. 8.1. Clip Leads 8.1.1. Clip Lead Illistration. 8.1.2. Current part (lid removed) showing clip lead. 8.2. Ball Grid Array (BGA) 8.2.1. Standard 8.2.2. Typical Layout 8.2.3. Schematic Layout. 8.2.4. Construction Rules 8.2.5. Example Part Cross Section ball 8.2.6. Example Part ball 8.3. Castellation. 8.3.1. Typical Layout 8.3.2. Cross Section. 8.3.3. Example Parts. 8.4. Others 8.5. Recommended Configurations. FILM RESISTORS. 9.1. Introduction. 9.2. Surface Resistors 9.2.1. Available Materials-Cofired Surface Resister. 9.3. Buried Resistors 9.3.1. Available Materials Buried Resistors. 9.4. Resistor Layout Characteristics Termination Table 9.5. Typical Layout Termination Table. 9.6. Typical Design Curves. 9.6.1. NSC-2021 Development Curve 9.6.2. NSC-2031 Development Curve 9.6.3. NSC-2041 Development Curve 9.6.4. NSC-2051 Development Curve 9.7. Example Part with Resistors Capacitors 10.1. K=7.8 Tape Sheet Capacitors.
Version 01/05/2000 Page
10.2. Printed Patch Capacitors 10.2.1. Application 10.2.2. Usage limits 10.2.3. Electrical Performance: 10.2.4. Dissipation Factor Temperature 10.2.5. Dissipation Factor Frequency 10.2.6. TCC. Wire Bond Pads. 11.1. Wire Bond Layout. 11.2. Layout: 11.3. Actual Wire Bonded Pattern 11.4. Typical Process Parameters 1419 Wire Bonder. 11.5. Typical Pull Data FACTORY INTERFACE 12.1. Design Basis Transfer. 12.2. Data Format 12.3. Design Transfer Check List. 12.4. Sample Layer Plot 12.5. Typical Flow Chart. OTHER CAPABILITIES 13.1. Cavities 13.2. Multilevel Bond Shelves 13.3. Brazing. 13.4. Grinding Revision Record
Version 01/05/2000 Page
INTRODUCTION
This document intended provide you, customer, information necessary have first pass success design manufacture electronic components Temperature Co-fired Ceramic (LTCC). Every effort been made make this document complete possible. However, errors omissions will occur, every application unique. something unclear missing, please call ask, most important feedback yours. following some basic definitions designed provide common basis discussion.
1.1.
Scope
This document provides Design Rules Physical Layout Temperature Co-Fired Ceramic Modules covering physical constraints part design properties materials used.
1.2.
Design Basis
designs made fired size, basis. Expansion arraying required manufacturing performed after design completion part conversion manufacturing process (a.k.a. tape out). values discussed fired values completed part delivered component assembly.
1.3.
Materials System
Present Standard materials used line are: DuPont tape with silver internal conductors. External conductors solderable Silver/Palladium alloy, Wire-Bondable Gold. This tape available four thickness' (see section
incorporation additional material systems continuing project. following dielectrics limited selection conductors available. Ferro A6M; loss microwave tape used premium applications higher frequencies. This tape available four thickness' (see section DuPont 943; loss microwave tape used premium applications higher frequencies, lower loss than other LTCC material. This tape available thickness (see section
Version 01/05/2000 Page
1.4.
UNITS
LTCC uses English Engineering System mechanical measurement dimensioning. Therefore following cross-reference table frequently used values provided based 25.4 millimeters inch. 1.4.1. Unit Conversion table Engineering Common inch mils 0.003" mils 0.0052" mils 0.006" mils 0.007" mils 0.008" mils 0.010"
Metric millimeter ~0.076 ~0.132 ~0.152 ~0.178 ~0.203 0.254
Version 01/05/2000 Page
Part Size Tolerances
2.1.
Part Size
Parts produced sizes mils 5000 mils inches). Near square rectangular shapes preferred dimensional accuracy lowest cost fabrication. Smaller size parts produced stepped repeated arrays inches square. Parts delivered either array format individually buyer's request. Array deliveries laser scored buyer after assembly delivered buyer pre-scored. Least cost unit occurs when material used efficiently. have this occur make part size even division inch array size Examples 2.1.1. Number Table Number Across Down Number Square Irrational Numbers
Part Size 1.000 .8333 .7143* .625 .5555 .500 .4545* .4166 .3846 .3571 .33333
2.2.
Part Size Tolerance (outside dimensional tolerances)
Physical part outside dimensional tolerance function part design generally 0.5% part size less than mils.
Version 01/05/2000 Page
2.3.
Fired Part Thickness
following table summarizes acceptable layer thickness combinations. 2.3.1. Part Thickness Table Table 951AT 951A2 951AX Thickness Minimum Layers /.014" Layers .020" Layers .016" Maximum Layers .180" Layers .180" Layers .180"
2.4.
Conductor Pattern Feature Feature Accuracy
Feature location tolerances within printed pattern, same screen, generally within 0.5% design size less than mils non-cumulative.
2.5.
Conductor Pattern Feature Part Edge Accuracy
dimensional tolerance conductor space green edge part mils. 2.5.1. Part Pattern Spacing Tolerance Summary Figure
mils
+/-0.5%, Less Than mils
+/-0.5%, Less Than mils
2.6.
Flatness Tolerance
less than 0.003 inch/inch less than .003 inch total.
Version 01/05/2000 Page
VIAS
3.1.
Size
Vias right circular cylinders. vias given layer should same size. Different part layers have different size vias.
3.2.
Catch Pads
Catch pads design features required; process will produce them automatically. 3.2.1. Catch Sizes Mils 17.0 17.0 Catch Square
Catch
3.3.
Spacing
Vias same layer must separated diameters center center meet both construction conductor spacing requirements. This spacing would used Isolating fences
Version 01/05/2000 Page
3.4.
Part Edge Spacing
vias must spaced back from part edge shown below. allowable closeness approach depends thickness part listed table below. 3.4.1. Part Edge Figure
Spacing 3.4.2. Edge Spacing Table Layer Count Spacing 951AT Equivalent mils 9-16 mils mils Conductor Spacing Only mils mils mils
3.5.
Layer Layer Connections
Connections between layers structure made means via. 3.5.1. Exposed Vias Exposed connections have their vias stacked vertically another maximum twenty-two (22) layers 951AT. greater length required additional internal vias stair stepped shown sketch following. Note: stacked connection results bump external surface part that reach six-layer stack. stacks intended hermetic best placed where they will solder sealed. Version 01/05/2000 Page
3.5.1.1.
Typical stack connecting buried vias.
Layers maximum
3.5.2. Buried Vias Buried blind vias (those exposed surface) stacked layers 951AT their thickness equivalent) should stair stepped center center shown following sketch: 3.5.2.1. Size Stagger Size 17.0 mils mils mils mils mils Stagger mils mils mils mils mils Stagger
Version 01/05/2000 Page
CONDUCTORS
4.1.
Line Space Width
4.1.1. Allowable Line Space Line Width Space Notes mils mils mils mils Connection requires 12.5 space from adjacent line(s). mils mils Connection requires 10.5 space from adjacent line(s). mils mils Connection requires space from adjacent line(s).
4.2. 4.3.
Standard Surface Conductors Close Edge Technology (CTTE)
standard conductor edges must kept mils more from part edge.
those occasions when placement surface conductor closer edge part than normal required, designer select "Close Edge Technology Option". Using this option surface conductor extend close mils from edge part. (Note: dimensional tolerance considerations will result these lines actually lying from zero mils from edge finished part)
4.4.
Buried Line edge
those occasions when placement buried conductor closer edge part than normal required, designer selects "Close Edge Technology Option place conductor close mils from edge part.
4.5.
Direction
Lines should parallel perpendicular part edges using orthogonal geometry. Angled lines permitted designer obligated ensure that adequate conductor width clearance adjacent conductors will exist.
4.6.
Line Line Connections
Lines line connections also known corners, junction intersecting lines. These made several methods including square, mitered
Line widths below mils done with FineLine process
Version 01/05/2000 Page
curved shown accompanying illustration long minimum line width requirements met.
4.7.
Line Edge Spacing
Internal Conductor should kept mils back from edge part depending part thickness shown following table. 4.7.1. Line Edge Spacing Table Layer Count Conductor Spacing Conductor Spacing 951AT Equivalent Only others mils mils 9-16 mils mils mils mils Exception: single line mils less width, parallel part edge placed mils from edge part mils once inch long conductor material other than 6145 thick print.
4.7.2.
Square Corner
Curved Corner
4.7.3. styles mitered corners Lines intersecting acute angles create self-spacing errors intersection width errors apex, filling inner portion intersection blunting apex shown following sketch prevent this. Version 01/05/2000 Page
4.8.
FineLine Process
FineLine process enables lines spaces narrow mils reliably produced high yield. This technology uses photo sensitive exposure development process that yields line width control mils. This same line width tolerance control available wider lines well. Layers using this technology mixed matched with conventional thick film layers. Coverage limits same other current conductors. This co-fired technology that presently available buried layers surface non-solderable features. It's fine resolution narrow line widths make particularly useful areas Reduced size inductors Precision capacitors Tighter tolerance filters Couplers
Version 01/05/2000 Page
following pictures graphs illustrate some capabilities this process material.
4.8.1. Continuity Narrow Lines FineLine Higher Yield
100% Line Width 2mil Baseline Baseline Silver Silver
Serpentine Properties
4.8.2. Absolute Resistance Lines FineLine Always Lower
Ohms Line Width
Baseline Baseline Silver Silver
Version 01/05/2000 Page
4.8.3. Conductors Blockier than Thick Film Interface Vias Well
4.8.4. Spaces Between Conductors Free Silver, X-ray
Version 01/05/2000 Page
4.8.5. Clean Sharp Lines
4.8.6. Interdigitated Caps Show Great Improvement
Interdigitated Capacitor
4.9.
Line Construction
Lines often made connecting individual segments. cases segments must contact each other, designers encouraged generous overlaps prevent unintended opens. This most common errors found designs; frequently aggravated dimensional round error files translated between formats dimensional systems. (0.002") overlap Version 01/05/2000 Page
recommended absolute minimum. overlap that goes across intersecting line costs nothing easier execute than precisely mating edges.
Full Overlap
Edges Mated
4.10.
Line Connections
Vias connect lines means overlap shown sketch. lines with rounded edges improve inspectability
4.11.
Conductor Distribution Issues
ratio conductor tape area affects part distortion directions. Therefore, best design which conductor distributed evenly across surface individual tape layers.
4.12.
Axis Distribution Issues
Conductor mechanically adds thickness (~0.2 print) part where present. those cases where many conductors stacked above another next areas having conductors, distortion will develop. Distortion especially occur with capacitor plates, shielding structures I/Os where there many stacked structures. additional effect conductor stack dielectric thinning. point concentration lamination force areas conductor stacking results dielectric thinning flow. Dielectric these areas been shown thin much mils affecting layer layer capacitance coupling. designer should incorporate this effect into models. Version 01/05/2000 Page
4.13.
Large Area Planes
Construction Conductor planes ground power planes other areas where bulk conductor coverage desired made density grid planes. preferred plane uses lines centers sets right angles. edges these planes should left ends. axis lines grid plane either parallel 45-degree angle edge part. Solid sections mils mils permitted. Pass Through cases where must pass through power, ground other grid layer, power ground conductor should kept back from shown illustration below. 0.015 minimum line
4.13.1.
4.13.2.
Conductor Traces Grid Plane Layers cases where conductor must placed adjacent grid plane layer conductor must designed same standards grid plane i.e. 10-mil line with spaces. Once lines mils away from grid they revert normal routing.
4.13.3.
Version 01/05/2000 Page
CERAMIC MATERIAL PROPERTIES
5.1.
Property
Ceramic Materials
mils, S.D. mils mils, S.D. mils mils, S.D. mils mils, S.D. mils 0.15% >10E12 Ohms layer >1000 Volts PPM/C 3.16 gm/cc microns W/mK 0.729 J/g*°C 25°C7
mils, S.D. mils 7.54 0.0015 >10E12 Ohms layer >1000 Volts PPM/C gm/cc microns W/mK
mils, S.D. mils mils, S.D. mils mils, S.D. mils <.002 >10E12 >1000 Volts layer PPM/C 2.50 gm/cc W/mK >210
Thickness (Bare Dielectric)23
Dielectric Constant MHz* Dissipation Factor MHz* Insulation Resistance Breakdown Voltage* Thermal Expansion (25-300C)* Density Surface Roughness Thermal Conductivity* Flexural Strength* Specific Heat Sapphire Manufacturers published data.
Different Thickness' Dielectric usually mixable. design with vertical symmetry layout less risk than that wildly unsymmetrical. Incoming Inspection Results Engineering Measurement Private Communication M.A.Smith
Version 01/05/2000 Page
CONDUCTOR PROPERTIES
6.1.
Conductor Properties Tape System
DuPont Designation Nominal Thickness Built Microns Nominal Resistance milliohms Square8 microns9 Mili Ohms Via14 Mili Ohms Via15
Usage Tape System
Solderable Surface Conductor Wire Bondable Surface Conductor Buried Conductor10 Buried Conductor (thick)11 Buried Conductor Buried Conductor FineLine13 Vias
6146N 5742 6142 6145D 6145D 6453 6141
Transition Vias Marking Text Black16 Solder Stop Blue Solder Stop Clear Solder Stop Black
6138
5682 5704 9615 5682
Measured value deposited thickness Manufacturers Data This conductor used surface where additional conductivity wanted solderability required some risk. Please review with LTCC Engineering before specifying. used layer part part layers Measured value deposited thickness Photo Formable Material Calculated from measured Resistance string 1078 diameter vias 951AT (3.6 mil) tape. Based relative properties PdAg inks. Marking Solder stop materials laminated into surface have apparent thickness only used surface part.
Version 01/05/2000 Page
6.2.
Conductor Properties Tape System
DuPont Designation Nominal Thickness Built Microns Nominal Resistance Milli Ohms Square17
Usage Tape System
Solderable Surface Conductor Mixed Parts Solderable Surface Conductor Parts Wire Bondable Surface Conductor Buried Conductor Vias
HF515
HF615 HF514 HF602 HF600
~0.3 Mili Ohms Mili Ohms
Transition Vias
HF610
deposited thickness.
Version 01/05/2000 Page
6.3.
Mixing Gold Silver
following scheme connecting dissimilar materials gold silver reliably either each other into same circuit.
Gold Transition Silver Alloy
Transition Internal Silver
6.4.
Thickness Profile
conductor materials deposited viscous pastes; result, thickness profiles non-rectangular shapes. following micrographs meant give sense actual condition.
6.4.1. 6142 Cross Section micron thickness
Version 01/05/2000 Page
6.4.2. 6145 Cross Section micron thickness
6.4.3. 6146N connecting 6141 6142 ceramic thickness
Version 01/05/2000 Page
LAYOUT CONSIDERATIONS ELECTRICAL FEATURES
7.1.
Inductors
From construction stand point Spiral Inductors merely long conductors that happen coil around themselves. manufacturing, important design consideration that inner catch must clear adjacent conductor design rule spacing more preferably should occur center point spiral give best possible yield. 7.1.1. Inductor Shapes
Spacing Violation
Minimum, space Scale exagerated clarity
Preferred
Version 01/05/2000 Page
7.2.
Capacitors
From manufacturing standpoint, capacitors green tape simply large areas conductor usual conductor design rules apply. Capacitor plates, large areas conductor, acceptable 0.250 inch square. Adjacent capacitor plates maximum size, must separated space equal size capacitor plate
Capacitor Plate Capacitor Plate Space 7.2.1. Maximum Percent Coverage Maximum Conductor Coverage 7.2.2. Best practice capacitor plate design Best practice capacitor plate design have plate mils side larger than other plate reduce alignment effects.
Version 01/05/2000 Page
STYLES
8.1.
Clip Leads
Clip leads provide effective strain relief penalty height cost real estate they require. lead bent into almost desired configuration; "L", "J", etc. developed cost-effective substitute Grid Array (PGA) microprocessor other high density applications. provides large number termination points without using level real estate. flexibility solder ball provides sufficient strain relief reasonable life many Board applications. Larger balls provide longer life increase thickness. Edge striped parts (castellations) provide lower profile surface mount than some sacrifice life density. There number manufacturers clip leads worldwide. well-known examples are: Electronics 120-12 28th Avenue Flushing, 11354 (718) 961-6757 Proner Comatel Maison Rouge Lognes, France
variables selection clip lead throat depth (X-Y real estate used) opening (LTCC thickness).
Version 01/05/2000 Page
illustration below 50-mil pitch lead that used several applications. lead bent required customer's assembly. 8.1.1. Clip Lead Illustration
Clip Leads solder Palladium Silver metallization bottom surface parts. Electrical connection vias either both pads required part design. connection both pads recommended highest reliability. Solder size required determined rules governing component placement. 8.1.2. Current part (lid removed) showing clip lead.
Version 01/05/2000 Page
8.2.
Ball Grid Array (BGA)
8.2.1. Standard Ball grid arrays available patterns presently supported JEDEC Solid State Product Outlines M0-156, M0-157 selected customs. 8.2.2. Typical Layout
Typical location centered, center locations permissible.
following Schematic Layout Construction Rules have been developed maximum reliability specific configurations 8.2.3. Schematic Layout Donut
8.2.4. Construction Rules Family Sn10/Pb90 ball Sn10/Pb90 ball pitch Pitch attached with attached with Feature Sn62/Pd36/Ag2 Sn62/Pd36/Ag2 6138 PdAg 6138 PdAg Pt/Au Pt/Au Donut 5682 Black Glass 5682 Black Glass Note: Details transition materials selections proprietary. Version 01/05/2000 Page
8.2.5. Example Part Cross Section ball
8.2.6. Example Part ball
Version 01/05/2000 Page
8.3.
Castellation
type packages with side conductor stripe facilitate visual inspection board assembly produced using castellation notch side part. Avoid cost sensitive (high production) products. preferred option. standard configuration 17-mil notch (centered from outside edge part) 50-mil pitch with 21-mil diameter ring surface attaching 35-mil bottom. driver bottom size assembly house system reliability requirements. Connections pads made through vias coming from bottom part down from ring larger part. Side connections permitted. closest castellation placed corner part mils. 8.3.1. Typical Layout
Plan View
8.3.2. Cross Section Ring Internal Castellation Bottom
Version 01/05/2000 Page
8.3.3. Example Parts
8.4.
Others
There wide variety other styles that described here. Some others include: Land Grid Array Grid Array Butterfly]
Version 01/05/2000 Page
8.5.
Recommended Configurations
Based worldwide view LTCC applications mobile electronics application, makes following observations recommendations. larger parts (~600 mils) Clip Leads will provide longest thermal cycle Life penalty both height board area. ball pattern pitch provides life ~700 cycles -40C +125C with minute soaks minute transitions when applied thick with Sn63 solder. Underfill will greatly increase thermal cycle life. moderate size parts (~350 mils) Pattern pitch provide similar life. lower profile applications, land grid array approach using generously sized pads high solder coverage been successful. particular example uses peripheral pads pitch with entire area between pads filled with grounding metallization that soldered down resulting 80%+ solder attach area good performance effective underfill created high solder attach area. suggests that this superior approach.
Version 01/05/2000 Page
FILM RESISTORS
9.1.
Introduction
National Semiconductor pioneered co-fired surface buried resistors LTCC ceramic.
9.2.
Surface Resistors
Surface resistors available fired tolerances with good tracking adjacent resistors laser trimmed tolerances less than ±0.5 ohms. There seven resistor film values presently available. Blending between adjacent materials custom film values usually possible. These surface resistors applied side part only. many different resistor films values used part. aggregate resistor coverage limited part area. resistor termination metal same Pd/Ag alloy mask surface mount pads same mask except surfaces where separate mask required resistor termination metal. Surface resistors must over coated preserve performance. additional mask 5mils side larger than resistor required. Trimmed resistor should designed fire their nominal value. example: resistor required, design resistor fire ohms.
Version 01/05/2000 Page
9.2.1. Available Materials-Cofired Surface Resister
NSC-2011 NSC-2015 NSC-2021 NSC-2031 NSC-2041 NSC-2051 NSC-2061 Ohms Square 6.15 14.7 37.9 6.68k 46.8k 545k
HTCR
CTCR
-130 -350 -220 -260
9.3.
Buried Resistors
Buried resistors available fired tolerances with good tracking adjacent resistors There three resistor film values presently available. Blending between adjacent materials custom film values possible. These buried resistors applied multiple internal layers part. many different resistor film values used layer. aggregate layer resistor coverage limited part area.
9.3.1. Available Materials Buried Resistors HTCR22 CTCR23 Ohms Square CF021 CF031 CF041 1,000 10,000 ±200 ±200 ±200 ±200 ±200 ±200
Pulse -0.01% -0.01%
long, square terminated PdAg only current process control results long, square terminated with PdAg 125C, preliminary engineering data only, guaranteed value. long square terminated with PdAg -40C, preliminary engineering data only, guaranteed values. mils long, square, terminated 6142 manufacturers data mils long, square, terminated 6142 manufacturers data 125C mils long, square, terminated 6142 manufacturers data
Version 01/05/2000 Page
9.4.
Resistor Layout Characteristics Termination Table
Characteristic
Length Width Aspect Ratio (L/W) Termination Width Termination Overlap Edge Clearance Probe Location
Maximum
0.400" 0.400' corner termination
Minimum
.020 .020 .008 .008 .008 .030 mils from inner edge termination
fired resistors tolerance with mils minimum dimensions permissible.
9.5.
Typical Layout Termination Table
Length Overlap Termination Width
Width
Remote Probe Probe Preferred Location
Probe Pads required trimmed resistors. They located resistor termination shown remotely located, connected surface buried conductor. Both probe pads given resistor must same part surface resistor, some clever designers pads provided mounting other components probe pads.
Version 01/05/2000 Page
9.6.
Typical Design Curves
following typical design curves resistor materials from development effort. important note change effective square value resistor size aspect ratio changes. 9.6.1. NSC-2021 Development Curve
NSC-2021 Surface Co-Fired Effect Size Aspect Ratio Resistance
Resistance (Ohms)
Resistor Length (Mils) Quarter square Half Square Square Square Four Square
Version 01/05/2000 Page
9.6.2. NSC-2031 Development Curve
NSC-2031 Surface Co-Fired Effect Size Aspect Ratio Resistance
4500
4000
3500
3000 Resistance (Ohms)
2500
2000
1500
1000
Resistor Length (Mils) Quarter square Half Square Square Square Four Square
9.6.3. NSC-2041 Development Curve
NSC-2041 Surface Co-Fired Effect Sixe Aspect Ratio Resistance
35000
30000
25000 Resistance (Ohms)
20000
15000
10000
5000
Resistor Length (Mils) Quarter Square Half Square Square Square Four Square
Version 01/05/2000 Page
9.6.4. NSC-2051 Development Curve
NSC-2051 Surface Co-Fired Effect Aspect Ratio Resistance
180000
160000
140000
120000 Resistance (Ohms)
100000
80000
60000
40000
20000
Resistor Length (Mils) Quarter Half 4Sq.
9.7.
Example Part with Resistors
Version 01/05/2000 Page
Capacitors
Capacitors made different techniques LTCC. most common technique used value elements taking advantage ceramic tape itself. Using this k=~7.8 material, mils fired thickness, capacitance density about 0.0005pF square achieved, mils fired thickness, capacitance density about 0.001pF square achieved. Multiple plate capacitors frequently used generate additional capacitance. Consideration self-inductance SelfResonant Frequency must given. capacitance tolerance here calculated directly from tape thickness variability. table below gives some example capacitor sizes values calculated without allowance edge effects, which will increase effective capacitance.
10.1.
K=7.8 Tape Sheet Capacitors24
Inches Square t=3.5 mils 0.045 0.063 0.077 0.089 0.100 0.141 0.200 0.245 0.28325 0.31626 Inches Square t=1.7 mils 0.031 0.044 0.054 0.062 0.070 0.098 0.139 0.171 0.197 0.220
(pF)
second alternative involves printing patches high dielectric constant material affect (Metal Insulator Metal) configuration. Using this technology proprietary dielectric pastes, much higher capacitance densities possible. Tolerance capacitance here 20%.
Calculated edge effects, reference only. Larger than allowable single plate size Larger than allowable single plate size
Version 01/05/2000 Page
10.2.
Printed Patch Capacitors27
C0328 Inches Square 0.024 0.034 0.041 0.048 0.053 0.076 0.107 0.131 0.151 0.169 0.23930 C2029 Inches Square 0.009 0.012 0.015 0.017 0.019 0.027 0.038 0.047 0.054 0.061 0.086
(pF)
10.2.1. Application Patch capacitors require three masks: Mask Bottom Plate Metal Mask Dielectric typically same size bottom plate meal Mask Plate Metal mils side smaller than dielectric Connection bottom plate usually conductor trace going rest circuit. used must staggered with respect connecting plate. Connection plate from layer above. 10.2.2. Usage limits used internal layer with coverage limited conductor design rules, maximum area coverage three capacitor layers maximum only used middle layer part stack coverage limited area coverage 100-mil maximum dielectric size.
Calculated edge effects, reference only. pF/Sq k=~7.8 dielectric thickness, reference only pF/Sq. k=~60 dielectric thickness, reference only Larger than allowable single plate size
Version 01/05/2000 Page
10.2.3. Electrical Performance: Property Ohms Insulation Resistance 0.15% Dissipation Factor cycles -55C Thermal Shock +125C Resistance Resistance Resistance Life Test 10.2.4.
Ohms 0.65%31 cycles -55C +125C 8,000V hits 2,000V hits >2,000 Hours32
Dissipation Factor Temperature
10.2.5.
Dissipation Factor Frequency
25C, chart temperature frequency effects
Version 01/05/2000 Page
10.2.6.
Calculated reference only
Version 01/05/2000 Page
Wire Bond Pads
Wire bond pads constructed with DuPont 5742 Gold suitable both gold aluminum wire bonding. Gold bonding typically using 1.25 nominal size wire ball-stitch mode.
11.1.
Wire Bond Layout
Scale
Version 01/05/2000 Page
11.2.
Layout:
Value (mils) 1.25 Comments Space attach squeeze out, LTCC Manufacturing issue. Clearance between attach Wire bond, LTCC manufacturing issue Depends capillary selection mils preferred wire bonders mils available fine line Recommended high yield Recommended high yield manufacturability. gold ball bonding wire angle shall less than degrees minimum bond width shall increase every degrees wire angle. Wedge boding wire angle shall less than degrees Fiducials required designs. Fiducials shall least mils diameter placed diagonal from each other corners wire bond area. indicator adjacent fiducial. Bridge adjacent common pads layer maximum bondability Clearance required Glob solder shorts.
Description Minimum Edge Mounting Edge Minimum Mounting Wire Bond Edge Minimum Pitch Gold Wire Diameter Ranges Minimum LTCC Bond Width Minimum LTCC Bond Spacing Minimum Bond Length (via free area) Maximum Number Bond Rows Maximum Wire Lengths
Wire Bond Angle
Minimize
Alignment Fiducials Required
Indicator Common Connections
Component Wirebond
Version 01/05/2000 Page
11.3.
Actual Wire Bonded Pattern
1.25 gold wire bonding bond sites.
NOTE: Lack alignment between wire bond angles!
Version 01/05/2000 Page
11.4.
Typical Process Parameters 1419 Wire Bonder
Parameter wire Force (ball bond) Force (stitch bond) Time (ball bond) Time (stitch bond) Ultrasonic Power (ball bond) Ultrasonic Power (stitch bond) Temperature Loop Height Setting 1.25mil 40ms 50ms 174mil
bonding done with: Wire 1.25mil gold wire, elongation (American Fine Wire AW14) Capillary SBNS-43FF-CM 1/16
11.5.
Typical Pull Data
Typical Pull Test Results: Minimum grams, Averaging grams. Typical Failure neckdown Stitch Bond
Version 01/05/2000 Page
FACTORY INTERFACE
12.1.
Design Basis Transfer
Customer designs submitted full-scale (1:1) single format Gerber AutoCADdxf file format. Each feature type (Via Layer Conductor Layer Layer etc.) allocated separate design layer. array, expansion offset work done factory. "readme" other file describing layering scheme required. Electronic transmission files less than 15MB e-mail acceptable NSC's mail server ensure data integrity files must zipped tarred. Larger files segmented sent 100MB Diskor CD-ROM.
12.2.
Data Format
Format specifications known work reliably include: Gerber RS-272 format, inch system with format AutoCAD Version lower files AutoCAD Light files complete sample files freeware Gerber viewer available from: Mike Ehlert LTCC Engineering Manger (949) 380-2010 michael.ehlert@nsc.com
12.3.
Design Transfer Check List Part Definition Length, Width, Thickness etc. Data Files Embedded Component Specification Values Tolerance Schematic Bill Material (BOM) parts requiring assembly component
size, value performance specification minimum. Where specific sources required, that information must supplied too. Wire Bond Diagram parts with requiring bonding.
Version 01/05/2000 Page
12.4.
Sample Layer Plot
Version 01/05/2000 Page
12.5.
Typical Flow Chart Statement Work LTCC Substrates Build
following Statement Work, SOW, defines process transfer design manufacturing. This process defines needed inputs, standard milestones standard cycle time build unpopulated LTCC substrates based design input. Definition Design Inputs National Semiconductor will perform review designs prior transfer LTCC manufacturing assure compliance National's Design Guidelines reduce risk errors sub-optimal designs that could effect yield performance. accomplish this, design must provided format suitable review final arraying into panels manufacturing. preferred format Gerber although .dxf substituted. Other formats will considered must approved National prior submission. addition, design inputs should include information component layout, component identification location schematic that identifies components, both discrete embedded required. Design Transfer Process After receipt complete design inputs, Design Transfer process starts. This process includes review assure compliance manufacturing requirements suggestions improve producibility where suitable. Plots layers schematic layout check will completed. Internal documents required manufacturing including build request, materials list, data base, schematic list required will generated from supplied design database. this information will entered into Documentum system used National control information database used manufacture both engineering production builds. When documents available reviewed, corrections improvements will made database required. This involve Preliminary Design Review collect provided inputs designer. After necessary correction, any, completed formal Critical Design Review, CDR, will held where transfer made LTCC Engineering. usually held within working days after documents complete changes database made. LTCC Prototype Manufacturing Once design database transferred, LTCC Engineering arrays design(s) standard array adds manufacturing aids such fiducials unused areas array. Engineering also provides expansion factor accommodate shrinkage that occurs during firing ceramic during LTCC standard process. event that problems encountered during array mask generation process, LTCC Engineering will inform designer that corrective Version 01/05/2000 Page
actions taken. follow-on required depending corrective action required. LTCC Engineering then uses database generate masks punch files build parts with. netlist then used build test program open shorts testing fired parts. This testing will performed using soft-tooled flying probe tester. Production volumes require hard-tooled test probes that developed covered under prototype phase. standard cycle time build three LTCC panels that meet design guidelines have eight fewer layers weeks less from shipment parts given that appropriate purchase order place. Schedule Pricing From time compliant data base delivered time working days. Many times however, errors layout requirements optimization extend this time unpredictably. Once successfully completed, manufacturing cycle time weeks purchase order three panels with eight layers less. This does include parts with trimmed resistors does allow some special metals wirebonding solder stop materials etc. will singlulate parts green state fire them singulated. will deliver output equivalent three(3) LTCC panels ship customer. panel equivalents will identified LTCC9934 LWF; where L=LTCC W=wafer F=foundry. purchase order should contain following line items: unit LTCCNRE $TBD units LTCC9934 each $TBD each
Delivery weeks receipt Customer Design Requirements.
Version 01/05/2000 Page
Version 01/05/2000 Page
OTHER CAPABILITIES
factory significant capabilities other areas including:
13.1. 13.2. 13.3. 13.4.
Cavities Multilevel Bond Shelves Brazing Grinding
Please enquire with your specific needs further information
Version 01/05/2000 Page
Revision Record
Revision
Date/By
1/4/99 1/15/99
Description
Major re-write Film Resistor Films Values Resistor termination material preliminary Added marking solder stop Conductors Major Revision Added Logo Front Page Reworded flatness clarity Added wire bond table, dimensions sketch Number Tables figures Clarify Surface resistor Termination Metal. Added Statement work flow chart Clarified clearance requirements narrow width lines.
11/17/99 12/5/2000
Version 01/05/2000 Page
Other recent searches
SSM6N16FE - SSM6N16FE SSM6N16FE Datasheet
SML32LF - SML32LF SML32LF Datasheet
NE32500 - NE32500 NE32500 Datasheet
NE27200 - NE27200 NE27200 Datasheet
MBR3030PT - MBR3030PT MBR3030PT Datasheet
HRW0302A - HRW0302A HRW0302A Datasheet
1SV311 - 1SV311 1SV311 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
