Converter Definition Terms ANALOG INPUT BANDWIDTH measure frequen

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Converter Definition Terms ANALOG INPUT BANDWIDTH measure frequen

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Converter Definition Terms
Converter Definition Terms
ANALOG INPUT BANDWIDTH measure frequency which reconstructed output fundamental drops below frequency value full scale input. test performed with equal plus integer multiples fCLK. input frequency which output relative frequency input signal full power bandwidth. APERTURE JITTER variation aperture delay from sample sample. Aperture jitter shows input noise. APERTURE DELAY Sampling Delay. BOTTOM OFFSET difference between input voltage that just causes output code transition first code negative reference voltage. Bottom Offset defined VZT-VRB, where first code transition input voltage lower reference voltage. Note that this different from normal Zero Scale Error. CONVERSION LATENCY PIPELINE DELAY. CONVERSION TIME time required complete measurement analog-to-digital converter. Since Conversion Time does include acquisition time, multiplexer time, other elements complete conversion cycle, conversion time less than Throughput Time. COMMON-MODE ERROR specification which applies ADCs with differential inputs. change output code that occurs when analog voltages inputs changed equal amount. usually expressed LSBs. DIFFERENTIAL GAIN ERROR percentage difference between output amplitudes given amplitude small signal, high frequency sine wave input different input levels. DIFFERENTIAL NON-LINEARITY (DNL) measure maximum deviation from ideal step size LSB. commonly measured rated clock frequency with ramp input. DIFFERENTIAL PHASE ERROR difference output phase reconstructed small signal sine wave different input levels. DYNAMIC SPECIFICATIONS those pertaining input signal. These include ratio, SNR, SINAD, S/(N+D), ENOB, THD, IMD, FPBW, SSBW. EFFECTIVE NUMBER BITS (ENOB, EFFECTIVE BITS) another method specifying Signal-to-Noise Distortion Ratio, SINAD. ENOB defined (SINAD 1.76)/6.02 says that converter equivalent perfect this (ENOB) number bits. FULL POWER BANDWIDTH frequency which reconstructed output fundamental drops below frequency value full scale input. test performed with equal plus integer multiples fCLK. input frequency which output relative frequency input signal full power bandwidth. FULL SCALE (FS) INPUT RANGE input range voltages over which will digitize that input. VREF+ 3.5V VREF- 1.5V, (VREF+) (VREF-) 2.0V. FULL SCALE ERROR measure last code transition from ideal 11/2 below VREF+ defined Vmax VREF+ where Vmax voltage which transition code occurs. FULL SCALE STEP RESPONSE defined time required after goes from VREF- VREF+, VREF+ VREF-, settles sufficiently converter recover make conversion with rated accuracy. GAIN ERROR (FULL SCALE ERROR) difference between input voltage just causing transition positive full scale VREF LSB. GAIN TEMPERATURE COEFFICIENT (FULL SCALE TEMPERATURE COEFFICIENT) change gain error divided change temperature. Usually expressed parts million degree Celsius (ppm/°C). INTEGRAL NON-LINEARITY (INL) measure deviation each individual code from line drawn from zero scale negative full scale (1/2 below first code transition) through positive full scale (1/2 above last code transition). deviation given code from this straight line measured from center that code value. point test method used. commonly measured rated clock frequency with ramp input. INTERMODULATION DISTORTION (IMD) creation additional spectral components result sinusoidal frequencies being applied input same time. defined ratio power intermodulation products total power original frequencies. usually expressed MISSING CODES those output codes that skipped will never appear outputs. These codes cannot reached input value. (MOST SIGNIFICANT BIT) that largest value weight. value half full scale. OFFSET ERROR difference between ideal transition actual transition point. OUTPUT DELAY time delay after edge input clock before data update present output pins. OUTPUT HOLD TIME length time that output data valid after edge input clock. OVERRANGE RECOVERY TIME time required after goes from AGND VREF+ goes from VREF- converter recover make conversion with rated accuracy. PIPELINE DELAY (LATENCY) number clock cycles between initiation conversion when that data presented output driver stage. Data given sample available Pipeline Delay plus Output Delay after
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2000 National Semiconductor Corporation
MS101150
Converter Definition Terms
that sample taken. data available every clock cycle, data lags conversion Pipeline Delay plus Output Delay. PSRR (POWER SUPPLY REJECTION RATIO) ratio change power supply voltage resulting change Full Scale Error, expressed QUANTIZATION ERROR error inherent conversions. Since even 'ideal' converter finite resolution, analog voltage that falls beween adjacent output codes will result output code that inaccurate LSB. RATIOMETRIC OPERATION uses same reference voltage that used drive signal source such that ratio output that signal source reference constant. When driving voltage that source also used voltage reference ADC, output code function ratio signal source output reference voltage and, limited reference voltage range, independent value that reference voltage. RESOLUTION smallest analog increment corresponding converter code change. converters, resolution normally expressed bits, where number digital codes equal example, 12-bit converter maps analog signal into 4096 digital codes. SAMPLING (APERTURE) DELAY time after edge clock when input signal acquired held conversion. SIGNAL NOISE RATIO (SNR) ratio, expressed value input signal output value other spectral components below one-half sampling frequency, including harmonics SIGNAL NOISE PLUS DISTORTION (S/(N+D) SINAD) ratio, expressed value input signal output value other spectral components below half clock frequency, including harmonics excluding
SPURIOUS FREE DYNAMIC RANGE (SFDR) difference, expressed between values input signal output peak spurious signal. where spurious signal signal present output spectrum that present input. STATIC SPECIFICATIONS specifications pertaining signal input. These include gain error, offset error, differential integral linearity errors. THROUGHPUT RATE maximun continuous conversion rate ADC. THROUGHPUT TIME inverse Throughput Rate. OFFSET difference between positive reference voltage input voltage that just causes output code transition full scale defined VREF+ where full scale transition input voltage. Note that this different from normal Full Scale Error. TOTAL HARMONIC DISTORTION (THD) ratio, expressed dBc, total first harmonic components value input signal output. TOTAL UNADJUSTED ERROR (TUE) maximum deviation voltage corresponding center digital code's associated input voltage span from ideal case. Total unadjusted error includes offset error, Gain error, differential integral nonlinearity errors. ZERO SCALE OFFSET ERROR difference between ideal input voltage (1/2 LSB) actual input voltage that just causes transition from output code zero output code one. ZERO ERROR difference between ideal input voltage (1/2 LSB) actual input voltage that just causes transition from output code zero output code one.
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critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
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