1993 National Semiconductor Corporation Printed U.S.A. Tutor

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1993 National Semiconductor Corporation Printed U.S.A. Tutor

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With operating frequencies exceeding 300MHz, National's line monolithic hybrid current feedback operational amplifiers have become attractive option (and design engineer. Typical operational amplifier specifications not, however, include many common specifications familiar engineers. help designer exploit many advantages these amplifiers offer, this application note will define specifications most interest designers, detail what determines each these particular performance characteristics National's current feedback amps, and, where possible, discuss performance optimization techniques. apply amps applications, questions three general areas must addressed: Setting amp's operating conditions Small signal performance context Typical limits amplifier dynamic range applied amps Wherever possible, tested performance using CLC404 will used demonstrate performance. CLC404 power supply monolithic amplifier intended over voltage gain range ±10. optimum gain CLC404 offers 175MHz frequency range while delivering 12dBm power into load while dissipating only 110mW quiescent power. National offers wide range additional monolithic amps, well higher supply voltage (and hence higher power output) hybrid amplifiers. best amplifier particular application will depend upon desired gain, power output, frequency range dynamic range. Operation National's Current Feedback Amps current feedback amp, developed National Semiconductor Corporation, provides very wideband, coupled that distinct advantage being relatively gain-bandwidth independent. with amps using closed loop negative feedback structure, frequency response National amps loop gain characteristics. development National amplifiers de-couple signal gain from loop gain part transfer function. This de-coupling allows desired signal gain changed without radically impacting frequency response. compared voltage feedback amplifiers, which constrained gain-bandwidth product operation, current feedback topology offers truly
1993 National Semiconductor Corporation
Printed U.S.A.
Tutorial Applying Amps Applications
September 1993
impressive equivalent gain-bandwidth products (e.g. CLC401 gain yields flat response with -3dB bandwidth 150MHz. match this, voltage feedback would require 20*150MHz 3GHz gain-bandwidth product). Please refer National application note OA-13 description current feedback topology transfer function. changes going from classical amplifier using exceptional flexibility offered amps. designer charged with setting proper operating conditions amp, defining gain, determining impedances with external components. amps allow designer option running either non-inverting inverting gain path. applications, 180° phase shift provided inverting mode often incidental. There are, however, advantages disadvantages each mode, depending desired performance, both will considered each stage this development. Most this discussion applying amps applications applies type amp. unique advantages current feedback topology higher frequency capabilities intrinsically distortion operating currents. specifically stated being unique current feedback topology, items considered here apply equally well voltage feedback amp. starting point describing amps applications, useful summarize some standard operating assumptions typical amplifiers. Although there certainly exceptions typical conditions shown here, amplifiers generally have: coupled input output. voltage generally little meaning applications. Input output impedances nominally (AC) over frequency range operation. This seldom physical resister, rather combination active element impedances along with passive matching networks. Fixed signal gain operations over certain band frequencies. particular purchased provide particular gain user adjustable. decade range operating frequencies seems typical.
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Single power supply operation. Since both input output coupled, bipolar power supplies, balanced around ground, needed. bias point maintained internally with minimal user adjustment possible. Figure shows typical amplifier connection, while Figures show ideal amp, either current voltage feedback, connected non-inverting inverting gains, respectively.
ideal inverting differs several respects from non-inverting. output voltage ideally 180° phase from input, which accounts signal inversion. amp's input ideally presents virtual ground, while drawing minimal current, either voltage current feedback amps. This leaves ideal input impedance seen source, while voltage gain from input output simply Rf/Rg. This signal inversion usually consequence application, most this discussion will deal only with magnitude inverting gain.
Figure Ideal Inverting Figure Typical Amplifier Connection amplifier, both input output coupled, while single power supply biases part through chokes output signal from seeing power supply load. amplifier signal gain specified with output driving load defined 10*log (power gain). ideal circuits assume that source coming from ground referenced, zero impedance voltage source while their outputs intended ideal (zero output impedance) voltage sources ground referenced load. non-inverting configuration ideally presents infinite input impedance, zero output impedance, voltage gain, shown Figure from plus input output pin. When using amps amplifiers, must first satisfy impedance matching requirements, recast gain from voltage gain power gain dB), possibly configure operation from single power supply. Figures show amps Figures provide impedance matching with resulting power gain equations, still using bipolar supplies. bipolar power supplies allow operation maintained down Single supply operation possible will considered next. non-inverting case, setting simply requires termination resistor ground noninverting input, Getting simply requires series resistor output,
Figure Ideal Non-Inverting
Figure Non-Inverting Configured Application
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inverting mode operation, input ground referenced, while signal channel input impedance becomes parallel combination 0A-13 describes, current feedback topology depends value feedback resistor determine frequency response. With each particular calling particular optimum then used gain along with will input impedance. Setting yield desired gain then setting satisfy will work until required Having fixed satisfy amplifier's stability requirements, going higher higher inverting gains will eventually yield Rg's Non-inverting operation should used this limitation reached. can, however, increased beyond recommended value current feedback order allow higher gains, only expense decreasing bandwidth.
10log
20log (8(50 )(0.001)) 20log
Conversely, given dBm) 4)/20 Peak Peak voltage swing load
4)/20 Peak Peak voltage swing output Figure Converting Between Voltage Swings Power Every specified maximum output voltage swing that generally shown peak excursion from ground. This type specification, balanced bipolar power supplies, really inferring close output come supply voltages before non-linear limiting occurs. coupled applications, always best hold output level centered between supply pins order provide maximum output Vpp. Application note OA-15 discusses more detail input output voltage range considerations. Most National's amps require ground reference proper operation easily operated from single supply. Generally, that required keep voltage input output centered between voltages appearing supply pins. single supply operation (with supply held ground) this translates into input being held Vcc/2. those amplifiers requiring ground pin, that should also driven with source impedance voltage midway between supply pins. There many possible implementations single power supply operation. Figures show simple ways operate non-inverting inverting amps coupled amplifiers using single power supply. non-inverting case, input termination still coupled, while input bias Rb's yield Vcc/2. should large enough limit excessive quiescent current bias path, large generate excessive errors amplifier's input bias current. gain setting resistor, also coupled limit gain Hence, input bias voltage also appears output pin. output should coupled both circuits limit current that would required grounded load were driven.
neglecting signal inversion
gain 20log Given desired (10G
Figure Inverting Configured Application Note that both topologies gain matched load been half (-6dB), from earlier ideal case, through voltage divider action simple, critical, conversion from description output voltage swing from power dBm) defined load. Figure shows these conversions purely sinusoidal signal. Basically, whatever initial description voltage swing given, need convert that into voltage, square divide load normally) absolute power watts. This then divided 0.001 reference that power 10*log that expression taken yield power dBm.
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Scattering Parameters Input reflection Output reflection Forward transmission
Amplifier Specifications Input VSWR Output VSWR Amplifier gain bandwidth Reverse transmission Reverse isolation
These frequency dependent specifications measured using network analyzer S-parameter test set. full 2-port calibration should performed prior device measurements. HP8753A, used measurements reported here, incorporates full term error correction 2-port calibration. This basically normalizes measurement errors imperfections cabling test hardware (reference Figure Single Supply, Non-Inverting Operation single supply inverting amplifier Figure still require midpoint reference brought input. de-coupling capacitor that node also suggested decrease source impedance non-inverting input noise current. gain this noninverting input reference voltage again coupled yield unity gain Vcc/2 output pin. inverting input impedance goes from higher frequencies. well Figure could also coupled avoid loading source. Figures show configurations CLC404 used demonstrating small signal performance parameters listed above. each case, S-parameter test places device into input output environment. Both configurations achieve voltage gain output load. This yields gain 20*Iog(3) 9.54dB measured network analyzer. Recall that advantages using amps applications exceptional flexibility setting gain. wide range gains could have been selected test circuits Figures selected allow easy comparisons CLC404's data sheet specifications, which defined gain
Figure Single Supply, Inverting Operation both these single supply circuits, have given coupling signal path. frequency limits operation will coupling capacitors, along with impedances each part circuit. subsequent discussions assume balanced bipolar supplies, apply equally well single supply operation. Small Signal Performance Characteristics typical small signal parameters specified amplifiers derived from S-parameters (reference These are:
Figure Non-inverting Amplifier S-parameter Test Circuit inverting gain configuration, along with sets input impedance retained non-inverting input limit possibility self-oscillation non-inverting input transistors (See application note OA-15).
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frequencies. test frequency increases, however, amp's output impedance will begin increase loop gain rolls (reference page 237). This inductive characteristic partially compensated small shunt capacitance across Figure shows this, either gain polarity, along with tested output VSWR with without this shunt capacitance. value this capacitance will depend amplifier and, some extent, gain setting, determined empirically this test using small adjustable 20pF) directly across Figure Inverting Amplifier S-parameter Test Circuit Input/Output VSWR Voltage Standing Wave Ratio (VSWR) measure well input output impedances matched source impedance. assumed throughout that transmission line characteristic impedance also equal source impedance both ports-50 this case). desirable that input output impedances closely matched possible source maximum power transfer minimum reflections. VSWR whichever Figure Measuring Tuning CLC404 Output VSWR marker 200MHz indicates output VSWR 1.3:1 when tuned optimally. Tuning also extends frequency response (S21) slightly will left place remainder tests. input impedance match non-inverting topology (Figure principally frequency increases, input capacitance will eventually degrade input VSWR. This effect negligible over expected operating frequency range, however, that tuning required. input impedance match inverting topology (Figure frequencies, parallel combination This holds very well long amplifier's inverting input acts like impedance over frequency. current feedback amplifiers, inverting input actually driven, impedance buffer. It's impedance will, however, increase with frequency. voltage feedback amplifier's apparent inverting input impedance will also increase with frequency loop gain rolls off. voltage feedback case, increase inverting input impedance will seen lower frequency than current feedback amplifier will depend strongly amplifier gain setting. Figure shows tested input VSWR gain polarities Figures this case, measuring allowing HP8753A convert measurement display VSWR directly.
amplifier input output impedance test system source impedance VSWR Return loss 20log 10log input VSWR 10log output Ideal VSWR Typically, VSWR 1.5, RF-amps over their operating frequency range Measuring input VSWR simply matter measuring ratio reflected power incident power Port Figures (S11). perfect match will reflect power. Output VSWR measured similarly Port (S22). described earlier, amp's input output impedances determined external components selected designer. this reason, VSWR never shown amp's data sheet. Excellent VSWR can, nevertheless, achieved using components shown Figures amp's gain polarity minimal effect output VSWR. frequencies, itself will determine output VSWR. Setting this resistor will yield excellent output VSWR reasonably high
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Figure CLC404 Input VSWR Note carefully change scale input VSWR output VSWR plot. marker non-inverting test trace shows exceptional input VSWR 1.03:1 200MHz, while inverting, though higher, remains under 1.4:1 through this range. Forward Gain Bandwidth Typical amplifier specifications show fixed gain, defined Figure with specified frequency range 0.5dB gain flatness, along with -3dB cutoff frequencies. designer using current feedback amp, wide range possible gains easily obtainable. With CLC404's specified voltage gain range ±10, including additional loss from output load, -6dB 14dB gains achieved using CLC404. Higher gains achieved with this, other current feedback amplifier, with some sacrifice bandwidth (see application note OA-13). example, CLC401, specified over voltage gain range, translates into 11dB 28dB gain range applications. forward gain over frequency (commonly called frequency response measured S21) always appear National data sheets over range gains. Small signal -3dB bandwidth gain flatness also guaranteed particular gain each amplifier. Rarely does voltage feedback show characteristics, since strongly depends upon gain setting. Rather, these amplifiers show open loop gain phase plot leave designer predict closed loop gain phase. frequency response plots National amps normalized show each gain coming same grid plot easier comparisons frequency response shape over wide range gains. Another advantage excellent loop gain control current feedback topology exceptional forward gain phase linearity. This phase also shown frequency response plot. maximum deviation from linear phase guaranteed particular gain setting data sheet specifications. part part variation frequency response minimal hybrid amplifiers from National, with more
variation seen monolithic amps. application note OA-13 describes, current feedback topology allows easy, resistive trim frequency response shape that impact forward gain. This frequency response flatness trim same effect either non-inverting inverting topologies. Figure shows this adjustment added circuit Figure along with measured with without this trim. OA-13 describes, this resistive trim inside feedback loop effect adjusting loop gain, hence frequency response, without adjusting signal gain, which would still only This particular test achieved flatness ±.1dB from 110MHz gain 9.54dB non-inverting test circuit shown (with identical results inverting configuration).
Figure Measuring Adjusting Frequency Response Note that values have been reduced from those used circuit Figure although their ratio hence gain, have remained same. With adjustment zero ohms, this lower value ensures that frequency response will peaked particular CLC404 used circuit. Then, increasing resistance into inverting input, amplifier compensated adjusted excellent flatness shown above. part part variation frequency response becomes more pronounced desired operating frequencies signal gains increase. Operation CLC404 through 50MHz 9.54dB gain would, example, have minimal variation relative operation through 100MHz 14dB gain. ±.1dB flatness, considering rapid degradation distortion performance higher frequencies, 100MHz probably reasonable upper limit operation National amps (available time publication) applications. Higher frequency operation achieved degraded flatness distortion characteristics acceptable application. product introductions expected extend this operating frequency.
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Reverse Isolation This small signal characteristic measure much signal injected into output port makes back into input source. magnitude measure reverse isolation. National's current feedback amps exhibit excellent reverse isolation relative most amplifiers. This results from both output inverting input being driven, impedance, nodes. extent that output inverting input both present very impedances over wide frequency ranges, significant signal attenuation expected taking signal voltage applied output matching resistor tracing back either inverting non-inverting input signal. Slightly more attenuation expected non-inverting inverting configurations, since signal must also from inverting non-inverting non-inverting case. circuit Figure along with inverting circuit Figure were used measure reverse isolation both gain polarities, shown Figure Although reverse isolation generally specified positive number, this simply negative gain going backwards through amplifier. Hence, plot Figure shows rising "gain" that would interpreted decreasing reverse isolation higher frequencies. Figure shows, isolations excess 30dB easily obtainable through frequencies higher than operating frequency range, with very high isolations observed frequencies.
Dynamic Range Limiting Characteristics final area concern applying amps applications limits dynamic range familiar amplifier users. These generally limited -1dB Compression Point 2-Tone, Order, Intermodulation Intercept Noise Figure -1dB Compression Point measure maximum output power capability amplifier. 2-Tone Intercept allows prediction spurious signals caused amplifier non-linearities when input signals closely spaced frequency applied input. noise figure measure much noise added amplifier will limit minimum detectable signal. Although each these certainly measured particular configuration, their interpretation amps vary from amplifiers depending being used specification. Each these will described generally developed, and/or measured, CLC404 with anomalies interpretation noted. -1dB Compression Point Briefly stated, this expected output power, fixed input frequency, where amplifier's actual output power 1dBm less than expected. Figure shows, also interpreted ideal output power which actual amplifier gain been reduced from value lower output powers. With both axis Figure scale, output power input power will have slope shift X-axis amplifier's power gain 20dB gain used arbitrarily Figure 10), amplifier's input output transfer would ideally unity slope line through origin. additional interpretation Figure that beyond -1dB compression point output power remains fixed input power increased. were measured fixed frequency, with swept input power, would horizontal line, showing power gain, that eventually transitions slope line output power becomes fixed while input power continues increase. -1dB compression power commonly used maximum output power limit when computing amplifier's dynamic range. Standard coupled amplifiers show relatively constant -1dB compression power over their operating frequency range.
Figure Inverting Reverse Isolation Test Circuit
Figure Reverse Gain Circuits Figures
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Figure shows measured -1dB compression powers frequency CLC404 circuits Figures Since maximum output power principally function output stage, there very little difference between non-inverting inverting compression points. National amplifiers that show higher inverting slew rate than non-inverting (e.g. CLC400), higher -1dB compression power higher frequencies inverting configurations would expected. frequency value, however, should similar between polarities, since determined maximum output voltage swing (principally power supply voltages headroom requirements output stage).
Figure Compression CLC404 Figure Illustration -1dB Compression operational amplifier, maximum output power depends strongly input frequency. specifications that serve similar purpose -1dB compression output voltage range slew rate. frequencies, increasing power fixed frequency input will eventually drive output "into rails" saturation limit typically some number diode drops below supply voltages. addition, input frequency increases, amps will reach limit fast output transition. This typically specified slew rate indicating maximum dV/dT output voltage. Half this slew rate available matched load when output series matching resistor used. sinusoidal signal, maximum slew rate occurs crossing. This maximum dV/dT simply peak voltage exursion times radian frequency. Given slew rate Volts/sec (SR) frequency, maximum peak amplitude before slew limited operation experienced predicted SR/(2**frequency). However, this peak amplitude, which converted power load using expressions developed earlier, does relate directly measured compression. Although Figure shows -1dB compression defined Figure also very useful look output waveforms spectrums gain understanding what setting measured -1dB compression power. Figures show time waveform spectrum load input power that yields compression point CLC404 operating 10MHz.
Figure 12A: Output Waveform 10MHz -1dB Compression
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Figure 12b: Output Spectrum 10MHz -1dB Compression this frequency, clearly running into output voltage swing limitation. With 17.3dBm -1dB compression shown 10MHz Figure 11), would expect fundamental amplitude spectrum 16.3dBm. observed 16dBm spectrum Figure reasonable match this expected fundamental power. however, incorrect directly convert this fundamental power -1dB compression into sinusoid expect that amplifier deliver sinusoid this amplitude. 16.3dBm fundamental power predicted -1dB compression measurement, might expect that output delivering approximately 4Vpp sinusoidal swing load, swing output pin. Although this would exceed maximum output swing specification CLC404 operating volt supplies,this amplitude sinusoid fact available zero loss filter used pass only fundamental harmonic. Notice that considerable portion output power been spread into order harmonics. This typical square wave output observed time domain trace Figure 12A. fundamental (10MHz) power related output time waveform amplitude through Fourier series expansion output waveform. output were perfect squarewave, under conditions output voltage limited operation, peak square wave amplitude would generate fundamental frequency amplitude 4*A/. Going from measured peak amplitude output time waveform, anticipated -1dB compression would calculated power sinusoid times square wave amplitude +1dBm. Doing this measured ±1.8V swing Figure would predict 15.1dBm (peak-peak square wave amplitude converted dBm) 2.1dBm (20*Iog(4/)) 1dBm (reported -1dBm output power 1dBm higher than measured power) 18.3dBm. This 1dBm higher than measured. This explained less than perfect square wave shape shown time waveform Figure 12A. This less than perfect square wave will yield coefficient fundamental term Fourier expansion that actually less than predicted A*4/.
operating frequency increases, slew limit will eventually restrict achievable output swing something less than output voltage swing limit amplifier. This observed Figure approximately 30MHz CLC404. Again, instructive look time waveform resulting spectrum when operating input power that yielded -1dB compression measured gain these higher frequencies. Figures show this non-inverting circuit (Figure operating input power necessary produce measured -1dB compression with 50MHz sinusoidal input signal (From Figure this input power would 16.3dBm 9.54(gain) 6.8dBm)
Figure 13A: Measured Output Waveform 50MHz -1dB Compression
Figure 13B: Measured Output Spectrum 50MHz -1dB Compression measured -1dB compression power under slew limited conditions dependent amount power fundamental frequency generated time waveform shown Figure 13a. Although that -1dB compression must related amplifier's slew rate, would very difficult relate slew rate waveform shape then, through Fourier series, fundamental power hence -1dB compression. exact distribution power into fundamental harmonics changing over frequency. that really said that these higher frequency -1dB compressions, significantly distorted waveform
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with peak peak excursion less than that seen lower frequencies being generated. frequencies, -1dB compression power predicted approximately using analysis shown earlier assuming square wave output output voltage swing limits shown data sheet. Remember that output voltage range specified data sheet twice what delivered through loss taken from matching resistor load. not, however, possible easily predict higher frequency -1dB compression from slew rate specification. will become apparent next section, also possible relate -1dB compression third order intercept. Typical amplifiers will show order intercept 10dBm higher than -1dB compression point. National amps, they show intercept characteristic, have intercept considerably higher than what would predicted adding 10dBm -1dB compression. 2-Tone, Order Intermodulation Intercept This specification directed predicting order intermodulation distortion powers combination closely spaced frequency) input signals. amplifier modeled have polynomial approximation transfer function from input output. When input signal frequencies present, order term this polynomial approximation will give rise distortion terms frequencies that very near input signal frequencies. These closely spaced distortions considerably more troublesome narrowband channels than simple harmonic distortion terms that appear integer increments away from input signal frequency. Appendix expands spurious frequency locations distortion coefficients input signals frequencies fO-f fO+f when passed through order polynomial. With this simple definition equal deviations from center frequency average frequency), spurious frequency locations become very simple algebraic expressions Using this approach defining test frequency locations also allows clear illustration symmetric clusters spurious terms around integer multiples From appendix order inter-modulation terms fall 3fO. With input signal defined Acos(2(fO-f)t) Bcos(2(fO+f)t), input output voltage gain transfer function K2Vi2 K3Vi3 (ignoring higher order terms now), lower order spurious term with amplitude (3/4)*K3*A*B2 upper spurious with amplitude (3/4)*K3*A2*B will result. equal amplitude signals were applied input these were increased equal fashion, spurious amplitudes would increase cubic fashion. terms, input, hence output, powers
were increased 1dBm, this model predicts that output third order spurious powers will increase 3dBm. interesting note effect adjusting just input frequency power's. Changing lower test frequency power 1dBm will change lower spurious 1dBm upper spurious 2dBm. Conversely, changing upper test frequency power 1dBm will change lower spurious 2dBm upper 1dBm. dependence order spurious power output test frequency power (assuming equal powers each test frequency) shown graphically Figure
Figure Output Order Spurious Power Input Power shown Figure order spurious powers, increasing rate input power, will, some output power, "intercept" desired output powers that increasing rate input power. Another saying this that there closure rate between desired output powers undesired order intermodulation spurious powers. graph Figure arbitrarily amplifier gain 20dB (the x-axis been shifted yield 0dBm output power -20dBm input power) 30dBm order intercept. actual amplifier will able reach intercept point from output power standpoint since this intercept typically exceeds -1dB compression
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power least 10dBm. intercept intended mathematical construct allow prediction spurious power level given output signal power. amplifier that shows order intermodulation intercept characteristic, single measurement output powers spurious levels sufficient solve intercept point shown equation Figure Figure assumes equal output power levels desired output signals. more general approach, with unequal test power levels, shows that, from measurements, estimates order intercept made. Figure steps through this analysis concludes with predictive equations each order spurious levels. graphical representation shown Figure modeling what would observed spectrum analyzer measurement test spurious powers.
forward path amplifier corrected whatever loop gain amplifier that frequency. amps show loop gain that decreases with frequency. Hence, order spurious levels will, general, increase with frequency fixed output test powers (reference discusses this loop gain dependence detail). additional concern what point circuit define order intercept. order make direct comparisons amplifiers, National defines order intercept load when driving from output impedance. Some earlier National data sheets (e.g. CLC220, CLC221) defined intercept voltage swing output converted into power were driving while actually applying that output swing series into load. This effect defining intercept that 6dBm higher than what actually available load. This seen from equation shown above IM3. Recall that IM3, equal test power levels test frequencies, simply test power level +1/2 difference between test power levels spurious power levels. This difference does change going from output matched load. However, output voltage swing will drop and, since output power erroneously defined being particular voltage swing across load (when fact sees 100? load), this will translate into 6dBm drop test power level matched load. Therefore, usable intercept matched load 6dBm lower than specified those earlier data sheets that call output power calculation output pin. Given that test power level being defined matched load, important consider amplifier limitations maximum power frequency test. tone test equal powers closely spaced frequencies, available peak peak voltage swing each test frequency load peak peak output voltage available amplifier's output while available slew rate each test tone estimated amplifier's specified slew rate. 2-tone test signal being generated matched load, twice peak peak swing being generated envelope (and twice slew rate). Going back through matching resistor output will double this swing slew rate again. addition, empirical testing revealed that overall maximum slew rate output that specified slew rate will show spurious performance. slew rate output waveform exceeds this limit, additional nonlinearities come into play rapidly increasing order spurious powers. Using circuit Figure typical specifications CLC404, maximum test power level load each test tone, from output swing standpoint, would (1/4)*6Vpp 1.5Vpp. This translates into
estimate intercept IM32 Averaging these define estimate intercept IM31 Solving intercept estimates
(IM3 (IM3
Figure Order Intermodulation Intercept Calculations Typical amplifiers closely approximate this order intermodulation spurious model with intercept that relatively constant over specified operating frequency range amplifier. amps, however, show significant deviations from this simple model. principal difference that amps will show strongly frequency dependent 2-tone, order spurious performance. observed intermodulation spurious levels will function intrinsic distortion
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maximum test power level each tone approximately 8dBm. this maximum output swing, available slew rate (1/8)*2000V/µsec 250V/µsec will limit frequency operation less than (SR/(2**Vpp/2) 250E6/(2**.75V) 53MHz. test operation powers decrease, this upper frequency limit slew rate limit will increase. example, dropping power 2dBm will push this limit 106MHz. Although some National current feedback amplifiers (e.g. CLC400, CLC401, CLC560) show good approximation order intercept model, CLC404, used example circuits shown thus far, shows spurious power test power characteristic that deviates significantly from simple model Figure Figure shows difference between test spurious powers plotted function single tone test power load. Note that independent variable axis output power; input power shown Figure Ideally, this would, each frequency, yield straight line with slope (instead slope shown Figure 14). similar plot CLC401, which more closely approximates this ideal, shown Figure closely approximated order intercept model, single measurement operating power would adequate predict intercept that frequency.
order spurious plot CLC404 clearly showing some additional mechanism that holding spurious levels down output power level moves above 0dBm. lower power levels, appears that spurious characteristic moving towards linear slope predicted simple intercept model. Looking again order expansion 2-tone coefficients shown appendix additional order term contributes spurious powers observed order intermodulation frequencies. Normally, would expected that coefficient much lower than value that this order contribution neglected. However, case CLC404, coefficient make this second term significant higher operating powers. Note that contribution this order term increases power test powers more slowly increasing order term. theorized that order coefficient opposite sign order coefficient. Then, test powers increase level that this order term becomes significant magnitude order, spurious levels actually decrease increasing output power. projected intercept very power levels still used predict spurious free dynamic range. Figure intercept output powers estimated particular frequency output power minus y-axis value. However, should realized that wideband amps like CLC404 actually provide better spurious performance high powers than would predicted this power intercept model. order intercept performance typically very similar between inverting non-inverting topologies. discussed reference anything that changes loop gain will have effect order spurious performance. Increasing loop gain, either going feedback resistor values current feedback amps signal gains voltage feedback amps, will decrease spurious powers. both cases, however, increasing loop gain changing external operating point constrained closed loop stability considerations. order distortions intermodulations further reduced operating higher quiescent currents possible) and/or driving output into higher impedance load those situations requiring matched impedance environment. Noise Figure Unlike compression point order intermodulation intercept, noise figure always usable same that amp. important remember that, like compression intercept, noise figure generally developed particular frequency change over frequency. Normally, however, single value used above amp's noise corner frequency (see application note OA-12
Figure Measured Order Spurious CLC404
Figure Measured Order Spurious CLC401
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additional noise discussion appendices noise corner discussion tabulated input noise terms National amps). noise figure accurately calculated from equivalent input noise terms resistor values used achieve desired gain input impedance. Unlike amplifier with fixed gain noise figure, amp's noise figure will strongly dependent gain setting. can, however, easily predict noise figure with equations developed here. very general development amp's non-inverting noise figure will performed order allow easy comparison noise figure expressions found earlier National data sheets. inverting amp's noise figure will, however, proceed with assumption normally used that input impedance matched source impedance. idealized schematic illustrating definition noise figure shown Figure
G[Ni 10log 10log noise figure expression simplified depend only ratio noise power added amplifier input (considering source resistor place noiseless getting noise power delivered source resistor (considering amplifier elements place noiseless getting Ni). Generally, definition also constrains input impedance amplifier conjugate matched source resistor (this yields with this constraint). will, however, relax this constraint initially allow comparison expressions found National's earlier data sheets. Equation specified terms power ratio. individual noise terms are, however, expressed spot noise voltages currents (Spot means bandwidth, opposed integrated over some noise power bandwidth. OA-12). Combining separately contributing noise sources matter adding noise powers. This done converting current noises voltage through appropriate impedance, then summing squared noise voltage terms. impedance (normally needed define power) noise power bandwidth (used convert from spot integrated noise) will normalize since developing ratio powers same point circuit?Na /Ni. Getting total spot noise power then simply matter summing relevant squared noise voltages. Figure shows non-inverting configuration with individual resistor amplifier input noise terms detailed. Where; input voltage noise non-inverting input current noise inverting input current noise input terminating resistor RT's voltage noise Rf's voltage noise Rg's current noise RS's voltage noise Figure Non-inverting Noise Figure Analysis Circuit Recall that noise resistor (Johnson Noise) defined either spot current voltage noise. resister value these possible expressions are: voltage noise, current noise, 4kTR
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Noise Figure 10log 10log Figure Noise Figure Definition input output noise signal terms equation noise figure (NF) considered powers. noise power delivered source resistor input amplifier. other noise sources considered part amplifier contribute noise power, seen output. Looking parts expression (inside function) yields: Si/So No/Ni Inverse power gain provided amplifier Total output noise power, including contribution divided noise power input
simplify this, consider noise power added amplifier (reflected input port): Si/So No/Ni G*(Ni+Na)/Ni (where G*(Ni+Na
Substituting these expressions into expression:
where; Boltzman's constant 1.38E-23 Joules/°Kelvin °Kelvin 290° this analysis 16E-21 Joules 290°K amplifier noise terms available most National's amplifiers appendix OA-12. spot noise Figure below noise corner interest, appendix OA-12 also shows approximate frequency spot noise from high frequency flat band value noise corner frequency. Using circuit Figure expression developed generating expression noise power delivered source resistor noise input amplifier. This analysis simply proceeds considering noise voltages sources normal linear circuit analysis, eventually squaring resulting noise voltage delivered from Figure shows equivalent circuit resulting This considering amplifier have infinite non-inverting input impedance, with other noise sources neglected (superposition noise voltage contributions used throughout this analysis).
Noise Source
Non-inverting input voltage noise Non-inverting input current noise Inverting input current noise Input terminating resistor voltage noise Gain setting resistor current noise Feedback resistor voltage noise
Value
4kT/Rg 4kT/Rg 4kT/Rg
Voltage Gain Input
Rs||RT(RP)
Rf/Av+ Rs/Rs+RT Rf/Av+ 1/Av+
Table Noise Terms Contributing Non-inverting Configuration point possible confusion that, although trying develop total noise power input amp, what relation does this have input voltage noise term that already appears model, described OA-12, noise model attempts lump internal noise sources actual amplifier into equivalent input noise voltage non-inverting input input noise currents. intent provide means predicting noise performance over wide range external operating conditions. shown analysis model Figure associated only with internal characteristics itself. total amplifier output noise includes this contributions from other noise sources shown there. Having gotten expression total output noise voltage, equivalent input noise voltage derived simply dividing voltage gain amp. This step input referring each noise source performed each term Table form expression need only squared product each noise source associated gain, shown Table
iniRp
4kTRS
define
4kTRS
4kTRpR
4kTRp
Figure Input Noise Power Calculation expression other noise voltages currents referred non-inverting input summed voltages squared. noise terms inverting side amplifier, best find each term's gain output voltage, then reflect back non-inverting input dividing non-inverting voltage gain amplifier. this point, since dealing with linear voltage gains, define this gain Rf/Rg. Table tabulates each individual voltage current noise "gain" input Figure Note that current noise terms have impedance their gain expression yield voltage noise terms input amplifier.
4kTR 4kTR 4kTR
This will simplify 4kTRp 4kTR (iniRp
noise terms input terminating combined feedback resistor noise term gain setting resistor noise terms
expression non-inverting noise Figure (N+) derived substituting Equations back into Equation
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4kTR 4kTR 10log 4kTR
This will further simplify
10log 4kTR 4kTR Rp2A
arbitrary input termination resister possible contributing terms (even though some prove negligible). simplified Equation assumes input terminating resister neglects noise contribution amps non-inverting input bias current noise feedback gain setting resister noises. expression found CLC205 CLC206 data sheets include arbitrary still neglected noise contribution Having labored through this clarify where some earlier noise figure expressions published National came from, step most useful form noise figure expression where Doing this Equation yields:
4kTR 10log
Simplifying these terms:
Recall that
then
4kTR
With
Putting these simplifications back into Equation yields:
This expression non-inverting noise Figure closely matches equation shown CLC205 CLC206 data sheets. Equation differs only some variable names addition term noise, which CLC205 CLC206 equations neglected. were driving signal directly into non-inverting input with input termination neglect noise contribution from ini, Equation will reduce
This probably most useful formulation noise figure non-inverting amp. arises from signal attenuation take getting from source input using external, noisy, resister matched (e.g. RT). Note that noise figure will decrease signal gain increased numerator terms showing their denominators. Also note that current feedback amplifiers, feedback resister fixed satisfy amplifier's loop gain phase margin requirements (application note OA-13 discusses relaxing this requirement somewhat). Hence, latter terms Equation numerator indeed decrease with increasing gain. were particularly constrained value, with voltage feedback amplifiers, Rf/Av+ term appearing last terms Equation would probably make more sense replaced Rf||Rg term. Inverting Noise Figure this case, discussion will simplified constraining input impedance equal Figure shows circuit analysis with contributing noise sources: been retained non-inverting input, along with noise voltage source, complete generality. Rg's noise appears voltage source instead current noise term used non-inverting analysis. Again, developing noise figure expression inverting amplifier configuration simply matter resolving placing these expressions into Equation Knowing that input impedance matched noise voltage attributed will delivered input port amplifier. This yields (voltage) input.
10log 4kTR
This expression matches that appearing several National hybrid amplifier data sheets (e.g. CLC200, CLC201, CLC103, CLC203, CLC220 CLC221 where term been replaced Equation consider only spot noise figure. Equation above most general expression amp's non-inverting spot noise figure, considering
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Where:
Constrain
Inverting Gain
Table Noise Terms Contributing Inverting Configuration noise terms non-inverting side have gain inverting input. increases, this gain drops which contributes lower noise figure achievable using inverting amplifier configuration. Again, expression noise (voltage) input obtained taking squared product each noise source associated gain shown Table (enA (imR 4kTR 4kTR 4kTRm 4kTRg Combining noise powers attributed input matching network will allow considerable simplification final inverting noise figure expression. Substituting with expression shown part Table expanding squared gain expressions
4kTR 4kTR
Figure Inverting Noise Figure Analysis 4kTRS kTRS
Table shows each individual noise terms, except with each term's "gain" inverting input. noise terms non-inverting input have gain inverting input. This represents non-inverting gain output divided inverting gain back inverting input. resistor noise terms taken have voltage gain inverting input defined simply resistor divider networks simplified with constraint that yield Rg||RM perhaps, easiest confirm gain equations Rg's RM's noise computing current those voltages generate into taking this current output multiplying then reflecting back inverting input dividing Rf/Rg. Doing this then substituting shown Table will (with some manipulation) yield simple gain expressions found Table inverting noise current noise voltage taken output then reflected back inverting input dividing inverting gain.
Voltage Gain Input
Noise Source
Non-inverting input voltage noise Non-inverting input current noise Non-inverting input source resistor noise Inverting input current noise Inverting input impedance matching resistor noise Gain setting resistor voltage noise Feedback resistor voltage noise
Value
4kT/RT 4kT/RM 4kT/Rg 4kT/Rf
RTAT
Putting this back into inverting expression grouping non-inverting input noise terms together yields:
4kTR (iniR 4kTR kTRS
Putting expressions inverting (Equations back into noise figure expression (Equation recognizing that dividing each term will yield respectively, shows that kTRs term that arose from resistor noises will collapse simple term, including kTRs (very reminiscent appearing
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expression). difference that this part expression includes contribution both while non-inverting equation kept noise part equivalent input noise. This arises since constrained input impedance matching requirement can, therefore, taken into this simplified form. inverting noise figure then:
4kTR (en2 (iniR 4kTR 10log kTRS
Figure Noise Figure Gain CLC404 Dynamic Range Calculation Having developed limits dynamic range commonly used describing amplifiers they apply amps, possible combine them into single dynamic range number. usable dynamic range typically described terms difference between minimum detectable signal amplifier output either -1dB compression output power that would bring order spurious this minimally detectable level. described reference (page 175) minimally detectable signal output amplifier POMDS kTGA(NF)BX where: Noise power delivered matched input Power gain Noise Figure Noise bandwidth Additional margin above noise floor detectability; typically 3dBm
compare non-inverting noise figure expression (Equation inverting expressions (Equation 10), note that noise terms non-inverting input side have gain non-inverting configuration gain inverting. Also note that term associated with feedback resistor noise divided simply non-inverting case. This arises because also includes noise non-inverting expression. However, divided (Av-)2 inverting case. This arises from noise term being considered part input termination. this case, RM's noise, appears 2*(2*Rg/Rs part noise figure expression. Note that this collapses simply equal when similar case. inverting gain, non-inverting input noise terms have larger impact inverting configuration than equivalent non-inverting gain, yielding higher noise figure. increases, however, non-inverting noise terms will attenuated going inverting signal input reference point, yielding lower inverting noise figure than equivalent gain non-inverting configuration. Figure compares noise figures over gain non-inverting inverting configurations using CLC404. this comparison, assumed fixed 500, non-inverting case inverting case. With these constraints, will desired gain requirement that Rg||RM inverting mode. assumed throughout. inverting noise figure plot simply stops point where since higher gains possible (with fixed while retaining input impedance matching requirement. Also note that gains shown x-axis matched load, while voltage gains used noise figure calculations linear voltage gains output pin.
Note that kTGA(NF) term solves yield spot output noise power. Substituting recalling that noise power delivered input matching resistor N0GA Adding 10*log(B) will then show integrated noise floor output amplifier. important remember that this bandwidth need bandwidth amplifier itself. advantageous bandlimit response narrowly possible some point after amplifier immediately prior desired signal extraction. this later bandlimiting bandwidth that would used equation determining minimum detectable signal.
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example, consider CLC404 circuit used throughout this discussion with post-filter yield bandwidth interest from 10MHz 20MHz. noninverting, gain 9.54dB topology would yield minimum detectable power level output:
P0MDS 10log (kT) 10log 10log (10MHz) -174dBm 9.54dB 18dB 70dB -73.5dBm where noise figure read Figure 10log 10log (1000(4E 21)) -174dBm. .001
spurious free dynamic range -5.8dBm (-73.5dBm) 67.7dB additional check this spurious free dynamic range recall that total output power equal power 2-tone condition (that will generate spurious level minimum detectable signal)is actually voltage envelope that twice individual signals, 6dBm higher power. This would imply 0dBm total output power when spurious just rising above noise floor. This well below dynamic range -1dB compression limit. Another interpret order spurious plot Figure compute absolute spurious power level output power swept higher simply compare that minimum detectable signal power output. absolute spurious power derived from data Figure simply x-axis value minus y-axis value, (PO-(PO-PS))=PS. When measured spurious free range region slope (24dBm 20MHz line), remaining constant output power increases. Using actual measured data, opposed intercept, become more appropriate compare spurious power noise floor when spurious level begins level become constant (for part like CLC404) just below minimum detectable signal. example, minimum detectable signal were actually -68dBm example considered earlier, order spurious would equal this level 4dBm output power instead -4dBm level that would predicted from equation used above with power estimate 28dBm intercept. Increasing amplifier gain would raise output noise floor -67.5 take advantage this improved spurious performance higher output powers. Doing this would actually yield 72dB spurious free dynamic range 68dB calculated earlier. primary determinants dynamic range noise power bandwidth, noise figure, -1dB compression, 2tone, order spurious. maximize dynamic range, following steps taken Limit noise power bandwidth after amplifier much possible. reduce noise figure, amplifier high gain possible consistent with bandwidth limitations and/or amplifier high inverting gains. Alternatively, using transformer coupled non-inverting amplifier configuration described National application note OA-14 typically reduce noise figure level. -1dB compression limits inadequate, higher supply voltage amplifier (such hybrid amplifiers offered National), increase power supply voltage above recommended
Having determined minimally detectable signal, output, maximum output signal some constraint will determine dynamic range. Typically, simple dynamic range specification uses -1dB compression power maximum output power. From earlier discussion -1dB compression, know that actual output power fundamental frequency 1dBm less than reported -1dB compression point, and, that true achievable sinusoidal power approximately 2.1dBm less than this increase power showing fundamental when output approaching square wave. With these considerations, would seem more realistic maximum output power 3dBm less than measured -1dB compression power. Going Figure subtracting 3dBm from measured -1dB compression maximum operating frequency will yield maximum useable output power matched, load 14.5dBm. Subtracting minimum detectable signal output from this shows 14.5 (-73.5) 88dB dynamic range. alternative approach define spurious free dynamic range. This approach sets maximum output power yield order spurious level equal minimum detectable signal. this point, amplifier generated spurious just equalling what detected from noise floor consideration. From Figure order spurious levels are: Setting this equal minimum detectable signal solving
-174dBm 10log 10log -174dBm 10log 10log 2(IM3)
Putting previously develop minimum detectable signal pulling 20MHz intercept from Figure shows maximum spurious free output power -73.5 -5.8
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value. National's voltage monolithic amplifier's specify maximum voltage across supply pins volts. Increasing supplies from using single supply single supply circuits described earlier) will typically increase maximum useable output power 2dBm. sure consider actual spurious performance intercept characteristic followed. Increasing supply current possible) increasing load impedance dramatically drop order distortion terms. Recall that feedback network remains upper limit output loading. Reference describes additional technique loop gain shaping that used further improve distortion performance. Conclusions High speed current feedback amplifier's offer considerable performance advantages when used applications. flexible gain impedance capability used designers benefit tailoring amplifier specific requirement. Last minute gain changes accommodated with resistor value changes opposed requiring amplifier. Exceptional VSWR reverse isolation easily attainable using wideband amps. Although somewhat different, dynamic range calculated, measured, compared between amps more typical amplifiers. most significant advantages wideband current feedback amplifiers order spurious level their relatively quiescent power dissipation. Most National's monolithic amplifier's dissipate less
than 150mW while delivering excess 40dBm intercepts below 10MHz. primary drawback closed loop amps their rapid rolloff distortion performance loop gain decreases higher frequencies. Another area improvement relatively high noise figures using standard topologies. Using input transformer reduce overall noise figure around (see National application note OA-14). Additional external circuit techniques, along with noise (the CLC425), show potential noise figures 2dB. applications below 100MHz, particularly below 50MHz (when high spurious free dynamic range required), wideband solution probably offer significant performance, power dissipation, price advantages over more typical fixed gain amplifiers. Appendix summarizes comparison between amplifiers wideband amps. References: Hewlett Packard Application Note "S-Parameter Design". "Error Models Systems Measurement", Fitzpatrick, MicroWave Journal, May, 1978. Passive Active Network Analysis Synthesis, Aram Budak; Houghton, Miflin, 1974. "Pushing Quiescent Power Amps Greater than 55dBm 2-Tone Intercept, Automated, Very Wide Dynamic Range System Measure these Exceptionally Spurious Levels.", Michael Steffes, National Application Note, 0A-22. Microwave Transistor Amplifiers: Analysis Design, Guillermo Gonzalez; Prentice Hall, Inc., 1984.
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Appendix Amplifier Comparison Table
Parameter Gain Amplifiers Almost always fixed gain. National Semiconductor Amps Easily adjustable over very wide range. capability. Upper limit around 100MHz match flatness specs. tuned much better match through 100MHz than amps. Much better isolation possible Degrades high frequencies. Better non-inverting than inverting. Varies with gain setting. Higher gains better bottoming about 12dB typical amp. Circuit improved Very good intercepts quiescent power. Strong frequency dependent-degrading rapidly high frequency. improved frequencies. App. Note OA-22. Requires more head room availble output power. Drops rapidly with frequency slew rate -1dB order related. Bi-polar supplies. Almost single supply. Much lower lower quiescent currents PoCapability.
Bandwidth
Limited capacity 1MHz. very high frequency. Generally, decade range. Typically 1.5:1.
VSWR
Reverse Isolation
30dB considered good. frequency dependent.
Noise Figure
very low. typical.
Order
Moderate levels, needs high excellent numbers. Relatively frequency independent.
-1dB Compression
Good levels voltage supplies. Relatively frequency independent. -1dB intercept order related. Usually single polarity supply. High quiescent current PoCapability.
Supply Current
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Appendix Harmonic Intermodulation Terms Order Polynomial Transfer Function
input signal that sinusoidal signals Acos2f1t Bcos2f1t: Processed through order polynomial transfer function K1Vi K2Vi2 K3Vi3 K4Vi4 K5Vi5 yields following frequencies coefficients:
Frequency terms coefficients order ascending frequency
Frequency
Coefficient
Order Intermod
Order Intermod
Order Intermod
coefficient
Lower Test Tone
Upper Test Tone
Order Intermod
Order Intermod
Order Intermod
2f1)
Harmonic
Order Intermod
2f2)
Harmonic
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Appendix (Continued) Harmonic Intermodulation Terms Order Polynomial Transfer Function
Frequency
Coefficient
Order Intermod
Order Intermod
3f1)
Harmonic
Coefficient
Higher Order Intermod
Higher Order Intermod
3f2)
Harmonic
K4A4 Coefficient K5A5 Coefficient
Order Intermod
4f1)
Harmonic
Order Intermod
Order Intermod
4f2)
Harmonic
5f1)
Harmonic
Order Intermod
Order Intermod
5f2)
Harmonic
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