DS3886A DS3886A 9-Bit Latching Data Transceiver General Desc

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DS3886A DS3886A 9-Bit Latching Data Transceiver General Desc

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DS3886A 9-Bit Latching Data Transceiver
DS3886A
DS3886A 9-Bit Latching Data Transceiver
General Description
DS3886A higher speed, lower power, compatible version DS3886. DS3886A series transceivers designed specifically implementation high performance Futurebus+ proprietary interfaces. DS3886A 9-Bit Latching Data Transceiver designed conform IEEE 1194.1 (Backplane Transceiver Logic-BTL) specified IEEE 896.2 Futurebus+ specification. DS3886A incorporates edge-triggered latch driver path which bypassed during fall-through mode operation transparent latch receiver path. Utilization DS3886A simplifies implementation byte wide address/data with parity lines also used Futurebus+ status, command lines. DS3886A driver output configuration open collector which allows Wired-OR connection bus. Each driver output incorporates Schottky diode series with it's collector isolate transistor output capacitance from bus, thus reducing loading inactive state. combined output capacitance driver output receiver input less than driver also high sink current capability comply with loading requirements defined within IEEE 1194.1 specification. Backplane Transceiver Logic (BTL) signaling standard that invented first introduced National Semiconductor, then developed IEEE enhance performance backplane buses. compatible transceivers feature output capacitance drivers minimize loading, nominal signal swing reduced power consumption receivers with precision thresholds maximum noise immunity. standard eliminates settling time delays that severely limit performance, thus provide significantly higher transfer rates. backplane intended operated with termination resistors (selected match impedance) connected 2.1V both ends. voltage typically Separate ground pins provided each output minimize induced ground noise during simultaneous switching. unique driver circuitry meets maximum slew rate V/ns which allows controlled rise fall times reduce noise coupling adjacent lines. transceiver's high impedance control driver inputs fully compatible. receiver high speed comparator that utilizes Bandgap reference precision threshold control, allowing maximum noise immunity signaling level. Separate QVCC QGND pins provided minimize effects high current switching noise. output TRI-STATE fully compatible. DS3886A supports live insertion defined IEEE 896.2 through (Live Insertion) pin. implement live insertion should connected live insertion
TRI-STATE registered trademark National Semiconductor Corporation.
power connector. this function supported, must tied pin. DS3886A also provides glitch free power up/down protection during power sequencing. DS3886A types power connections addition pin. They Logic (VCC) Quiet (QVCC). There Logic pins DS3886A that provide supply voltage logic control circuitry. Multiple connections provided reduce effects package inductance thereby minimize switching noise. these pins common internal device, voltage delta should never exist between these pins voltage difference between QVCC should never exceed 0.5V because circuitry. When (Chip Disable) high, high impedance state high. transmit data signal high. When RBYP high, positive edge triggered flip-flop transparent mode. When RBYP low, positive edge ACLK signal clocks data. addition, circuitry between pins other pins except I/O's pins requires that voltage these pins should exceed voltage +0.5V. There three different types ground pins DS3886A; logic ground (GND), grounds (B0GND-B8GND) Bandgap reference ground (QGND). these ground reference pins isolated within chip minimize effects high current switching transients. optimum performance QGND should returned connector through quiet channel that does carry transient switching current. B0GND-B8GND should connected nearest backplane ground with shortest possible path. Since many different grounding schemes could implemented circuitry exists DS3886A, important note that voltage difference between ground pins, QGND, B0GND-B8GND should exceed 0.5V including power up/down sequencing. Additional transceivers included Futurebus+ family are; DS3884A Handshake Transceiver featuring selectable Wired-OR glitch filtering DS3885 Arbitration Transceiver with arbitration competition logic /ABP* signal lines, DS3883A 9-Bit Data Transceiver. DS3875 Arbitration Controller included Futurebus+ family supports required optional modes Futurebus+ arbitration protocol. designed used conjunction with DS3884A DS3885 transceivers. Logical Interface Futurebus+ Engine (LIFE) high performance Futurebus+ Protocol Controller designed IEEE 896.1 1991. LIFE will handle handshaking signals between Futurebus+ local interface. Protocol Controller supports Futurebus+ compelled
1997 National Semiconductor Corporation
DS011458
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PrintDate=1997/04/04 PrintTime=11:57:31 7428 ds011458 Rev.
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General Description
(Continued)
mode data transfer both master slave. Protocol Controller configured operate compliance IEEE 896.2 Profile mode. LIFE incorporates controller 64-bit FIFO's fast queuing. DS3886A offered 44-pin PLCC, 44-pin PQFP, 48-pin PQFP high density package styles. 48-pin PQFP space saving package that requires less space than 44-pin PQFP package.
Features
Fast propagation delay (3ns typ) 9-BIT Latched Transceiver Driver incorporates edge triggered latches Receiver incorporates transparent latches Meets IEEE 1194.1 Standard Backplane Transceiver Logic (BTL)
Supports Live Insertion Glitch free Power-up/down protection Typically less than Bus-port capacitance Bus-port voltage swing (typically Exceeds testing (Human Body Model) Open collector Bus-port outputs allows Wired-OR connection Controlled rise fall time reduce noise coupling adjacent lines compatible Driver Control inputs Built Bandgap reference with separate QVCC QGND pins precise receiver thresholds Individual Bus-port ground pins Product offered PLCC PQFP package styles PQFP requires less space than PQFP Tight skew (0.5 typical)
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Connection Diagrams
DS011458-1
DS011458-2
DS011458-16
Note: Connect
Order Number DS3886AV, DS3886AVB DS3886AVF Package Number V44A, VBH48A VF44B
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Absolute Maximum Ratings
(Notes
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage Control Input Voltage Driver Input Receiver Output Receiver Input Current Termination Voltage Power Dissipation 25°C PLCC (V44A) PQFP (VF44B) PQFP (VBH48A) 6.5V 6.5V 5.5V 2.4V 2.5W 1.3W 1.59W (Notes
Derate PLCC Package (V44A) Derate PQFP Package (VF44B) Derate PQFP Package (VBH48A) Storage Temperature Range Lead Temperature (Soldering, sec.)
mW/°C 11.1 mW/°C 12.8 mW/°C -65°C +150°C 260°C
Recommended Operating Conditions
Supply Voltage (VCC) Termination Voltage (VT) Operating Free Temperature 2.06 2.14 Units
Electrical Characteristics
+70°C, Symbol VOLB IOFF Parameter Minimum Input High Voltage Maximum Input Voltage Input Leakage Current Input High Current Input Current Input Current Input Diode Clamp Voltage Output Voltage (Note Output Current Output High Current Output Current-Chip Disabled Output High Current-Chip Disabled VCLP VCLN Receiver Input Threshold Positive Clamp Voltage Negative Clamp Voltage Voltage Output High Voltage Output TRI-STATE Leakage Current
Conditions
Units
DRIVER CONTROL INPUT (CD, ACLK, RBYP) 5.5V 2.4V, 0.5V, 2.4V 0.5V, 0.5V, 2.4V Port, 0.5V, 0.5V 2.4V, RBYp 2.4V ICLAMP 2.4V, 0.5V, 0.5V, 2.4V, 0.75V, 0.5V 0.5V, 2.4V, 2.1V, 0.5V 0.5V, 2.4V, 0.75V 0.5V, 2.4V, 2.1V 0.5V ICLAMP 1.1V, -2mA, 0.5V 0.5V, 2.1V, 0.5V, 2.4V, 2.4V, 0.75V 0.5V, 2.4V, 0.75V 1.1V, 2.1V, 0.5V, 0.5V, 0.5V (Note 1.47 1.55 0.75 -100 -1.2 -200 1.62 -1.2 0.35 0.30 -100
DRIVER OUTPUT/RECEIVER INPUT (Bn)
RECEIVER OUTPUT (An)
Output Short Circuit Current
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Electrical Characteristics
+70°C, Symbol SUPPLY CURRENT ICCT ICCT-Power Supply Current High Input (VIN 2.1V) Supply Current: VCC, QVCC Live Insertion Current Parameter
(Notes (Continued)
Conditions 3.4V, 0.5V ACLK RBYP 3.4V 0.5V, 2.1V, 0.5V ACLK RBYP 3.4V ACLK 0.5V RBYB 2.4V, ACLK 0.5V
Units
Note "Absolute maximum ratings" those beyond which safety device cannot guaranteed. They meant imply that device should operated these limits. table "Electrical Characteristics" provides conditions actual device operation. Note input and/or output pins shall exceed plus 0.5V shall exceed absolute maximum rating anytime, including power-up power down. This prevents structure from being damaged excessive currents flowing from input and/or output pins QVCC VCC. There diode between each input and/or output which forward biased when incorrect sequencing applied. Alternatively, current limiting resistor used when pulling-up inputs prevent damage. current into input/output shall greater than Exception, pins have power sequencing requirements with respect QVCC. Furthermore, difference between QVCC should never greater than 0.5V time including power-up. Note currents into device pins positive; currents device pins negative. voltages referenced device ground unless otherwise specified. typical values specified under these conditions: 25°C, unless otherwise stated. Note Only output should shorted time, duration short should exceed second. Note Referenced appropriate signal ground. exceed maximum power dissipation package.
Electrical Characteristics (Note This table applies DS3886AVF PQFP) DS3886AV (PLCC) only.
+70°C, Symbol DRIVER tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tskew Fall-through mode ACLK Latch mode Enable Time Disable Time Enable Time Disable Time Transition Time-Rise/Fall Slew Rate calculated from 1.3V 1.8V ACLK tPHL ACLK ACLK ACLK Pulse Width Propagation Delay Same Package Same Package Set-up Time Hold Time RBYP (Figure Figure (Note (Note (Note RBYP RBYP RBYP Propagation Delay Propagation Delay RBYP (Figure Figure RBYP (Figure Figure (Figure Figure (Figure Figure 11), RBYP (Figure Figure 11), RBYP RBYP (Figure Figure (Note 0.85 V/ns Parameter Conditions Units
DRIVER TIMING REQUIREMENTS (Figure
RECEIVER
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Electrical Characteristics (Note This table applies DS3886AVF PQFP) DS3886AV (PLCC) only. (Continued)
+70°C, Symbol RECEIVER tPLH tPHL tPLH tPLZ tPZL tPHZ tPZH tPLZ tPZL tPHZ tPZH tskew Coutput Pulse Width Capacitance Noise Rejection Bypass Mode Latch Mode Disable Time Enable Time Disable Time Enable Time Disable Time Enable Time Disable Time Enable Time Same Package Same Package Set-up Time Hold Time Propagation Delay (Figure Figure (Figure Figure 3.0V 2.1V, (Figure Figure 3.0V 1.1V, (Figure Figure 3.0V, 2.1V (Figure Figure 3.0V 1.1V, (Figure Figure (Note (Note (Note (Note Parameter Conditions Units
RECEIVER TIMING REQUIREMENTS (Figure
PARAMETERS TESTED
Electrical Characteristics (Note This table applies DS3886AVB PQFP) only.
+70°C, Symbol DRIVER tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tskew Fall-through mode ACLK Latch mode Enable Time Disable Time Enable Time Disable Time Transition Time-Rise/Fall Slew Rate calculated from 1.3V 1.8V ACLK Same Package Same Package Propagation Delay Propagation Delay RBYP (Figure Figure RBYP (Figure Figure (Figure Figure (Figure Figure 11), RBYP (Figure Figure 11), RBYP RBYP (Figure Figure (Note RBYP (Figure Figure (Note (Note (Note 15.5 0.85 V/ns Parameter Conditions Units
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PrintDate=1997/04/04 PrintTime=11:57:43 7428 ds011458 Rev.
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Electrical Characteristics (Note This table applies DS3886AVB PQFP) only.
+70°C, Symbol tPHL tPLH tPHL tPLH tPLZ tPZL tPHZ tPZH tPLZ tPZL tPHZ tPZH tskew Coutput Pulse Width Capacitance Noise Rejection ACLK ACLK ACLK Pulse Width Bypass Mode Latch Mode Disable Time Enable Time Disable Time Enable Time Disable Time Enable Time Disable Time Enable Time Same Package Same Package Set-up Time Hold Time Propagation Delay Propagation Delay Parameter Set-up Time Hold Time Conditions RBYP RBYP RBYP (Figure Figure (Figure Figure 3.0V 2.1V, (Figure Figure 3.0V 1.1V, (Figure Figure 3.0V, 2.1V (Figure Figure 3.0V 1.1V, (Figure Figure (Note (Note (Note (Note
(Continued)
Units
DRIVER TIMING REQUIREMENTS (Figure
RECEIVER
RECEIVER TIMING REQUIREMENTS (Figure
PARAMETERS TESTED
Note Input waveforms shall have rise fall time Note tskew absolute value defined differences seen propagation delay between drivers same package with identical load conditions. Note parameter tested using techniques described P1194.0 Backplane Design Guide. Note This parameter tested during device characterization. measurements revealed that part will typically reject pulse width. Note Futurebus+ transceivers required limit signal rise fall times faster than V/ns, measured between 1.3V 1.8V (approximately nominal voltage swing). rise fall times measured with transceiver loading equivalent 12.5 tied +2.1 VDC.
Description
Name A0-A8 ACLK B0-B8 B0GND-B8GND Number Pins Input/ Output TRI-STATE receiver output driver input Clock input latch receiver input driver output Driver output ground reduces ground bounce high current switching driver outputs. (Note Chip Disable Ground reference switching circuits.(Note Latch Enable Description
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Description
Name QGND QVCC RBYP
(Continued) Input/ Output Power supply live insertion. Boards that require live insertion should connect live insertion connector. (Note Connect Ground reference receiver input bandgap reference non-switching circuits. (Note supply bandgap reference non-switching circuits. (Note Register bypass enable Transmit/Receive Transmit Receive supply switching circuits. (Note Description
Number Pins
Note multiplicity grounds reduces effective inductance bonding wires leads, which then reduces noise caused transients ground path. various ground pins tied together provided that external ground iductance (i.e., ground plane with power pins many signal pins connected backplane ground). external ground floats considerably during transients, precautionary steps should taken prevent QGND from moving with reference backplane ground. receiver threshold should have same ground reference signal coming from backplane. voltage offset between their grounds will degrade noise margin. Note same considerations ground used reducing lead inductance (see (Note 10)). QVCC should tied together externally. live insertion supported, tied together with QVCC VCC.
Truth Table
RBYP
High logic state High impedance state state High state high transition change from previous state change from previous state high state nominally 2.1V 1.0V, respectively. high state nominally 2.4V 0.5V, respectively.
Package Thermal Characteristics
Linear Feet Minute Flow (LFPM) 44-Pin PQFP (°C/W) 44-Pin PLCC 48-Pin PQFP
Note above values typical values different from Absolute Maximum Rating values, which include guardbands.
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PrintDate=1997/04/04 PrintTime=11:57:48 7428 ds011458 Rev.
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Logic Diagram
DS011458-3
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Typical Application
DS011458-4
Test Circuits Timing Waveforms
DS011458-5
FIGURE Driver Propagation Delay Set-up
DS011458-8
FIGURE Driver: ACLK
DS011458-6
FIGURE Driver:
DS011458-9
Switch Position
tPLH
DS011458-7
tPHL close
open
FIGURE Receiver Propagation Delay Set-up
FIGURE Driver:
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Test Circuits Timing Waveforms (Continued)
DS011458-12
Switch Position
DS011458-10
tPZL tPLZ close open
tPZH tPHZ open close
FIGURE Receiver:
FIGURE Receiver: Enable/Disable Set-up
DS011458-11
FIGURE Receiver Enable/Disable Set-up FIGURE Receiver: (tPHZ tPZH only)
DS011458-13
DS011458-14
FIGURE
Book Extract
DS011458-15
FIGURE (tPHLand tPLH only), (tPZLand tPLZ only)
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THIS PAGE IGNORED DATABOOK
PrintDate=1997/04/04 PrintTime=11:57:52 7428 ds011458 Rev.
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Physical Dimensions
inches (millimeters)
Note: dimensions inches (millimeters) 44-Lead Molded Plastic Leaded Chip Carrier Order Number DS3886AV Package Number V44A
Note: dimensions millimeters 48-Lead Molded Plastic Quad Flat Package JEDEC Order Number DS3886AVB Package Number VBH48A
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PrintDate=1997/04/04 PrintTime=11:57:53 7428 ds011458 Rev.
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DS3886A 9-Bit Latching Data Transceiver
Physical Dimensions
inches (millimeters) (Continued)
Note: dimensions millimeters 44-Lead Plastic Quad Flatpak Order Number DS3886AVF Package Number VF44B
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION. used herein: critical component component life support Life support devices systems devices sysdevice system whose failure perform reatems which, intended surgical implant into sonably expected cause failure life support body, support sustain life, whose faildevice system, affect safety effectiveness. perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
National Semiconductor Corporation 1111 West Bardin Road Arlington, 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 National Semiconductor Europe Fax: (+49) 0-180-530 Email: cnjwge@tevm2.nsc.com Deutsch Tel: (+49) 0-180-530 English Tel: (+49) 0-180-532 Tel: (+49) 0-180-532 Italiano Tel: (+49) 0-180-534 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, Canton Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408
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National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.
PrintDate=1997/04/04 PrintTime=11:57:53 7428 ds011458 Rev.
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DS3886A DS3886A 9-Bit Latching Data Transceiver General Desc

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