JEDEC's ``Revolutionary'' SRAM Pinout Standard Helps Combat Noise High

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JEDEC's ``Revolutionary'' SRAM Pinout Standard Helps Combat Noise High

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JEDEC's ``Revolutionary'' SRAM Pinout Standard Helps Combat Noise High Speed Systems
JEDEC's ``Revolutionary'' SRAM Pinout Standard Helps Combat Noise High Speed Systems
INTRODUCTION today's high-performance systems SRAM speed critical issue More often than system speed limited fastest SRAM cycle time available Using SRAMs very high speeds introduces critical design issue avoid noise system Noise defined electrical signal present circuit other than desired signal Serious design considerations both from system designer semiconductor manufacturer must given reducing system noise System designers must well aware noise problems created improper transmission line termination inadequate power supply decoupling component level semiconductor designers help reduce system noise minimizing power ground lead inductance their SRAM packages controlling rate change output current Specifically SRAM manufacturers offer system designers higher speed reduced noise devices providing devices that adhere JEDEC ``Revolutionary'' pinout standards National Semiconductor's Megabit BiCMOS SRAM customers gain best speed noise performance available because National's JEDEC ``Revolutionary'' pinout standard because other design features that manage noise SYSTEM NOISE SOURCES With very fast SRAMS Megabit densities) system design factors controlling noise decoupling capacitors matching termination impedance These especially important very short rise fall times associated with fast SRAMS
National Semiconductor Application Note Sean Pitonak Eric Hall June 1990
Current spikes from outputs switching major cause noise power ground Supply decoupling influenced many factors including printed circuit board power supply layout types values decoupling capacitor best given application determined experimentally observing supply noise operation general guideline systems designer should plan decoupling capacitors distributed among memories Circuit board space least capacitor SRAM should allowed Subsequent experimentation indicate that capacitor sites need populated adequate supply noise suppression capacitors chosen should selected impedance high frequencies across range most effective decoupling inductance from SRAM device power supply leads decoupling capacitors should kept minimum Ideally capacitors could placed next supply pins memory package possibly underneath memory package between supply pins Decoupling capacitors also placed back side circuit board directly behind each memory package high impedance unterminated line acts like antenna radiate receive electromagnetic interference (EMI) This result ringing crosstalk various other noise associated problems more transmission lines more antennas pick radiate noise best reduce ensure that properly terminated into low-impedance load Ideally termination resistor should equal characteristic impedance line This will provide best incident wave switching least amount signal reflection
11037
FIGURE SRAM Practical Output Delays Package Lead Inductance VOUT VGND
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C1995 National Semiconductor Corporation
11037
RRD-B30M75 Printed
When reflected voltage arrives back driving transistor (due unmatched improperly terminated line) impedance transistor will determine response neither load termination source impedance matches characteristic impedance transmission line multiple reflections ringing will occur until voltage reflections damped more detailed discussion transmission line theory found National's F100K Logic Data Book Design Guide information contained this publication equally applicable high speed systems GROUND BOUNCE Very fast SRAMs with wide data busses bits more) further complicate noise issue Having many data outputs leaves open possibility that many output drivers switch same time 128K SRAM's outputs switched from ``1's'' ``0's'' same time output drivers would place large demand current single ground conductor (the lead frame chip bond wire) that brings ground chip Such abrupt transition could temporarily raise ground potential chip causing what commonly referred ground bounce This change ground voltage supply voltage outputs switched from ``0's'' ``1's'') mainly voltage drop (DVGND) over package lead bondwire inductance This voltage drop given where total current through output drivers most cases this equal total output load charging discharging current Theoretically charge necessary switch output current given DVGND DVOUT DiDt
Where DVOUT voltage swing output maximize output switching speed static should utilize output buffer that ramps current constant (equal tolerable DVGND maximum then ramp down same constant Combining equations yields relationship between discharging charging time (Dt) output capacitive load voltage drop DVGND DVOUT DVGND where theoretical minimum output switching time that achieved Assuming certain values DVOUT DVGND Figure shows speed gains that achieved minimizing ground inductance SRAM package Note that configuration inherently slower capacitive load (CL) High speed SRAM manufacturers provide their customers with higher speed reduced noise devices careful circuit design minimizing power ground lead inductance their SRAM packages ``REVOLUTIONARY'' PINOUT SOLUTION JEDEC (Joint Electron Device Engineering Council industry standard setting body) adopted pinout standard very fast SRAMs below Megabit density) known ``Revolutionary'' pinout standard Revolutionary pinout standard features dual power ground pins center each sides package slower SRAMs (access times greater than JEDEC supports ``Evolutionary'' pinout standard featuring traditional single corner power ground pinout JEDEC Revolutionary Evolutionary pinouts shown Figure 256K SRAMs
JEDEC Standard Revolutionary Pinout Center Power Ground
JEDEC Standard Evolutionary Pinout Corner Power Ground
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FIGURE JEDEC Revolutionary Evolutionary Standard Pinouts 256K SRAMs
Revolutionary pinout reduces lead inductance supply leads several ways First shown Figure Revolutionary pinout much shorter leadframe than possible with Evolutionary pinout package lead inductance Revolutionary pinout approximately when compared that Evolutionary pinout's approximate 6-10 realizing immediate increase switching speed (shown Figure Second having power ground inductors creates inductance that combines parallel reduce inductance from between nH-2 further improving speed-noise tradeoff Third mutual coupling between power ground created reducing effective series inductance Finally double bonding each power ground semiconductor manufacturers reduce effective bondwire inductance even further achieve sub-20 speed next generation Megabit SRAMs simply efficient semi-
conductor manufacturers design their devices with Evolutionary pinout Excessive inductance would cause very fast Evolutionary-style devices extremely noisy ADDITIONAL SYSTEM BENEFITS JEDEC's ``REVOLUTIONARY'' PINOUT STANDARD addition minimizing switching noise Revolutionary pinout standards carry additional system design-in benefits First power data control pins remain fixed pinous migrate upward density from Megabit Megabit density SRAMs Shown Figure JEDEC standard pinouts very fast SRAMs system designer much more easily design around future products higher density memories developed longer causing extensive board redesigns higher costs upgrade
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FIGURE Revolutionary Evolutionary Pinout Lead Frames SRAM SRAM SRAM
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FIGURE JEDEC Standard Revolutionary Pinouts SRAMs
Second today's Evolutionary pinouts have commonality between wide (x1) nibble wide (x4) byte wide (x8) pinouts (Figure This results multiple devices higher costs passed consumer because manufacturer simply cannot same service more than configuration However with today's Revolutionary standards consistent pinout will allow simple options create function organizations same density manufacturer will also able pass this shorter product development cycle (normally organizations available same time frame) terms cost quality manufacturability customer SUMMARY High-speed system designers must very careful when dealing with system noise issues including decouRevolutionary Pinout SRAM)
pling power supplies adequately terminating transmission lines properly Very high-speed SRAM manufacturers must equally careful providing their customers with fastest least noise generating product possible creation JEDEC Revolutionary Pinout Standards made this universally possible National Semiconductor committed helping customers very fast BiCMOS SRAMs gain highest performance possible from their systems introducing very fast Megabit BiCMOS SRAMs with JEDEC Revolutionary Pinout Standard carefully designed onchip output drivers National's customers gain huge performance edge with superior speed-noise optimization
Revolutionary Pinout (256K SRAM)
Revolutionary Pinout (128K SRAM)
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11037 11037
Evolutionary Pinout SRAM)
Evolutionary Pinout (256K SRAM)
Evolutionary Pinout (128K SRAM)
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FIGURE JEDEC Standard Revolutionary Pinouts (Above) Evolutionary Pinouts (Below) 256K 128K SRAMs
JEDEC's ``Revolutionary'' SRAM Pinout Standard Helps Combat Noise High Speed Systems
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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JEDEC's ``Revolutionary'' SRAM Pinout Standard Helps Combat Noise High

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