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Pulse Width Modulation Using MicroControllers embedded control ap
Top Searches for this datasheetPulse Width Modulation Using Pulse Width Modulation Using MicroControllers embedded control applications grows popularity find more width modulated pulse trains Typical applications that Pulse Width Modulation automotive engine control motor speed control display intensity control sound generation DEFINITION Pulse width modulation simply method communicating information device viewed analog signal provided digital form Figure shows typical timing diagram signal duty cycle expressed duration over Toff signal constant duty cycle Toff uniform equal Toff signal duty cycle Duty Cycle Toff National Semiconductor Application Note Alvin Chan Bill Miller Moeckel Hanrahan April 1989 accelerator pedal throttle completely shut idle speed control utilizes stepping motor operate auxilliary fuel valve Figure shows control signals that have generated four phase stepper motor Each signals should have phase quarter cycle from previous applied motor speed control speed motor directly proportional voltage applied 10347 10347 FIGURE Typical Signal TYPICAL APPLICATIONS THAT REQUIRE element automotive engine control system spark ignition distributorless ignition system spark control signals required appear sequence with time delay between each them Typical signals four spark plug system shown Figure generation these signals will explained further timer synchronous output section FIGURE Stepper Motor Control Signals used selectively switch full supply power motor some frequency duty cycle bigger duty cycle more power supplied motor Hence speed higher Motor speed controlled adjusting time signal Figure depicts relationship motor speed applied signal 10347 10347 FIGURE Based Spark Ignition Control Another element automotive system carburetion idle speed control When pressure applied FIGURE Using Control Motor Speed same manipulation also applies controlling intensity light emitting diodes brightness varied using different duty cycles Sound synthesis achieved uniting process sinusoidal signal generation envelope generation sinusoidal signal generated variety methods common technique Walsh functions Walsh functions digital equivalent Fourier Series They essentially pulse signals with varying duty cycles individual Walsh components generated microcontroller combined with proper weighting factors form sinusoids AN-586 C1995 National Semiconductor Corporation DD10347 RRD-B30M75 Printed Envelope generation done using build converter envelope will give composite sinusoidal signal characteristic sharp attack followed slow decay amplitude envelope function altered changing duty cycle input converter This function performed another timer Implementation National Semiconductor's High Performance MicroController provides simple method generating width modulated pulse trains with little software overhead device's on-chip timers through SETTING Outputs Timers through down-counters with associated input registers through value registers loaded automatically into timers when timers underflow Timers through have individual output signals which toggle when timers underflow Interrupts generated time underflow Figure shows structure these timers 10347 Note Only Time Shown identical FIGURE Timers Timers through separated into groups Different procedures registers used groups timers group timers through which dedicated applications They count down constant rate input clock (CKI while enabled other group more versatile timers clock input timers independently selected coming from available prescaled versions clock from external specified DIVBY register Timer also specified clocked underflows from timer appropriate selection DIVBY register pair then form effect single 32-bit counter With timers through maximum frequency that achieved half associated register provides 16-bit resolution duration pulse width timers clock must come from internal source configuring DIVBY register selecting value counter maximum frequency that achieved half minimum frequency half (CKI 131072) 65536 Duty Cycle underflow timers through value corresponding input register automatically reloaded into counters Therefore duty cycle generated without software intervention once timer Listings illustrate generating outputs frequency generated using crystal input clock counter value loaded into registers that underflow occurs output toggles every Generating Duty Cycle without Listing Generate Duty Cycle TITLE SECT TMMODE DIVBY PWMODE PORTP PWMSTR CODE ROM16 0190 018E 0140 0142 0144 0146 0150 0152 STKS initialize stack pointer PWMODE stop timer delay provide cycles make sure timer updated PWMODE clear interrupt pending load with counter value obtain frequency counter should underflow frequency therefore using crystal input timer counter value should load auto-reload register PORTP initial value output PORTP enable toggling underflow PWMODE start timer SBIT SBIT RBIT STOP STOP ENDSECT SECT STACK BASE ENDSECT PWMSTR STKS Duty Cycle (Software Interrupts) Timers through will generate interrupt underflow non-50% duty cycle software involved controlling duty cycle same software duty cycle used timers counting down interrupt from timers interrupt service routine loads other half cycle time into timer register each interrupt from timer user software alternately loads Toff into register result constant duty cycle output Examples programming interrupts shown listings TIMER SYNCHRONOUS OUTPUTS TIMER Timer addition normal output four output pins which independently selected These pins referred collectively ``Timer Synchronous'' outputs Figure shows synchronous output being applied engine control spark ignition signals synchronous outputs derived from timer enabling each sequence spark control signals generated SOFTWARE INTERVENTION Another problem facing designer MicroController based system that software overhead must kept minimum Interrupt latency changing input registers significant portion time which would otherwise available processing sensor data conventional generating non-50% duty cycle discussed earlier That involves software changing value auto-reload register every time timer counts down interrupts timers used generate synchronized offset duty cycle pulses EXCLUSIVE-ORing them non-50% duty cycle generated Listing Generate Duty Cycle TITLE SECT CODE ROM16 0190 018E 00F4 00F2 00E2 0188 0186 STKS initialize stack pointer TMMODE 0x400 stop timer delay provide cycles make sure timer updated TMMODE 0xC00 clear interrupt pending SBIT BFUN port timer output SBIT DIRB output direction port DIVBY 0x200 clock load with counter value obtain frequency counter should underflow frequency therefore using crystal input timer counter value should load auto-reload register RBIT PORTB initialize output value RBIT TMMODE start timer STOP ENDSECT SECT STACK BASE ENDSECT PWMSTR TMMODE DIVBY BFUN DIRB PORTB PWMSTR STOP STKS Listing Generate Non-50% Duty Cycle with Interrupts TITLE NON-50% SECT CODE ROM16 0190 018E 0140 0142 0144 0146 0150 0152 00D0 00D2 STKS initialize stack pointer PWMODE stop timer delay provide cycles make sure timer updated PWMODE clear interrupt pending ENIR disable interrupts IRPD clear interrupt pending bits load with counter value obtain frequency with duty cycle using crystal input timer counter value should load auto-reload register with count TCYCLE total cycle time count SBIT PORTP initial value output SBIT PORTP enable toggling underflow ENIR 0x20 enable timer interrupt RBIT PWMODE start timer STOP ENDSECT SECT STACK BASE ENDSECT TCYCLE INTRPT5 total cycle time TMMODE DIVBY PWMODE PORTP ENIR IRPD PWMSTR STOP STKS SECT DATA BASE ENDSECT SECT SUBR INTRPT5 SUBC TCYCLE total cycle time subtract current counter alternate cycle time store auto-reload RETI ENDSECT PWMSTR Listing Generate Non-50% Duty Cycle with Interrupts TITLE NON-50% SECT CODE ROM16 0190 018E 00F4 00F2 00E2 0188 0186 00D0 00D2 STKS initialize stack pointer TMMODE 0x400 stop timer delay provide cycles make sure timer updated TMMODE 0xC00 clear ENIR interrupt pending disable interrupts IRPD clear interrupt pending bits SBIT BFUN port timer output SBIT DIRB output direction port DIVBY 0x200 clock load with counter value obtain frequency using crystal input timer counter value should load auto-reload register with count TCYCLE total cycle time count RBIT PORTB initialize output value ENIR 0x20 enable timer interrupt RBIT TMMODE start timer STOP ENDSECT SECT STACK BASE ENDSECT INTRPT5 TMMODE DIVBY BFUN DIRB PORTB ENIR IRPD PWMSTR STOP STKS TCYCLE SECT DATA BASE total cycle time ENDSECT SECT SUBR ROM16 TCYCLE total cycle time subtract current counter alternate cycle time store auto-reload INTRPT5 SUBC RETI ENDSECT PWMSTR Figure shows result EXCLUSIVE-ORing timers duty cycle depends only phase shift between timer outputs seen that resulting frequency actually twice frequency original timers Therefore order generate result timers must used code shown listing varying initial delay second timer different duty cycles chosen example given digit difference counter value results difference duty cycle 10347 FIGURE Using Timers Generate Duty Cycle Listing Generate Non-50% Duty Cycle without Interrupts TITLE 'NON T5)' SECT CODE ROM16 0190 018E 0140 0142 0144 0146 0150 0152 counter value timers this generates duty cycle STKS PWMODE 0X44 stop PWMODE 0XCC clear pending bits FREQ load FREQ with counter value FREQ calculate delay MULT FREQ store PORTP 0X10 output pins high SBIT PORTP enable toggling SBIT PORTP pins underflow PWMODE 0XFFBB start STOP ENDSECT SECT STACK BASE ENDSECT PWMSTR TMMODE DIVBY PWMODE PORTP FREQ PWMSTR STOP STKS Listing Generate Non-50% Duty Cycle without Interrupts TITLE 'NON T3)' SECT CODE ROM16 00F4 00F2 00E2 0190 018E 0140 0142 0144 0146 0150 0152 0188 0186 018A counter value timers this generates duty cycle STKS TMMODE 0x4400 stop TMMODE 0xCCC8 clear pending bits PORTB 0x10 output pins high DIRB 0xFFFF output PORT BFUN 0x0018 timers DIVBY 0x2200 select clock FREQ load with counter value FREQ FREQ calculate delay MULT FREQ store delay TMMODE 0xBBFF start STOP STOP ENDSECT SECT STACK BASE ENDSECT PWMSTR BFUN DIRB PORTB TMMODE DIVBY PWMODE PORTP FREQ PWMSTR STKS CONCLUSION easily generated 16083 with abundant source timers With crystal maximum frequency that achieved timers themselves once proper setup performed method obtaining non-50% duty cycle without software intervention presented Pulse Width Modulation Using 100586 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness AN-586 National Semiconductor Corporation 2900 Semiconductor Drive 58090 Santa Clara 95052-8090 1(800) 272-9959 (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str D-82256 F4urstenfeldbruck Germany (81-41) 35-0 Telex 527649 (81-41) 35-1 National Semiconductor Japan Sumitomo Chemical Engineering Center Bldg 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture (043) 299-2300 (043) 299-2500 National Semiconductor Hong Kong 13th Floor Straight Block Ocean Centre Canton Tsimshatsui Kowloon Hong Kong (852) 2737-1600 (852) 2736-9960 National Semiconductores Brazil Ltda Deputado Lacorda Franco 120-3A Paulo-SP Brazil 05418-000 (55-11) 212-5066 Telex 391-1131931 NSBR (55-11) 212-1181 National Semiconductor (Australia) Building Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia 558-9999 558-9998 National does assume responsibility circuitry described circuit patent licenses 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