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Reliability Small Outline Surface Mount Packages ABSTRACT space e
Top Searches for this datasheetReliability Small Outline Surface Mount Packages Reliability Small Outline Surface Mount Packages ABSTRACT space efficient packages integrated circuits have been developed These include Plastic Chip Carrier Small Outline packages Design considerations reliability tests package were compared standard plastic Dual-in-Line Package (DIP) package found equal reliability tests performed INTRODUCTION There always been basic trends electronics Make assemblies smaller less costly surface mount packages were developed meet these on-going challenges types Plastic Chip Carrier Small Outline have emerged become dominant styles surface mount plastic packages today these smaller package been subject controversy area reliability RELIABILITY DESIGN with product good designs package ultimately determines good reliability will Because package small affords less plastic protection when compared traditional dualin-line (DIP) package This could lead earlier failures environmental testing compared dual-in-line specifically both made same materials Test data verified this possibility reduce this chance failure re-design package necessary Among items evaluated were Leadframe design leadframe plating leadframe composition semiconductor molding compound passivation National Semiconductor Application Note James Walker October 1986 LEADFRAME DESIGN design leadframe must optimum allow minimum moisture penetration maximum electrical thermal properties design possibility reduce moisture penetration place holes internal lead tips These locking holes provide barrier moisture traveling leads between leadframe-molding compound interface Figure shows results moisture peneNational SO-14 9115 Competitor SO-14 9115 FIGURE Penetration Test DIP-14 9115 SO-14 AN-469 9115 FIGURE C1995 National Semiconductor Corporation 9115 RRD-B30M115 Printed tration test between frames with without locking holes results this bias moisture test clearly show advantage leadframes with ``holes Leadframe plating also crucial package design serves metallurgical interface between bare leadframe functional chip Figure illustrates distance from edge package approximately half times greater dual-in-line package than small outline package This would lead conclude that moisture traveling along leadframe plastic interface would reach earlier small outline package reduce moisture penetration along this interface path length (edge-to-die) must similar increase this distance various plating techniques were evaluated with idea being increase surface area path length which moisture must travel unique plating process developed which rough surface characteristics effectively makes plated surface area comparable typical plated This plating compared Figure where plating process that yields increased surface area traditional plating Thermal Resistance 9115 FIGURE Thermal Resistance Thermal Expansion Glass Transition Temperature 9115-5 FIGURE Plating Process Leadframe composition area where change resulted improved performance Traditionally Alloy nickelsteel composition been used leadframe material dual-in-line many manufacturers years However designing smaller package such thermal properties become more critical factor high strength modified copper alloy composition developed which lowers thermal resistance package over that produced with Alloy material fact Figure shows that (Junction-to-Ambient temperature thermal resistance) lead package using copper leadframe material less than conventional Alloy fourteen (14) lead dual-in-line package Copper also expansion properties which improve thermal cycle characteristics Figure compares linear coefficient thermal expansion (designated Alloy copper semiconductor molding compound Notice that copper more closely matches molding compound expansion rate Less thermal mismatch created copper-epoxy interface compared that Alloy 42-epoxy 9115 FIGURE MATERIAL CONSIDERATIONS Semiconductor molding compounds have also helped improve reliability Small Outline package Reduced contaminants specifically sodium chloride ions have resulted less corrosive species available cause failures bias-temperature-humidity tests addition lower internal stress producing encapsulants reduce failures package warping cracking during assembly process Properties these proprietary high purity stress compounds listed Table TABLE ``High Purity'' Semiconductor Molding Compound Chemical Properties Extracted Conductivity Hydrolizable Chloride passivation always been critical ensuring reliability Most manufacturers silicon-nitride passivation help protect Some polyimide enhance moisture protection Most effective especially small packages ``multi-layer passivation system this system thick layer silicon oxide formed during wafer fabrication This followed second nitride passivation layer These overlapped passivation techniques essentially eliminate defects since unlikely that both masks will have imperfections exactly same spot RELIABILITY TEST RESULTS Upon completion these design improvements described package reliability tests were performed various linear devices Small Outline molded dual-in-line package configuration Package variety included leads test categories conditions evaluated listed Table Tables indicate that reliability performance products assembled National Semiconductor Small Outline package excellent compares favorably reliability performance products assembled standard dual-in-line package Additional detailed reliability information found report entitled ``Reliability Report Package'' (Lit 980045) TABLE Test Descriptions High Temperature Bias Continuous operation rated supply voltage Temperature Humidity Bias Continuous operation rated supply voltage Unbiased 100% humidity Storage without bias minutes cycle liquid min- TABLE Autoclave Humidity-Temperature Storage Package 1357 Time Points 1357 1000 Storage Life Package Time Points 1000 Thermal Shock Liquid-to-Liquid Package Time Points Cycles TABLE Accelerated Bias Moisture Test(A) Equivalent Hours Time Points 2000 1046 4000 6000 8000 Package Autoclave Storage Life Temperature Cycle Thermal Shock High Temperature Bias Test(A) Package Time Points utes immersion seconds transfer time CONCLUSIONS Small Outline package been shown reliable Criteria ensure reliability include enhancement controls (but limited Temperature Cycle C(A) Package Time Points 1000 Cycles 2000 Cycles Leadframe Design Leadframe Plating Composition Leadframe Plating Texture Leadframe Materials Epoxy Molding Compound Passivation Package) parts mounted printed circuit boards using vapor phase soldering results expressed failures units tested Reliability Small Outline Surface Mount Packages 100469 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness AN-469 National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018 National Semiconductor Europe (a49) 0-180-530 Email cnjwge tevm2 Deutsch (a49) 0-180-530 English (a49) 0-180-532 Fran (a49) 0-180-532 Italiano (a49) 0-180-534 National Semiconductor Hong Kong 13th Floor Straight Block Ocean Centre Canton Tsimshatsui Kowloon Hong Kong (852) 2737-1600 (852) 2736-9960 National Semiconductor Japan 81-043-299-2309 81-043-299-2408 National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications Other recent 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