High-Speed-CMOS designs address noise levels National Semiconduct
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High-Speed-CMOS designs address noise levels
High-Speed-CMOS designs address noise levels
National Semiconductor Application Note Larry Wakeman November 1984
maximize benefits high-speed CMOS must cope with environmental interactions component limitations Especially important system noise decoupling both transient steady-state level control
Designs using high-speed-CMOS logic such MM54HC 74HC Series attain characteristics that mark improvements over LS-TTL designs optimize these characteristics however must adopt proper design procedures This article deals with ICs' input-output noise-immunity considerations High-speed CMOS logic essentially digital-IC family that combines (bipolar) CD4000 (CMOS) characteristics Because family's high speed must more aware requirements fast systems than case CD4000B logic Although 54HC 74HC IC's CMOS construction results noise immunity comparable CD4000 family high speed necessitates system-grounding supply-decoding techniques normally used LSTTL system design following sections discuss general usage guidelines system noise susceptibility immunity 54HC 74HC logic's power-supply-noise characteristics Note that unless specific exceptions stated considerations discussed apply also 54HCT 74HCT HC's TTL-compatible subset FOLLOW BASIC GUIDELINES basic rules designing with 54HC 74HC circuits similar those that apply 74LS CD4000B devices First under normal static operating conditions input should exceed below ground normal high-speed systems transients line ringing cause inputs violate this rule momentarily forcing enter SCR-latch-up mode Latch-up results either input- output-protection diodes forward biased because voltages above below ground result IC's internal parasitic shorts ground Figure shows diodes CMOS schematically simplified cross section Thanks some processing refinements latch-up isn't problem with MM54HC 74HC Series There however limitations currents that internal metallization protection diodes handle high-level transients (pulse widths less than inputs above below ground) must limit current IC's internal diode peak Usually simple resistor configured series with input suffices Powering device another important design concern Don't power inputs before both ground con(a)
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FIGURE Essential sometimes evil diodes CMOS-logic easily damaged excessive currents Reversed supplies large input output currents cause diode burnout
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Published Magazine Copyright 1984 Cahners Publishing C1995 National Semiconductor Corporation
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RRD-B30M105 Printed
nected don't plug unplug boards into from powered connectors unless input currents short lived limited manner already described Both conditions forward bias input diodes resulting excessive diode currents Again Figure shows these diodes possible current paths these conditions unavoidable external current limiting prevent damage 54HC 74HC circuits special connectors that apply power before signals Some family members (notably HC4049 have modified input structures survive application power input before supply Floating inputs frequently overlooked problem CMOS inputs have extremely high impedance left open float voltage This situation result logic-function mishaps unnecessary power consumption Moreover open inputs susceptible electrostatic damage should thus unused inputs ground either through resistor directly Finally correct logic results should inputs with rise fall times faster then Slower transition times result logic errors oscillation OBSERVE OUTPUT RULES must observe certain usage rules 54HC 74HC outputs well inputs Output voltages shouldn't exceed supply voltage currents output diodes shouldn't exceed Moreover output drive currents shouldn't exceed standard-output devices devices die's metal lines dictate this limitation Violations result long-term deterioration Much larger currents (greater than peak) arising from capacitive-load charging line driving normal pose real problem rule thumb don't allow output current's value exceed device's current rating Unlike inputs unused outputs should left floating allow output switch without drawing current When testing board often necessary short output CMOS device overdrive force given level input driven this output other instances might need short outputs onetime basis without degrading IC's life follow rules When bench testing 54HC 74HC devices example short output several minutes without harm automatic testing short many eight outputs 1-sec duration Here again limitation imposed metallization POWER-SUPPLY CAVEATS that you've looked input output signals give some extra attention power-supply considerations instance supply levels affect device's logical operation should example keep supplies within range devices range devices Voltages high won't harm their performance isn't guaranteed these levels However HCTs (with exception oneshots Schmitt triggers) typically function with supplies about with it's crucial that reverse supply voltages Doing will forward bias substrate diode between ground (Figure resulting excessive currents damage with inputs outputs don't ground currents exceed
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FIGURE reaction 74HC00 gates noise spikes clearly seen these scope drawings gate exhibits noise immunity more Furthermore immunity equally good positive- negative-going noise spikes
devices units Again transients pose real problem long their values stay within devices' ratings UNDERSTANDING NOISE What happens signals just discussed aren't clean digital-logic systems ``noise'' defined extraneous voltage signal supply paths CMOS devices system noise that's great enough affect logic's integrity CMOS-logic families such CD4000 highly immune certain types system noise This immunity mainly nature CMOS also fact that devices' slowness reduces self-induced supply noise crosstalk prevents logic from responding short externally induced radiated transients However high-speed CMOS (which about times faster than CD4000 logic) crosstalk induced supply noise noise transients become factors Higher speeds allow device respond more quickly externally induced noise transients accentuate parasitic interconnection inductances capacitances that increase self-induced noise crosstalk Because HC-CMOS specifies input levels similar those CD4000 logic noise rejection also superior LSTTL because high-speed CMOS output impedance one-tenth that CD4000 devices it's less susceptible noise currents coupled outputs result lower stray voltages induced given amount current coupling quantify these noise parameters first define ``noise immunity'' device's ability prevent noise input from being transferred output More specifically it's amount voltage that applied input without causing output change state HC-CMOS this immunity approximately worst case it's maximum input High logic levels specified data sheet
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FIGURE Noise margins HC-CMOS HCTCMOS-TTL combination illustrated this graph that all-CMOS system exhibits higher noise immunity Noise immunity important attribute noise margin proves more useful because defines amount noise that system tolerate still maintain correct logic operation It's defined difference between output logic High) gate input logic High) gate given device driving example HC-CMOS using typical output levels ground input thresholds These figures yield noise margins approximately 1300 (logic One) (logic Zero) LS's noise immunity respectively Note that 54HC 74HC input levels skewed slightly toward ground tolerate slightly more noise than ground noise
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FIGURE Exhibiting high clock-noise immunity this 74HC74 flip flop shows change output noise spikes greater than
illustrate noise margin immunity Figure shows output that results when apply several types simulated noise 74HC00's input Typically even more input noise produces little change output Figure shows noise affects 74HC74's clock input Again logic errors occur with more clock noise 54HCT 74HCT have input buffer specially designed yield input levels Their noise-immunity characteristics therefore substantially different from those 54HC 74HC devices evaluating these differences note general applications logic NMOS XMOS HOMS) system all-CMOS system first case inputs driven outputs that essentially specify output levels this situation specified noise margin similar margin logic Zero either logic These values shown Figure significantly less than those all-HC system examine second case When using with output logic levels almost equal power-supply levels Therefore HCT's specified noise margin approximately logic Zero logic first glance high noise margin Ones might seem strange this situation presents tradeoff against Zero-level margin Compare gate-transfer functions Figure device logic trip point while gate trips Thus HC's typical performance twice that ground noise noise about better conclusion normal system (including all-CMOS systems) provides better noise immunity than case where could prove more helpful systems that designed with noiseless ground dirty Naturally this design approach isn't good second fact highlighted these transfer functions conservatively specified input output logic levels whereas specified more tightly even though data-sheet limits seem better actual system performance indicates that provides better overall noise margins
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FIGURE Comparing logic this graph shows noise immunity respective families wins ground noise noise CONSIDER SYSTEM NOISE take closer look system noise which group into several categories depending source type noise dictates appropriate noise-supression technique
Power-supply noise generated power-supply
line comes from logic switching CMOS circuits
Transmission-line reflections unwanted ringing overshoot phenomena arise from signals propagating down improperly terminated transmission signal lines
Signal crosstalk caused capacitive inductive coupling extraneous voltages from signal line another power-supply line
Radiated noise phenomenon that originates within high-speed-logic system emits other systems arises from high-frequency energy emitted when logic toggles This noise major problem with regard logic integrity interfere with other systems
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FIGURE This schematic shows currents 74HC00 gate that result when applying positive input step Also shown internal parasitic external load capacitances
Power-supply spiking perhaps most important contributor system noise When element switches logic states generates current spike that produces voltage transient these transients become large they cause logic errors because supply-voltage drop upsets internal logic because supply spike circuit's output feeds extraneous noise voltage into next device's input With CMOS logic quiescent state essentially current flows between ground when internal
gate output buffer switches state momentary current flows from ground This current components current required charge discharge stray load capacitance current that flows directly from ground when n-channel transistors turn momentarily during input transition
Figure shows paths these current components within 74HC00 upon application positive step device's input represent internal parasitic capacitances external load capacitance correspond currents that flow through both p-channel transistors during switching ICP1 ICP2 ICP3 charging currents capacitances switching transient caused unloaded output changing state typically equals peak Figure shows current voltage spikes resulting from switching single unloaded NAND gate Figures through show current spike's increase addition 1550- 100-pF loads large amount ringing results from test circuit's transmission-line effects This ringing occurs partly because CMOS gate switches from very high impedance very back
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FIGURE effects capacitive loads seen these drawings through show spikes resulting with load with 100-pF loads respectively ringing arises from test circuit's transmission-line effects
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FIGURE On-chip circuitry before 74HC00's output stage generates little current spiking shown drawing test circuit input switching (but output) Note very small power-supply glitches provoked input-circuit transitions again Note that even medium-size loads load-capacitance current becomes major current contributor verified dramatic increase current from unloaded 100-pF-load case Although internal logic generates current spikes when switching bulk spike's current comes from outputcircuit transitions Because outputs have largest n-channel currents greatest parasitic load capacitances Figure shows current 74HC00 gate with input switching other ground (thus with output transitions) best reduce noise-voltage transients implement good power-supply busing should maintain impedance from each circuit's ground model supply (Figure both ground traces exhibit inductances resistances capacitances reduce voltage transients keep supply line's parasitic inductances possible reducing trace lengths using wide traces ground planes strip-line microstrip transmission-line techniques decoupling supply with bypass capacitors effective supply decoupling bypass capacitors must supply charge required current spike duration with minimal voltage change determine bypass capacitor's approximate value from expression (SPIKE CURRENT) (SPIKE DURATION) (ALLOWABLE DROOP VOLTAGE) Consider this example typical MM54HC 74HC transient about lasting approximately (excluding ringing) allow peak noise required bypass capacitance about mA)(20 output CBYPASS
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FIGURE This equivalent circuit power-supply emphasizes both VCC's ground's series inductances minimize these inductances through careful circuit layout
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FIGURE Demonstrating importance bypassing drawings through show power-supply transients that occur when 74HC00 decoupled with 100-nF capacitors respectively
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FIGURE Showing results similar those depicted Figure these drawings show effects bypassing 74HC74 flip flop with capacitors that bypass yields supply spiking approximately lower than that 1-nF capacitor order prevent additional voltage spiking this local bypass capacitor must exhibit inductive reactance should therefore high-frequency ceramic capacitors place them very near minimize wiring inductance approximate amount tolerable inductance given (SPIKE VOLTAGE) (SPIKE RISE FALL TIME) (SPIKE CURRENT) example restricting inductive noise spike peak with current rise time yields 4V)(4 Note that addition localized decoupling very fast transients also need bulk decoupling spikes generated board's decouple provide high-value capacitor smoothing long time periods LSUPPLY show decoupling affects supply noise real-world situations Figure depicts power-supply transients that result when choose different values decoupling capacitors this example gate 74HC00 toggles 100-nF capacitors have approximately wiring between them supply Figure presents similar results obtained with 74HC74 circuit Note both cases (although unbypassed situation isn't depicted) that capacitor greatly reduces voltage transient Based empirical theoretical considerations determine guidelines These practical maxims serve only foundation system that should yield good results Consequently there's some leeway following them particular designs rule thumb it's generally good design practice restrict both ground noise less than
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FIGURE Tailor bypassing system's supply scheme Circuit diagram shows method with local regulators shows scheme adopt with centralized regulated supply tantalum- aluminum-electrolytic capacitors Before presenting guidelines examine some comparative attributes earlier CMOS LS-TTL devices First because higher speeds larger output currents supply-bypassing requirements devices more rigorous than those earlier metal-gate-CMOS Compared with those LS-TTL requirements similar little more stringent depending application Furthermore random logic 54HC 74HC 54LS 74LS similar bus-driving applications devices produce larger spikes Finally logic needs better grounding than logic fact design considerations closely follow those LS-TTL However with exhibits greater spiking bus-driving applications you're ready guidelines Keep VCC-bus routing short When using double-sided multilayer circuit boards strip-line transmission-line ground-plane techniques
local regulators bypass their inputs with tantalum capacitor least (Figure bypass their outputs with 50-mF tantalum- alumiumelectrolytic capacitor
system uses centralized regulated power supply
20-mF tantalum-electrolytic capacitor 100-mF aluminum-electrolytic capacitor decouple connected circuit board (Figure Provide localized decoupling random logic rule thumb dictates approximately (spaced within every five packages every packages group these capacitances it's more effective distribute them among design fair amount synchronous logic with outputs that tend switch simultaneously additional decoupling might advisable Octal flip flops buffers bus-oriented circuits might also require more decoupling Note that wire-wrapped circuits require more decoupling than ground-plane multilayer boards
Keep ground lines short boards make them
wide possible even trace width varies separate ground traces supply high-current devices such relay transmission-line drivers
circuits that drive transmission lines large capacitive loads buses example) ceramic capacitor close devices' supply pins
systems mixing linear logic functions where
supply noise critical analog components' performance provide separate supply buses even separate supplies
Finally terminate transmission-line grounds near
drivers
High-Speed-CMOS designs address noise levels
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