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High-Speed-CMOS designs address noise and I O levels

National Semiconductor Application Note 375 Larry Wakeman November 1984

High-Speed-CMOS designs address noise and I O levels
National Semiconductor Application Note 375 Larry Wakeman November 1984
To maximize the benefits of high-speed CMOS you must cope with environmental interactions and component limitations Especially important are system noise decoupling and both transient and steady-state level control
FIGURE 1 Essential but sometimes evil the diodes in CMOS-logic ICs can be easily damaged by excessive currents Reversed supplies or large input or output currents can cause diode burnout
AN-375
Published in EDN Magazine Copyright 1984 Cahners Publishing C1995 National Semiconductor Corporation
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RRD-B30M105 Printed in U S A
FIGURE 2 The reaction of 74HC00 gates (a) to noise spikes is clearly seen in these scope drawings The gate exhibits noise immunity of 2V or more (b) Furthermore the immunity is equally good for positive- and negative-going noise spikes
FIGURE 3 Exhibiting high clock-noise immunity this 74HC74 flip flop (a) shows no change in output for noise spikes greater than 2V (b)
FIGURE 5 Comparing HC and HCT logic this graph shows noise immunity of the respective families HC wins for ground noise HCT for VCC noise CONSIDER SYSTEM NOISE Now take a closer look at system noise which you can group into several categories depending on the source The type of noise dictates the appropriate noise-supression technique
Power-supply ICC noise generated in the power-supply
line comes from logic switching in CMOS circuits
Transmission-line reflections unwanted ringing and overshoot phenomena arise from signals propagating down improperly terminated transmission and signal lines
Signal crosstalk is caused by capacitive or inductive coupling of extraneous voltages from one signal line to another or to the power-supply line
Radiated noise an RF phenomenon that originates within a high-speed-logic system emits to other systems It arises from the high-frequency energy emitted when logic toggles This noise not a major problem with regard to logic integrity can interfere with other systems
FIGURE 6 This schematic shows the currents in a 74HC00 gate that result when applying a positive input step Also shown are the internal parasitic and external load capacitances
gate or an output buffer switches state a momentary current flows from VCC to ground This current has two components the current required to charge and discharge any stray or load capacitance and the current that flows directly from VCC to ground when the p- and n-channel transistors turn on momentarily during an input transition
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FIGURE 10 Demonstrating the importance of bypassing drawings (b) through (e) show power-supply transients that occur when a 74HC00 is decoupled with 1- 4 7- 10- and 100-nF capacitors respectively
If you use local regulators bypass their inputs with a tantalum capacitor of at least 1 mF (Figure 12a ) and bypass their outputs with a 10- to 50-mF tantalum- or alumiumelectrolytic capacitor (b)
If the system uses a centralized regulated power supply
Keep ground lines short and on pc boards make them as
wide as possible even if trace width varies Use separate ground traces to supply high-current devices such as relay and transmission-line drivers
In systems mixing linear and logic functions and where
Finally terminate transmission-line grounds near the
drivers
High-Speed-CMOS designs address noise and I O levels
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