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AC Characteristics of MM54HC MM74HC High-Speed CMOS

TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 5067

AC Characteristics of MM54HC MM74HC High-Speed CMOS
TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 5067
National Semiconductor Application Note 317 Larry Wakeman June 1983
AN-317
FIGURE 1 Typical Timing Waveform for (a) Propagation Delays and (b) Clocked Delays Also Test Circuit (c) for These Waveforms (tr e tf e 6 ns)
RRD-B30M115 Printed in U S A
TL F 5067-4
TL F 5067-5
(b) FIGURE 2 Typical TRI-STATE (a) Timing Waveforms and (b) Test Circuit for 54HC 74HC Devices
Note Some early data sheets used a different test circuit This has been changed or will be changed
The MM54HCT MM74HCT TTL input compatible devices are intended to operate with TTL devices and so it makes sense to specify them the same way as TTL Thus as shown in Figure 3 typical timing input waveforms use 0-3V levels and timing measurements are made from the 1 3V levels on these signals The test circuits used are the same as standard HC input circuits This is shown in Figure 3 These measurements are compatible with TTL type specified devices Specifying standard MM54HC MM74HC speeds using 2 5V input measurement levels does represent a specification incompatibility between TTL and most RAM ROM and microprocessor speed specifications It should not however present a design problem The timing difference that results from using different measurement points is the time it takes for an output to make the extra excursion from 1 3V to 2 5V Thus for a standard high-speed CMOS output the extra transition time should result worst case in less than a 2 ns increase in the circuit delay measurement for a 50 pF load Thus in speed critical designs adding 1-2 ns safely enables proper design of HC into the TTL level systems Power Supply Affect on AC Performance The overall power supply range of MM54HC MM74HC logic is not as wide as CD4000 series CMOS due to performance optimization for 5V operation however this family can operate over a 2 - 6V range which does enable some versatility 2
FIGURE 4 Typical Propagation Delay Variations of 74HC00 74HC139 74HC174 with Power Supply
In some designs it may be important to calculate the expected propagation delays for a specific situation not covered in the data sheet This can easily be accomplished by using the normalized curve of Figure 5 which plots propagation delay variation constant t(V) versus power supply voltage normalized to 4 5V and 5V operation This constant when used with the following equation and the data sheet 5 0V specifications yields the required delay at any power supply tPD(V) e t(V) tPD(5V) 10 Where tPD(5V) is the data sheet delay and tPD(V) is the resultant delay at the desired supply voltage This curve can also be used for the VCC e 4 5V specifications For example to calculate the typical delay of the 74HC00 at VCC e 6V the data sheet typical of 9 ns (15 pF load) is used From Figure 5 t(V) is 0 9 so the 6V delay would be 8 ns
FIGURE 6 Typical Propagation Delay Variation With Load Capacitance for 74HC04 74HC164 74HC240 74HC374
FIGURE 5 MM54HCMM74HC Propagation Delay Variation Vs Power Supply Normalized to VCC e 4 5V and VCC e 5 0V
Speed Variation with Capacitive Loading When high-speed CMOS is designed into a CMOS system the load on a given output is essentially capacitive and is the sum of the individual input capacitances TRI-STATE output capacitances and parasitic wiring capacitances As the load is increased the propagation delay increases The rate of increase in delay for a particular device is due to the increased charge discharge time of the output and the load The rate at which the delay changes is dependent on the output impedance of the MM54HC MM74HC circuit As mentioned for high-speed CMOS there are two output structures bus driver and standard
FIGURE 7 Propagation Delay Capacitance Variation Constant Vs Power Supply
Figure 6 plots some typical propagation delay variations against load capacitance To calculate under a particular load condition what the propagation delay of a circuit is one need only know what the rate of change of the propagation delay with the load capacitance and use this number to extrapolate the delay from the data sheet vaue to the desired value Figure 7 plots this constant t(C) against power supply voltage variation Thus by expanding on equation 1 0 the propagation delay at any load and power supply can be calculated using tPD(C V) e t(C) (CL b 15 pF) a tPD(5V) t(V) 11
Speed Variations with Change in Temperature Changes in temperature will cause some change in speed As with CD4000 and other metal-gate CMOS logic parts MM54HC MM74HC operates slightly slower at elevated temperatures and somewhat faster at lower temperatures The mechanism which causes this variation is the same as that which causes variations in metal-gate CMOS This
factor is carrier mobility which decreases with increase in temperature and this causes a decrease in overall transistor gain which has a corresponding affect on speed
ternal propagation delays Thus they exhibit the similar temperature and supply dependence as propagation delays They are however independent of output load conditions
FIGURE 9 Typical Output Rise or Fall Time Vs Load For Standard and Bus Driver Outputs
FIGURE 8 Typical Propagation Delay Variation With Temperature for 54HC02 54HC390 54HC139 54HC151
Output Rise and Fall Setup and Hold Times and Pulse Width Performance Variations So far the previous discussion has been restricted to propagation delay variations and in most instances this is the most important parameter to know Output rise and fall times may also be important Unlike TTL type logic families HC specifies these in the data sheet High-speed CMOS outputs were designed to have typically symmetrical rise and fall times Output rise and fall time variations track very closely the propagation delay variations over temperature and supply Figure 9 plots rise and fall time against output load at VCC e 5V and at room temperature Load variation of the transition time is twice the delay variation because delays are measured at halfway points on the waveform transition Setup times and pulse width performance under different conditions may be necessary when using clocked logic circuits These parameters are indirect measurements of in-
FIGURE 10 Comparison of LSTTL and High-Speed CMOS Delays
FIGURE 12 Comparison of HC-CMOS Metal-Gate CMOS and LSTTL Propagation Delay Vs Temperature
Conclusion High-speed CMOS circuits are speed compatible with 54LS 74LS circuits not only on the data sheets but even driving different loads In general HC-CMOS provides a large improvement in performance over older metal-gate CMOS By using some of the equations and curves detailed here along with data sheet specifications the designer can very closely estimate the performance of any MM54HC MM74HC device Even though the above examples illustrate typical performance calculations a more conservative design can be implemented by more conservatively estimating various constants and using worst case data sheet limits It is also possible to estimate the fastest propagation delays by using speeds about 0 4 - 0 7 times the data sheet typicals and aggressively estimating the various constants
FIGURE 11 Comparison of Metal-Gate CMOS and High-Speed CMOS Delays
AC Characteristics of MM54HC MM74HC High-Speed CMOS
AN-317
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