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COP888FH 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply / Divide

COP888FH 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply / Divide

COP888FH 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply / Divide
July 1999
COP888FH 8-Bit CMOS ROM Based Microcontrollers with 12k Memory, Comparators, USART and Hardware Multiply / Divide
General Description
The COP888FH Family of ROM based microcontrollers are highly integrated COP8 Feature core devices with 12k memory and advanced features including Analog comparators, and Hardware Multiply / Divide. These single-chip CMOS devices are suited for more complex applications requiring a full featured controller, low EMI, two comparators, a full-duplex USART, and hardware multiply / divide functions. COP87L88FH devices are pin and software compatible (different VCC range) 16k OTP (One Time Programmable) versions for pre-production , and for use with a range of COP8 software and hardware development tools. Device COP684FH COP884FH COP984FH COP688FH COP888FH COP988FH Memory (bytes) RAM (bytes) I / O Pins 12k ROM 12k ROM 12k ROM 12k ROM 12k ROM 12k ROM 512 512 512 512 512 512 24 24 24 36 / 40 36 / 40 36 / 40 Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1µs instruction cycle, hardware multiply / divide functions, three multi-function 16-bit timer / counters with PWM, full duplex USART, MICROWIRE / PLUSTM, two Analog comparators, two power saving HALT / IDLE modes, MIWU, idle timer, high current outputs, software selectable options WATCHDOG and clock / oscillator mode, low EMI 2.5V to 5.5V operation, and 28 / 40 / 44 pin packages. Devices included in this data sheet are:
Packages 28 DIP / SOIC 28 DIP / SOIC 28 DIP / SOIC
Temperature -40 to +85°C 0 to +70°C
Comments
Key Features
n Hardware Multiply / Divide Functions n Full duplex USART n Three 16-bit timers, each with two 16-bit registers supporting: - Processor Independent PWM mode - External Event counter mode - Input Capture mode n Quiet design (low radiated emissions) n 12 kbytes on-board ROM n 512 bytes on-board RAM
I / O Features
n Software selectable I / O options ( TRI-STATE ® , Push-Pull, Weak Pull-Up, and High Impedance Input) n Schmitt trigger inputs on ports G and L n Packages: - 40 DIP with 36 I / O pins - 44 PLCC with 40 I / O pins - 28 DIP / SO with 24 I / O pins
CPU / Instruction Set Features
n 1 µs instruction cycle time n Fourteen multi-source vectored interrupts servicing - External Interrupt - Idle Timer T0 - Three Timers (Each with 2 Interrupts) - MICROWIRE / PLUS - Multi-Input Wake Up - Software Trap - USART (2) - Default VIS (default interrupt) n Versatile and easy to use instruction set
Additional Peripheral Features
n n n n n Idle Timer Multi-Input Wakeup (MIWU) with optional interrupts (8) Two analog comparators WATCHDOG and Clock Monitor logic MICROWIRE / PLUS serial I / O
COP8 is a trademark of National Semiconductor Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. MICROWIRE / PLUS is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. WATCHDOG is a trademark of National Semiconductor Corporation. iceMASTER is a trademark of MetaLink Corporation.
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CPU / Instruction Set Features
(Continued) n 8-bit Stack Pointer (SP) - stack in RAM n Two 8-bit Register Indirect Data Memory Pointers (B and X)
Fully Static CMOS
Development Support
n Emulation and OTP devices n Real time emulation and full program debug offered by MetaLink Development System
Block Diagram
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FIGURE 1. COP888FH Block Diagram
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Connection Diagrams
Plastic Chip Carrier Dual-In-Line Package
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Top View Order Number COP688FH-XXX / V, COP888FH-XXX / V or COP988FH-XXX / V See NS Plastic Chip Package Number V44A
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Top View Order Number COP688FH-XXX / N, COP888FH-XXX / N or COP988FH-XXX / N See NS Molded Package Number N40A Dual-In-Line Package
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Order Number COP684FH-XXX / M, COP884FH-XXX / M, COP984FH-XXX / M, COP684FH-XXX / N, COP884FH-XXX / N or COP984FH-XXX / N See NS Molded Package Number M28B or N28B FIGURE 2. Connection Diagrams
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Connection Diagrams
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Pinouts for 28-, 40- and 44-Pin Packages Alt. Fun MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU INT T1B T1A SO SK SI HALT Restart CKX TDX RDX T2A T2B T3A T3B Alt. Fun 28-Pin Pack. 11 12 13 14 15 16 17 18 25 26 27 28 1 2 3 4 19 20 21 22 40-Pin Pack. 17 18 19 20 21 22 23 24 35 36 37 38 3 4 5 6 25 26 27 28 29 30 31 32 7 COMP1IN- COMP1IN+ COMP1OUT COMP2IN- COMP2IN+ COMP2OUT 8 9 10 9 10 11 12 13 14 15 16 39 40 1 2 44-Pin Pack. 17 18 19 20 25 26 27 28 39 40 41 42 3 4 5 6 29 30 31 32 33 34 35 36 9 10 11 12 13 14 15 16 43 44 1 2 21 22 23 24 6 23 5 24 8 33 7 34 8 37 7 38
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COP98xFH Absolute Maximum Ratings (Note 1)
If Military / Aerospace specified devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin -0.3V to VCC 7V + 0.3V
Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range
100 mA 110 mA -65°C to +140°C
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP98xFH:
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DC Electrical Characteristics COP98xFH:
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Units
AC Electrical Characteristics COP98xFH:
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AC Electrical Characteristics COP98xFH:
0°C TA +70°C unless otherwise specified Parameter MICROWIRETMSetup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time Reset Pulse Width
Note 2: Rate of voltage change must be less than 0.5V / ms.
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Conditions
Min 20 56
Units ns ns
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G ports in the TRI-STATE mode and tied to ground, all outputs low and tied to ground. The clock monitor and the comparator are disabled. Note 5: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
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FIGURE 3. MICROWIRE / PLUS Timing
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COP88xFH Absolute Maximum Ratings (Note 7)
If Military / Aerospace specified devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. Supply Voltage (VCC) 7V
Voltage at Any Pin Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range
-0.3V to VCC + 0.3V 100 mA 110 mA -65°C to +140°C
Note 7: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP88xFH:
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DC Electrical Characteristics COP88xFH:
-40°C TA +85°C unless otherwise specified Parameter Maximum Input Current without Latchup (Notes 11, 12) RAM Retention Voltage, Vr Input Capacitance Load Capacitance on D2 500 ns Rise and Fall Time (Min) (Note 12) (Note 12) Conditions Room Temp
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Units mA V
AC Electrical Characteristics COP88xFH:
-40°C TA +85°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal Resonator or External R / C Oscillator CKI Clock Duty Cycle (Note 12) Rise Time (Note 12) Fall Time (Note 12) Inputs tSETUP tHOLD Output Propagation Delay tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) (Note 12) MICROWIRE Hold Time (tUWH) (Note 12) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note 13) Interrupt Input High Time Interrupt Input Low Time Timer 1, 2, 3 Input High Time Timer 1, 2, 3 Input Low Time Reset Pulse Width
Min 2.5 1.0 7.5 3.0 45
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COP68xFH Absolute Maximum Ratings (Note 14)
If Military / Aerospace specified devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 7V -0.3V to VCC + 0.3V
Total Current into VCC Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range
100 mA 110 mA -65°C to +140°C
Note 14: Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics COP68xFH:
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AC Electrical Characteristics COP68xFH:
-55°C TA +125°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal Resonator or External CKI Clock Duty Cycle (Note 19) Rise Time (Note 19) Fall Time (Note 19) Inputs tSETUP tHOLD Output Propagation Delay (Note 20) tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) (Note 19) MICROWIRE Hold Time (tUWH) (Note 19) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note 20) Interrupt Input High Time Interrupt Input Low Time Timer 1, 2, 3 Input High Time Timer 1, 2, 3 Input Low Time Reset Pulse Width
Min 1.0 45
Comparators AC and DC Characteristics
VCC - 1.5
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Pin Descriptions
VCC and GND are the power supply pins. All VCC and GND pins must be connected. CKI is the clock input. This can come from an R / C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset Description section. The device contains three bidirectional 8-bit I / O ports (C, G and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I / O ports. Each I / O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I / O port. (See the memory map for the various addresses associated with the I / O ports.) Figure 4 shows the I / O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below: CONFIGURATION Register 0 0 1 1 0 1 0 1 Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull One Output DATA Register Port Set-Up
Since G6 is an input only pin and G7 is the dedicated CKO clock output pin (crystal clock option) or general purpose input (R / C clock option), the associated bits in the data and configuration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros. Note that the chip will be placed in the HALT mode by writing a "1" to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writing a "1" to bit 6 of the Port G Data Register. Writing a "1" to bit 6 of the Port G Configuration Register enables the MICROWIRE / PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R / C clock configuration is used.
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FIGURE 4. I / O Port Configurations Config Reg. G7 G6 CLKDLY Alternate SK Data Reg. HALT IDLE
PORT L is an 8-bit I / O port. All L-pins have Schmitt triggers on the inputs. The Port L supports Multi-Input Wake Up on all eight pins. L1 is used for the USART external clock. L2 and L3 are used for the USART transmit and receive. L4 and L5 are used for the timer input functions T2A and T2B. L6 and L7 are used for the timer input functions T3A and T3B. The Port L has the following alternate features: L7 L6 L5 L4 L3 L2 L1 MIWU MIWU MIWU MIWU MIWU MIWU MIWU or or or or or or or T3B T3A T2B T2A RDX TDX CKX
L0 MIWU Port G is an 8-bit port with 5 I / O pins (G0, G2-G5), an input pin (G6), and two dedicated output pins (G1 and G7). Pins G0 and G2-G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R / C oscillator mask option selected, G7 serves as a general purpose input pin but is also used to bring the device out of HALT mode with a low to high transition on G7. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I / O bits (G0, G2-G5) can be individually configured under software control.
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Port G has the following alternate features: G6 SI (MICROWIRE Serial Data Input) G5 SK (MICROWIRE Serial Clock) G4 SO (MICROWIRE Serial Data Output) G3 T1A (Timer T1 I / O) G2 T1B (Timer T1 Capture Input) G0 INTR (External Interrupt Input) Port G has the following dedicated functions: G7 CKO Oscillator dedicated output or general purpose input G1 WDOUT WATCHDOG and / or Clock Monitor dedicated output Port C is an 8-bit I / O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation for these unterminated pins will return unpredicatable values. PORT I is an eight-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw power only when addressed. Port I1-I3 are used for Comparator 1. Port I4-I6 are used for Comparator 2.
Pin Descriptions
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The Port I has the following alternate features. COMP2OUT (Comparator 2 Output) COMP2+IN (Comparator 2 Positive Input) COMP2-IN (Comparator 2 Negative Input) COMP1OUT (Comparator 1 Output) COMP1+IN (Comparator 1 Positive Input) COMP1-IN (Comparator 1 Negative Input)
with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X, SP pointers and S register. The data memory consists of 512 bytes of RAM. Sixteen bytes of RAM are mapped as "registers" at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, B and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively, with the other registers being available for general usage. The instruction set permits any bit in memory to be set, reset or tested. All I / O and registers (except A and PC) are memory mapped therefore, I / O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.8 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to less than 1000 pF.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits transfer of data from ROM to RAM. CPU REGISTERS The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tc) cycle time. There are six CPU registers: A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented. X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented. SP is the 8-bit stack pointer, which points to the subroutine / interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset. S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256 data segments of 128 bytes each. All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC). PROGRAM MEMORY The program memory consists of 12288 bytes of ROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the devices vector to program memory location 0FF Hex. DATA MEMORY The data memory address space includes the on-chip RAM and data registers, the I / O registers (Configuration, Data and Pin), the control registers, the MICROWIRE / PLUS SIO shift register, and the various registers, and counters associated
Data Memory Segment RAM Extension
Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S). The data store memory is either addressed directly by a single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously. With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 to 00FF) is extended. If this upper bit equals one (representing address range 0080 to 00FF), then address extension does not take place. Alternatively, if this upper bit equals zero, then the data segment extension register S is used to extend the base address range (from 0000 to 007F) from XX00 to XX7F, where XX represents the 8 bits from the S register. Thus the 128-byte data segment extensions are located from addresses 0100 to 017F for data segment 1, 0200 to 027F for data segment 2, etc., up to FF00 to FF7F for data segment 255. The base address range from 0000 to 007F represents data segment 0.
Figure 5 illustrates how the S register data memory extension is used in extending the lower half of the base address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are available for all data segments. The S register must be changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I / O registers, control registers, etc.) is always available regardless of the contents of the S register, since the upper base segment (address range 0080 to 00FF) is independent of data segment extension. The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always lo13 www.national.com
Data Memory Segment RAM Extension (Continued)
cated in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of reset. The 128 bytes of RAM contained in the base segment are split between the lower and upper base segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment, while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM is located at the upper sixteen addresses (0070 to 007F) of the lower base segment. Additional RAM beyond these initial 128 bytes, however, will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (XX00 to XX7F) of the lower base segment. The additional 128 bytes of RAM are memory mapped at address locations 0100 to 017F hex.
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is pulled low. Upon initialization, the data and configuration registers for ports L, G and C are cleared, resulting in these Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and / or Clock Monitor error output pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL, T2CNTRL and T3CNTRL control registers are cleared. The USART registers PSR, ENU (except that TBMT bit is set), ENUR and ENUI are cleared. The Comparator Select Register is cleared. The S register is initialized to zero. The Multi-Input Wakeup registers WKEN, WKEDG and WKPND are cleared. (Wakeup register WKPND is unknown.) The stack pointer, SP, is initialized to 6F Hex. The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the maximum WATCHDOG service window of 64k tC clock cycles. The Clock Monitor bit being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will continue until 16 tC-32 tC clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE mode. The external RC network shown in Figure 6 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
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Reads as all ones.
FIGURE 5. RAM Organization
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction cycle clock (tc). Figure 7 shows the Crystal and R / C oscillator diagrams.
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CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
FIGURE 6. Recommended Reset Circuit
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Oscillator Circuits
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Table 1 shows the component values required for various standard crystal values.
R / C OSCILLATOR By selecting CKI as a single pin oscillator input, a single pin R / C oscillator circuit can be connected to it. CKO is available as a general purpose input, and / or HALT restart input.
Table 2 shows the variation in the oscillator frequencies as functions of the component (R and C) values.
EXTERNAL OSCILLATOR CKI can be driven by an external clock signal. CKO is available as a general purpose input and / or HALT restart control. Crystal Oscillator
Note: 3k R 200k 50 pF C 200 pF
Control Registers
T1C3 Bit 7 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 0
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External Oscillator
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 0 Bit 7
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R / C Oscillator
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Reserved Bit 7 LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 0
FIGURE 7. Crystal R / C, and External Oscillator Diagrams
The ICNTRL register contains the following bits: Reserved This bit is reserved and must be zero.
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Control Registers
LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
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TIMER T0 (IDLE TIMER) The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The Timer T0 runs continuously at the fixed rate of the instruction cycle clock, tc. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions:
L Port Interrupt Enable (Multi-Input Wakeup / Interrupt) Timer T0 Interrupt pending Timer T0 Interrupt Enable (Bit 12 toggle) MICROWIRE / PLUS interrupt pending Enable MICROWIRE / PLUS interrupt Timer T1 Interrupt Pending Flag for T1B capture edge Timer T1 Interrupt Enable for T1B Input capture edge
T2C3 Bit 7 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 0
T3C3 Bit 7 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB Bit 0
TIMER T1, TIMER T2 AND TIMER T3 The device has a set of three powerful timer / counter blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the timer block Tx. Since the three timer blocks, T1, T2 and T3 are identical, all comments are equally applicable to any of the three timer blocks. Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload / capture registers, RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I / O required by the timer block, while the pin TxB is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode. The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation. Mode 1. Processor Independent PWM Mode As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The user only has to define the parameters of the PWM signal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely independent of the microcontroller. The user software services the timer block only when the PWM parameters require updating. In this mode the timer Tx counts down at a fixed rate of tc. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB. The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the timer for PWM mode operation.
The T3CNTRL control register contains the following bits: T3C3 Timer T3 mode control bit T3C2 Timer T3 mode control bit T3C1 Timer T3 mode control bit T3C0 Timer T3 Start / Stop control in timer modes 1 and 2, T3 Underflow Interrupt Pending Flag in timer mode 3 T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA in mode 1, T3 Underflow in mode 2, T3A capture edge in mode 3) T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A Input capture edge T3PNDB Timer T3 Interrupt Pending Flag for T3B capture edge T3ENB Timer T3 Interrupt Enable for Timer Underflow or T3B Input capture edge
Timers
The device contains a very versatile set of timers (T0, T1, T2, T3). All timers and associated autoreload / capture registers power up containing random data.
Figure 8 shows a block diagram of the timer in PWM mode. The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts. Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must reset these pending flags under software control. Two control en16
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Timers
(Continued)
able flags, TxENA and TxENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timerenable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output.
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FIGURE 9. Timer in External Event Counter Mode Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the input capture mode. In this mode, the timer Tx is constantly running at the fixed tc rate. The two registers, RxA and RxB, act as capture registers. Each register acts in conjunction with a pin. The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin. The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently. The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the TxA and TxB pins will be respectively latched into the pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin. Similarly, the flag TxENB controls the interrupts from the TxB pin. Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input capture or a timer underflow (or both) caused the interrupt.
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FIGURE 8. Timer in PWM Mode Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, Tx, is clocked by the input signal from the TxA pin. The Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are latched into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer underflows. In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag.
Figure 9 shows a block diagram of the timer in External Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being used as the counter input clock.
Figure 10 shows a block diagram of the timer in Input Capture mode.
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Timers
(Continued)
DS012602-14
FIGURE 10. Timer in Input Capture Mode
Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board RAM, registers, I / O states, and timers (with the exception of T0) are unaltered. HALT MODE The device can be placed in the HALT mode by writing a "1" to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The WATCHDOG logic on the device is disabled during the HALT mode.
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Power Save Modes
(Continued)
tion (since CKO becomes a dedicated output), and so may be used with an RC clock configuration. The third method of exiting the HALT mode is by pulling the RESET pin low. Since a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the tc instruction cycle clock. The tc clock is derived by dividing the oscillator clock down by a factor of 10. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip. If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset. The device has two mask options associated with the HALT mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT mode. With the HALT mode enable mask option, the device will enter and exit the HALT mode as described above. With the HALT disable mask option, the device cannot be placed in the HALT mode (writing a "1" to the HALT flag will have no effect, the HALT flag will remain "0"). IDLE MODE The device is placed in the IDLE mode by writing a "1" to the IDLE flag (G6 data bit). In this mode, all activities, except the associated on-board oscillator circuitry, and the IDLE Timer T0, are stopped.
Note: It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes.
Multi-Input Wakeup
The Multi-Input Wakeup feature is ued to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup / Interrupt feature may also be used to generate up to 8 edge selectable external interrupts.
Figure 11 shows the Multi-Input Wakeup logic.
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Multi-Input Wakeup
(Continued)
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FIGURE 11. Multi-Input Wake Up Logic The Multi-Input Wakeup feature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the Reg: WKEN. The Reg: WKEN is an 8-bit read / write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wakeup from the associated L port pin. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the Reg: WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a pseudo Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: RBIT 5, WKEN Disable MIWN SBIT 5, WKEDG Change edge polarity RBIT 5, WKPND Reset pending flag SBIT 5, WKEN Enable MIWU If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup / Interrupt, a safety procedure should also be followed to avoid inherited pseudo wakeup conditions. After the selected L port bits have been
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changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called WKPND. The respective bits of the WKPND register will beset on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Consequently, the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode. WKEN, WKPND and WKEDG are all read / write registers, and are cleared at reset. PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine. The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable inter-
Multi-Input Wakeup
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rupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. (See HALT mode for clock option wakeup information.)
Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits.
USART
The device contains a full-duplex software programmable USART. The USART (Figure 12) consists of a transmit shift
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FIGURE 12. USART Block Diagram
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USART
(Continued)
USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. DESCRIPTION OF USART REGISTER BITS ENU-USART Control and Status Register (Address at 0BA)
PEN Bit 7 PSEL1 XBIT9 / PSEL0 Bit 0 CHL1 CHL0 ERR RBFL TBMT
STP2 Bit 7 STP78 ETDX SSEL XRCLK XTCLK ERI ETI Bit 0
DOE Bit 7
Note 21: Bit is reserved for future use. User must set to zero.
Reserved (Note 21)
RBIT9
RCVG Bit 0
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USART
(Continued)
Associated I / O Pins
Data is transmitted on the TDX pin and received on the RDX pin. TDX is the alternate function assigned to Port L pin L2 it is selected by setting ETDX (in the ENUI register) to one. RDX is an inherent function of Port L pin L3, requiring no setup. The baud rate clock for the USART can be generated on-chip, or can be taken from an external source. Port L pin L1 (CKX) is the external clock I / O pin. The CKX pin can be either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a clock signal which may be selected to drive the transmitter and / or receiver. As an output, it presents the internal Baud Rate Generator output.
USART Operation
The USART has two modes of operation: asynchronous mode and synchronous mode. ASYNCHRONOUS MODE This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to the USART is 16 times the baud rate. The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current character on the TDX pin, the TBUF register may be loaded by software with the next byte to be transmitted. When TSFT finishes transmitting the current character the contents of TBUF are transferred to the TSFT register and the Transmit Buffer Empty Flag (TBMT in the ENU register) is set. The TBMT flag is automatically reset by the USART when software loads a new character into the TBUF register. There is also the XMTG bit which is set to indicate that the USART is transmitting. This bit gets reset at the end of the last frame (end of last Stop bit). TBUF is a read / write register. The RSFT and RBUF registers double-buffer data being received. The USART receiver continually monitors the signal on the RDX pin for a low level to detect the beginning of a Start bit. Upon sensing this low level, it waits for half a bit time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and the remaining bits in the character frame are each sampled a single time, at the mid-bit position. Serial data input on the RDX pin is shifted into the RSFT register. Upon receiving the complete character, the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag (RBFL) is set. RBFL is automatically reset when software reads the character from the RBUF register. RBUF is a read only register. There is also the RCVG bit which is set high when a framing error occurs and goes low once RDX goes high. TBMT, XMTG, RBFL and RCVG are read only bits. SYNCHRONOUS MODE In this mode data is transferred synchronously with the clock. Data is transmitted on the rising edge and received on the falling edge of the synchronous clock.
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USART Operation
(Continued)
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FIGURE 13. Framing Formats USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses 0xEC to 0xEF Hex in the program memory space. The interrupts can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in the ENUI register. The interrupt from the Transmitter is set pending, and remains pending, as long as both the TBMT and ETI bits are set. To remove this interrupt, software must either clear the ETI bit or write to the TBUF register (thus clearing the TBMT bit). The interrupt from the receiver is set pending, and remains pending, as long as both the RBFL and ERI bits are set. To remove this interrupt, software must either clear the ERI bit or read from the RBUF register (thus clearing the RBFL bit). the basic baud clock is created from the oscillator frequency through a two-stage divider chain consisting of a 1-16 (increments of 0.5) prescaler and an 11-bit binary counter. (Figure 14) The divide factors are specified through two read / write registers shown in Figure 15. Note that the 11-bit Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset. As shown in Table 3, a Prescaler Factor of 0 corresponds to NO CLOCK. NO CLOCK condition is the USART power down mode where the USART clock is turned off for power saving purpose. The user must also turn the USART clock off when a different baud rate is chosen. The correspondences between the 5-bit Prescaler Select and Prescaler factors are shown in Table 3. There are many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive the software programmable baud rate counter to create a 16x clock for the following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 Table 4. Other baud rates may be created by using appropriate divisors. The 16x clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receiver.
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of the USART can be individually selected to come either from an external source at the CKX pin (port L, pin L1) or from a source selected in the PSR and BAUD registers. Internally,
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Baud Clock Generation
(Continued)
DS012602-18
FIGURE 14. USART BAUD Clock Generation
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FIGURE 15. USART BAUD Clock Divisor Registers TABLE 3. Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 Prescaler Factor NO CLOCK 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 TABLE 4. Baud Rate Divisors (1.8432 MHz Prescaler Output) Baud Rate 110 (110.03) 134.5 (134.58) 150 300 600 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor - 1 (N-1) 1046 855 767 383 191 95 63 47 31 23 15 11 5 2
Prescaler Select 11110 11111
Prescaler Factor 15.5 16
The entries in Table 4 assume a prescaler output of 1.8432 MHz. In the asynchronous mode the baud rate could be as high as 625k.
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Baud Clock Generation
(Continued)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
(RDX) is internally connected to the transmitter output pin (TDX) the output of the Transmitter Shift Register is "looped back" into the Receive Shift Register input. In this mode, data that is transmitted is immediately received. This feature allows the processor to verify the transmit and receive data paths of the USART. Note that the framing format for this mode is the nine bit format one Start bit, nine data bits, and 7 / 8, one or two Stop bits. Parity is not generated or verified in this mode.
Attention Mode
The USART Receiver section supports an alternate mode of operation, referred to as ATTENTION Mode. This mode of operation is selected by the ATTN bit in the ENUR register. The data format for transmission must also be selected as having nine Data bits and either 7 / 8, one or two Stop bits. The ATTENTION mode of operation is intended for use in networking the device with other processors. Typically in such environments the messages consists of device addresses, indicating which of several destinations should receive them, and the actual data. This Mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1. If the ninth bit is reset to a zero the byte is a Data byte. While in ATTENTION mode, the USART monitors the communication flow, but ignores all characters until an address character is received. Upon receiving an address character, the USART signals that the character is ready by setting the RBFL flag, which in turn interrupts the processor if USART Receiver interrupts are enabled. The ATTN bit is also cleared automatically at this point, so that data characters as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding either to accept the subsequent data stream (by leaving the ATTN bit reset) or to wait until the next address character is seen (by setting the ATTN bit again). Operation of the USART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted is programmed by setting XBIT9 appropriately. The value of the ninth bit received is obtained by reading RBIT9. Since this bit is located in ENUR register where the error flags reside, a bit operation on it will reset the error flags.
Effect of HALT / IDLE
The USART logic is reinitialized when either the HALT or IDLE modes are entered. This reinitialization sets the TBMT flag and resets all read only bits in the USART control and status registers. Read / Write bits remain unchanged. The Transmit Buffer (TBUF) is not affected, but the Transmit Shift register (TSFT) bits are set to one. The receiver registers RBUF and RSFT are not affected. The device will exit from the HALT / IDLE modes when the Start bit of a character is detected at the RDX (L3) pin. This feature is obtained by using the Multi-Input Wakeup scheme provided on the device. Before entering the HALT or IDLE modes the user program must select the Wakeup source to be on the RDX pin. This selection is done by setting bit 3 of WKEN (Wakeup Enable) register. The Wakeup trigger condition is then selected to be high to low transition. This is done via the WKEDG register (Bit 3 is one.) If the device is halted and crystal oscillator is used, the Wakeup signal will not start the chip running immediately because of the finite start up time requirement of the crystal oscillator. The idle timer (T0) generates a fixed (256 tC) delay to ensure that the oscillator has indeed stabilized before allowing the device to execute code. The user has to consider this delay when data transfer is expected immediately after exiting the HALT mode.
Comparators
The device contains two differential comparators, each with a pair of inputs (positive and negative) and an output. Ports I1-I3 and I4-I6 are used for the comparators. The following is the Port I assignment: I6 Comparator2 output I5 Comparator2 positive input I4 I3 Comparator2 negative input Comparator1 output
Diagnostic
Bits CHL0 and CHL1 in the ENU register provide a loopback feature for diagnostic testing of the USART. When these bits are set to one, the following occur: The receiver input pin
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I2 Comparator1 positive input I1 Comparator1 negative input A Comparator Select Register (CMPSL) is used to enable the comparators, read the outputs of the comparators internally, and enable the outputs of the comparators to the pins. Two control bits (enable and output enable) and one result bit are associated with each comparator. The comparator result bits (CMP1RD and CMP2RD) are read only bits which will read as zero if the associated comparator is not enabled. The Comparator Select Register is cleared with reset, resulting in the comparators being disabled. The comparators
Comparators
(Continued)
Rsvd Bit 7 CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Rsvd Bit 0
The CMPSL register contains the following bits: Rsvd These bit are reserved and must be zero CMP20E Selects pin I6 as comparator 2 output provided that CMP2EN is set to enable the comparator CMP2RD Comparator 2 result (this is a read only bit, which will read as 0 if the comparator is not enabled) CMP2EN Enable comparator 2 CMP10E Selects pin I3 as comparator 1 output provided that CMPIEN is set to enable the comparator CMP1RD Comparator 1 result (this is a read only bit, which will read as 0 if the comparator is not enabled) CMP1EN Enable comparator 1 Note that the two unused bits of CMPSL may be used as software flags. Comparator outputs have the same spec as Ports L and G except that the rise and fall times are symmetrical.
Multiply / Divide
This device contains a multiply / divide block. This block supports a 1 byte x 2 bytes (3 bytes result) multiply or a 3 bytes / 2 bytes (2 bytes result) divide operation. The multiply or divide operation is executed by setting control bits located in the multiply / divide control register. The multiply or divide operands must be placed into the appropriate memory mapped locations before the operation is initiated. CONTROL REGISTER BITS
Rsvd Bit 7 Rsvd Rsvd Rsvd Rsvd DIV OVF Bit 0 DIV MULT
MULTIPLY / DIVIDE OPERATION For the multiply operation, the multiplicand is placed at addresses xx9B and xx9C. The multiplier is placed at address xx99. For the divide operation, the dividend is placed at addresses xx98 to xx9A and the divisor is placed at addresses xx9B to xx9C. In both operations, all operands are interpreted as unsigned values. The divide or multiply operation is started by setting the appropriate MDCR bit. If both the MULT and DIV bits are set, the microcontroller performs a divide operation. (The user is not required to read or clear the DIVOVF error bit prior to beginning a new multiply / divide operation. This bit is ignored during subsequent operations. However, the next divide operation will overwrite the error flag as appropriate, and the next multiply operation will clear it.) The multiply operation requires 1 instruction cycle to complete. The divide operation requires 2 instruction cycles to complete. A divide by zero or a division which produces an overflow requires only 1 instruction cycle to execute. The MDR1 through MDR5 registers and the MDCR register can not be read from or written to during a multiply or divide operation. Any attempt to write in to these registers will be ignored. Any attempt to read these registers will return undefined data. The result of a multiply is placed in addresses xx99-xx9B. The result of a divide is placed in a ddresses xx98-xx99. If a division by zero is attempted or if the resulting quotient of a divide operation is more than 16 bits long, then the DIVOVF bit is set in the multiply / divide control register. The dividend and the divisor are left unchanged. The divide operation always causes the DIVOVF flag to be set or reset as appropriate. The DIVOVF flag is cleared following a multiply operation. RESET STATE A reset signal applied to the device during normal operation has the following affects: MDCR is cleared, and any operation in progress is stopped. MDR1 through MDR5 are undefined.
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Multiply / Divide
Register Name (Address) MDR1 (xx98) MDR2 (xx99) MDR3 (xx9A) MDR4 (xx9B) MDR5 (xx9C)
(Continued) TABLE 5. Multiply / Divide Registers Multiplication Assignment Division Assignment Before Operation Low Byte of Dividend Middle Byte of Dividend High Byte of Dividend Low Byte of Divisor High Byte of Divisor After Operation Low Byte of Result High Byte of Result Undefined Low Byte of Divisor High Byte of Divisor
Before Operation Unused Multiplier Low Byte of Multiplicand High Byte of Multiplicand
After Operation Unchanged Low Byte of Result Middle Byte of Result High Byte of Result Unchanged
Interrupts
Introduction Each device supports thirteen vectored interrupts. Interrupt sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L Wakeup, Software Trap, MICROWIRE / PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to vector to the appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default VIS has the lowest priority. Each of the 13 maskable inputs has a fixed arbitration ranking and vector.
Figure 16 shows the Interrupt Block diagram.
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FIGURE 16. Interrupt Block Diagram
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Interrupts
(Continued)
Table 6 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table. The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For exwww.national.com
Interrupts
(Continued)
ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction is executed, the program jumps to the address specified in the vector table. The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. If two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced. If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to the execution of the VIS instruction, such as executing a single cycle instruction which clears an enable flag at the same time that the pending flag is set. It can also result, however, from inadvertent execution of the VIS command outside of the context of an interrupt. The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro-
gram context (A, B, X, etc.) and executing the RETI instruction, an interrupt service routine can be terminated by returning to the VIS instruction. In this case, interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started. After testing the GIE bit to ensure that execution is not erroneous, the routine should restore the program context and execute the RETI to return to the interrupted program. This technique can save up to fifty instruction cycles (tc), or more, (50µs at 10 MHz oscillator) of latency for pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending. To ensure reliable operation, the user should always use the VIS instruction to determine the source of an interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be altered, but the reliability of the interrupt system is compromised. The polling routine must individually test the enable and pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced, resulting in an inadvertent "locking out" of all maskable interrupts by the Software Trap pending flag. Problems such as this can be avoided by using VIS instruction.
TABLE 6. Interrupt Vector Table Arbitration Ranking (1) Highest (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Lowest Source Software Reserved External Timer T0 Timer T1 Timer T1 MICROWIRE / PLUS Reserved UART UART Timer T2 Timer T2 Timer T3 Timer T3 Port L / Wakeup Default VIS Receive Transmit T2A / Underflow T2B T3A / Underflow T3B Port L Edge Reserved Pin G0 Edge Underflow T1A / Underflow T1B BUSY Goes Low Description INTR Instruction Vector Address Hi-Low Byte 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
Note 22: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a block. In this case, the table must be in the next block.
VIS Execution When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc..) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is generated and so forth. If the only active interwww.national.com 30
rupt is software trap, than E0 is generated. This number replaces the lower byte of the PC. The upper byte of the PC remains unchanged. The new PC is therefore pointing to the vector of the active interrupt with the highest arbitration ranking. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitration ranking.
Interrupts
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Figure 17 illustrates the different steps performed by the VIS instruction. Figure 18 shows a flowchart for the VIS instruction.
The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET.
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FIGURE 17. VIS Operation
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FIGURE 18. VIS Flowchart
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Interrupts
(Continued)
WAIT:
G0 pin configured Hi-Z Ext interrupt polarity falling edge Enable the external interrupt Set the GIE bit Wait for external interrupt
The interrupt causes a branch to address 0FF The VIS causes a branch to interrupt vector table
Vector table (within 256 byte of VIS inst.) containing the ext interrupt service routine
SERVICE:
EXPND, PSW
Interrupt Service Routine Reset ext interrupt pend. bit
Return, set the GIE bit
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Interrupts
(Continued)
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WATCHDOG
The device contains a WATCHDOG and clock monitor. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or "runaway" programs. The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin. The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window. Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 7 shows the WDSVR register. The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window.
Table 8 shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software. Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is t