µPD78058F(A) 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD78058F(A) 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD78058F(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78058F(A) 8-bit single-chip microcontroller belonging µPD78058F Subseries 78K/0. stricter quality assurance program applied this device, which classified special grade, compared
µPD78058F, which classified standard grade.
Electro Magnetic Interference (EMI) noise generated inside µPD78058F(A) reduced compared
µPD78058 Subseries.
This microcontroller includes rich peripheral hardware, such 8-bit resolution converter, 8-bit resolution converter, timer, serial interface, real-time output port, interrupt functions. µPD78P058F, one-time PROM which operated same supply voltage range mask version, various development tools also available. Details function description, etc, described following User's Manual. sure read when designing.
µPD78058F, 78058FY Subseries User's Manual U12068E
78K/0 Series User's Manual, Instruction IEU-1372
FEATURES
noise reduction version (The overall peak level reduced dB.) Large on-chip Buffer Expanded Kbytes bytes 1024 bytes High-speed 1024 bytes
Package: 80-pin plastic External memory expansion space: Kbytes Instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain 8-bit resolution converter channels 8-bit resolution converter channels Serial interface channels Timer: channels Supply voltage
APPLICATIONS
Automobile equipment control units, detector/cutoff units, safety devices, etc.
information this document subject change without notice.
Document U12325EJ1V0DS00 (1st edition) Date Published April 1997 Printed Japan
1996 1997
µPD78058F(A)
ORDERING INFORMATION
Part Number Package 80-pin plastic Special (for high reliability electronic equipment) Remark denotes code suffix.
Please refer "Quality grade Semiconductor Devices" (Document number C11531E) published Corporation know specification quality grade devices recommended applications.
Quality Grade
Differences between PD78058F(A) PD78058F
Product name Item Quality grade Package Special 80-pin plastic resin thickness Standard 80-pin plastic 80-pin plastic 80-pin plastic resin thickness resin thickness TQFP (fine pitch)
PD78058F(A)
µPD78058F
µPD78058F(A)
78K/0 SERIES PRODUCT DEVELOPMENT
These products further development 78K/0 Series. designations appearing inside boxes subseries names.
Mass-produced products Products under development Subseries supports specifications. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin µPD78075B µPD78078 µPD78070A µPD780018Note µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD78075BY µPD78078Y µPD78070AY µPD780018YNote Note µPD780058Y µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y noise version µPD78078 Timer added µPD78054 external interface enhanced. ROM-less versions µPD78078 Serial µPD78078 enhanced only selected functions provided. Serial I/O-enhanced versions µPD78054; noise version noise version µPD78054 UART converter added µPD78014 enhanced. A/D-enhanced version µPD780024 Serial I/O-enhanced versions µPD78018F; noise version noise version µPD78018F Low-voltage (1.8 operation versions µPD78014 with several capacities available. converter 16-bit timer added µPD78002. converter added µPD78002. Basic subseries control applications On-chip UART, operable voltage (1.8
Inverter control 64-pin 64-pin µPD780964 µPD780924 driving 78K/0 Series 100-pin 100-pin 80-pin 80-pin µPD780208 µPD780228 µPD78044H µPD78044F µPD78044F enhanced. Total display outputs pins µPD78044H enhanced. Total display outputs pins N-ch open-drain added µPD78044F. Total display outputs pins Basic subseries driving. Total display outputs: pins A/D-enhanced version µPD780924 On-chip inverter control circuit UART incorporated; noise version
driving 100-pin 100-pin 100-pin µPD780308 µPD78064B µPD78064 µPD780308Y µPD78064Y µPD78064 enhanced, expanded. noise version µPD78064 Basic subseries driving LCDs with on-chip UART.
IEBus 80-pin
supported IEBus controller added µPD78054.
µPD78098
64-pin µPD78P0914 output, digital code decoder Hsync counter incorporated.
Note Under planning
µPD78058F(A)
major functional differences among subseries shown below.
External MIN. Expansion Value
Function Subseries Name Control
Capacity
Timer 8-bit 16-bit Watch
8-bit 10-bit 8-bit
Serial Interface (UART:
µPD78075B µPD78078 µPD78070A
(Time division 3-wire: (Time division UART: (UART: (UART: Time division 3-wire:
µPD780018 µPD780058 µPD78058F µPD78054 µPD780024 µPD78014H µPD78018F µPD78014 µPD78002 µPD78083
Inverter control driving Note
µPD780034
(UART: (UART:
µPD780001
µPD780964 µPD780924
µPD780208 µPD780228 µPD78044F
µPD78044H
(Time division UART: (UART:
driving
µPD780308 µPD78064B µPD78064
IEBus µPD78098 supported
(UART:
µPD78P0914
Note 10-bit timer: channel
µPD78058F(A)
OVERVIEW FUNCTION
Item Internal memory High-speed Buffer Expanded Memory space General registers Instruction cycle When main system clock selected When subsystem clock selected Instruction Kbytes 1024 bytes bytes 1024 Kbytes Kbytes bits registers bits registers banks) On-chip instruction execution time cycle modification function µs/0.8 s/1.6 µs/3.2 s/6.4 µs/12.8 5.0-MHz operation) 32.768-kHz operation) 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, boolean operation) correction, etc. Function
ports
Total CMOS input CMOS N-ch open-drain
converter converter Serial interface
8-bit resolution channels 8-bit resolution channels 3-wire srial I/O, SBI, 2-wire serial mode selectable: channel 3-wire serial mode (on-chip max. bytes automatic data transmit/receive function): channel 3-wire serial UART mode selectable: channel 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer channel channels channel channel
Timer
Timer output Clock output
(14-bit output 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, main system clock operation) 32.768 subsystem clock 32.768 operation) kHz, kHz, kHz, main system clock operation) Maskable Non-maskable Software Internal interupt external interrupt Internal interrupt Internal external 85°C 80-pin plastic
Buzzer output Vectored interrupt source
Test input Supply voltage Operating ambient temperature Package
µPD78058F(A)
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS Port Pins Non-port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES Ports Clock Generator Timer/event Counter Clock Output Control Circuit. Buzzer Output Control Circuit Converter Converter Serial Interfaces Real-Time Output Port Functions
INTERRUPT FUNCTIONS TEST FUNCTIONS Interrupt Functions Test Functions
EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS
PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78058F(A)
CONFIGURATION (TOP VIEW)
80-pin plastic
P01/INTP1/TI01 P00/INTP0/TI00
P06/INTP6
P05/INTP5
P04/INTP4
P03/INTP3
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1
P02/INTP2
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
XT1/P07
AVREF0
AVDD
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P56/A14
P57/A15
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
Cautions Connect directly Internally Connected (IC) functions both converter power supply port power supply. When µPD78058F(A) used applications where noise generated inside microcontroller need reduced, connect another power supply which same potential functions both ground converter port. When PD78058F(A) used applications where noise generated inside microcontroller needs reduced, connect AVSS ground line other than
P64/RD
P50/A8
P51/A9
µPD78058F(A)
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD AVREF0 AVREF1 AVSS BUSY P120 P127 P130, P131
Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 Port13
RESET RTP0 RTP7 SB0, SCK0 SCK2 TI00, TI01 TI1, TI2, WAIT XT1,
Programmable Clock Read Strobe Reset Real-Time Output Port Receive Data Serial Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
INTP0 INTP6 Interrupt from Peripherals
µPD78058F(A)
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER WATCHDOG TIMER
PORT1
PORT2
PORT3
WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72
PORT4
SERIAL INTERFACE 78K/0 CORE SERIAL INTERFACE Kbytes
PORT5
PORT6
PORT7
PORT12 SERIAL INTERFACE 2080 bytes PORT13
P120 P127
P130, P131
ANI0/P10 ANI7/P17 AVREF0
CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127 AD0/P40 AD7/P47 A8/P50 A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67
ANO0/P130, ANO1/P131 AVREF1
CONVERTER
EXTERNAL ACCESS
INTP0/P00 INTP6/P06 BUZ/P36
INTERRUPT CONTROL BUZZER OUTPUT SYSTEM CONTROL CLOCK OUTPUT CONTROL
PCL/P35
AVDD AVSS
RESET XT1/P07
µPD78058F(A)
FUNCTIONS
Port Pins (1/2)
After Dual-function Reset Input Input INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 Input Input/ output Input only Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.Note Input Input ANI0 ANI7
Name
Note
Input Input/ output Port 8-bit port
Function Input only Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input/ output
Port Input 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
SCK1 BUSY SI0/SB0 SO0/SB1 SCK0
Notes When using P07/XT1 pins input port, (FRC) processor clock control register (PCC). On-chip feedback resistor subsystem clock oscillator should used. When using P10/ANI0 P17/ANI7 pins converter analog input pins, on-chip pullup resistor cancelled automatically. Caution pins which also function port pins, perform following operations during conversion. these operations performed, total error ratings cannot kept. Rewrite output latch which used port pin. Change output level used output pin, even used port pin.
µPD78058F(A)
Port Pins (2/2)
Input/ output Function Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. After Dual-function Reset Input Input/ output Port Input 8-bit input/output port. Input/output specified 8-bit unit. When used input port, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection. Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/outport port. Input/output specified bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. When used input port, on-chip pull-up resistor used software. Input
Name
Input/ output
Input/ output
Input
Input
WAIT ASTB
Input/ output
Port 3-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 2-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input
SI2/RXD SO2/TXD SCK2/ASCK
P120 P127 Input/ output
Input RTP0 RTP7
P130, P131
Input/ output
Input
ANO0, ANO1
Caution
pins which also function port pins, perform following operations during conversion. these operations performed, total error ratings cannot kept. Rewrite output latch which used port pin. Change output level used output pin, even used port pin.
µPD78058F(A)
Non-port Pins (1/2)
Input Function After Dual-function Reset Input Serial interface serial data input. Input P25/SB0 P70/R Output Serial interface serial data output. Input P26/SB1 P71/TXD Input/ output Input/ output Serial interface serial data input/output. Input P25/SI0 P26/SO0 Serial interface serial clock input/output. Input P72/ASCK Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) Output 16-bit timer (TM0) output (dual-function 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Real-time output port which data output synchronization with trigger. Low-order address/data external memory expansion. Input Input Input Input Input Input Input Input Input Input Input P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P120 P127
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01
External interrupt request input which effective edge (rising edge, falling Input edge, both rising edge falling edge) specified.
RTP0 RTP7 Output Input/ output Output Output
High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
µPD78058F(A)
Non-port Pins (2/2)
Input Output Function Wait insertion external memory access. Strobe output which latches address information output port access external memory. converter analog input. converter analog output. converter reference voltage input. converter reference voltage input. converter analog power supply (shared with port power supply) converter ground potential (shared with port ground potential) System reset input. Main system clock oscillation crystal connection. After Dual-function Reset Input Input
Name WAIT ASTB
ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET
Input Output Input Input Input Input Input
Input Input
P130, P131
Subsystem clock oscillation crystal connection.
Input
Positive power supply (except port). Ground potential (except port). Internal connection. Connect directly.
Cautions AVDD functions both converter power supply port power supply. When PD78058F(A) used applications where noise generated inside microcontroller need reduced, connect another power supply which same potential functions both ground converter converter port. When µPD78058F(A) used applications where noise generated inside microcontroller needs reduced, connect AVSS ground line other than
µPD78058F(A)
Circuits Recommended Connection Unused Pins
input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1.
Table 3-1. Input/Output Circuit Type Each (1/2)
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 11-C Input Input/output Connected Independently connected through resistor. Input/output Circuit Type Input Input/output Connected Independently connected through resistor. Recommended Connection when Used
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7
10-C
Independently connected through resistor.
P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB
13-I
Independently connected through resistor. Independently connected through resistor. Independently connected through resistor.
µPD78058F(A)
Table 3-1. Input/Output Circuit Type Each (2/2)
Input/output Circuit Type P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0 P131/ANO1 RESET AVREF0 AVREF1 AVDD Input Leave open. Connected Connected Connect another power supply which same potential VDD. AVSS Connect another ground line which same potential Connected directly. 12-B Input/output Independently connected through resistor. Input/output Independently connected through resistor.
Name
Recommended Connection when Used
µPD78058F(A)
Figure 3-1. Input/Output Circuits (1/2)
Type
Type AVDD
pull-up enable data AVDD P-ch
P-ch
IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic output disable N-ch AVSS
Type pull-up enable AVDD data
AVDD
Type 10-C
AVDD
P-ch
pull-up enable AVDD data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch AVSS
output disable
N-ch AVSS
input enable Type AVDD Type 11-C pull-up enable data AVDD P-ch AVDD P-ch IN/OUT IN/OUT output disable N-ch AVSS input enable output disable Comparator N-ch P-ch AVSS AVSS N-ch VREF (Threshold Voltage)
pull-up enable AVDD data P-ch
P-ch
µPD78058F(A)
Figure 3-1. Input/Output Circuits (2/2)
Type 12-B pull-up enable AVDD data
AVDD
Type feed back cut-off P-ch
P-ch
P-ch IN/OUT
output disable AVSS input enable
N-ch
P-ch Analog Output Voltage N-ch AVSS
Type 13-I AVDD Mask Option IN/OUT data output disable N-ch AVSS AVDD
P-ch
Medium Voltage Withstand Input Buffer
µPD78058F(A)
MEMORY SPACE
Figure shows PD78058F(A) memory map. Figure 4-1. Memory
FFFFH Special Function Registers (SFR) bits FF00H FEFFH FEE0H FEDFH
General Registers bits
Internal High-Speed 1024 bits FB00H FAFFH Prohibited Data Memory Space FAE0H FADFH Buffer bits FAC0H FABFH Prohibited F800H F7FFH Internal Expanded 1024 bits Program Memory Space F400H F3FFH F000H EFFFH Internal 61440 bits 0000H 0040H 003FH Vector Table Area 0000H 0800H 07FFH Program Area 0080H 007FH CALLT Table Area 1000H 0FFFH CALLF Entry Area EFFFH Program Area
Prohibited Note
Note When external device expansion function used, internal capacity Kbytes less using memory size switching register (IMS).
µPD78058F(A)
PERIPHERAL HARDWARE FUNCTION FEATURES
Ports
following types ports available. CMOS input (P00, P07) CMOS input/output (P01 P06, port port P67, port port port N-channel open-drain input/output (P60 P63) Total
Table 5-1. Port Functions
Name Port
Name P00, Dedicated input port pins
Function
Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable 8-bit units. When used input port pins, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Port
Port
Port
Port
Port
Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. direct drive capability. N-channel open-drain input/output port pins. Input/output specifiable bit-wise. On-chip pull-up resistor used mask option. direct drive capability. Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software.
Port
Port
Port
P120 P127 Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software. P130, P131 Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software.
Port
µPD78058F(A)
Clock Generator
types generators, main system clock generator subsystem clock generator, avaibable. instruction execution time also changed. s/0.8 µs/1.6 s/3.2 µs/6.4 s/12.8 (main system clock: 5.0-MHz operation) (subsystem clock: 32.768-kHz operation) Figure 5-1. Clock Generator Block Diagram
XT1/P07 Subsystem Clock Oscillator Watch Timer, Clock Output Function Prescaler Main System Clock Oscillator Divider STOP Selector Prescaler Selector Standby Control Circuit Wait Control Circuit Clock (fCPU) Clock Peripheral Hardware
INTP0 Sampling Clock
Timer/event Counter channel channel channel channel Table 5-2. Types Functions Timer/Event Counter
16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer Watchdog Timer
PD78058F(A) incorporates channels timer/event counter. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Type Interval timer External event counter Function Timer output Pulse width measurement Square wave output One-shot pulse output Interrupt request Test input output output inputs output output outputs outputs input channel channel channels channels channel channel
µPD78058F(A)
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/2 TI00/P00/INTP0 Edge Detector Match Selector 16-Bit Timer Register (TM0) Clear
pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector INTTM01 INTP0
16-Bit Capture/ Compare Register (CR01)
Internal
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match fxx/2 fxx/29 fxx/211 TI1/P33 Selector 8-Bit Timer Register (TM1) Selector Clear 8-Bit Timer Register (TM2) Clear Selector fxx/211 TI2/P34 Selector
Output Control Circuit
TO2/P32 INTTM2
fxx/2 fxx/29
Output Control Circuit Internal
TO1/P31
µPD78058F(A)
Figure 5-4. Watch Timer Block Diagram
Selector XX/27 Selector Prescaler
5-Bit Counter Selector
INTWT
Selector
INTTM3 16-Bit Timer/ Event Counter
Figure 5-5. Watchdog Timer Block Diagram
Prescaler
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
µPD78058F(A)
Clock Output Control Circuit
clock with following frequency output clock output. 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 (main system clock: operation) 32.768 (subsystem clock: 32.768 operation) Figure 5-6. Clock Output Control Circuit Configuration
Selector Synchronization Circuit Output Control Circuit PCL/P35
Buzzer Output Control Circuit
clock with following frequency output buzzer output. kHz/2.4 kHz/4.9 kHz/9.8 (main system clock: 5.0-MHz operation)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
Selector Output Control Circuit BUZ/P36
µPD78058F(A)
Converter
converter 8-bit resolution channels incorporated. following types conversion operation start-up methods available. Hardware start Software start Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approximation Register (SAR) AVSS Selector AVSS Selector Sample Hold Circuit Voltage Comparator AVDD AVREF0
INTP3/P03
Edge Detection Circuit
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78058F(A)
Converter
converter 8-bit resolution channels available. Conversion method R-2R resistor ladder method.
Figure 5-9. Converter Block Diagram
AVREF1
ANOn
Selector DACSn Write AVSS INTTMX
Conversion Value Register (DACSn)
DAMm Converter Mode Register
Internal
Serial Interfaces
channels clocked serial interface incorporated. Serifal interface channel Serifal interface channel Serifal interface channel Table 5-3. Types Functions Serial Interface
Function 3-wired serial mode 3-wired serial mode with automatic transmission/reception function (serial interface) mode 2-wired serial mode Asynchronous serial interface (UART) mode (MSB first) (MSB first) Serial Interface Channel (MSB/LSB first switchable) Serial Interface Channel (MSB/LSB first switchable) (MSB/LSB first switchable) Serial Interface Channel (MSB/LSB first switchable)
(Dedicated baud rate generator incorporated)
µPD78058F(A)
Figure 5-10. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25 Selector SO0/SB1/P26 Serial Shift Register (SIO0) Output Latch
Selector
Release/Command/ Acknowledge Detection Circuit Serial Clock Counter
Busy/Acknowledge Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fXX/2-fXX/28 Serial Clock Control Circuit Selector
Figure 5-11. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial Shift Register (SIO1)
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
XX/2-f XX/28 Serial Clock Control Circuit Selector
µPD78058F(A)
Figure 5-12. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RxD/SI2/P70 TxD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX-fXX/210
Real-Time Output Port Functions
Data previously real-time output buffer register transferred output latch hardware concurrently with timer interrupt request external interrupt request generation order output off-chip. This real-time output function. pins output off-chip called real-time output ports. using real-time output port, signal which jitter output. This most applicable control stepping motor, etc. Figure 5-13. Real-Time Output Port Block Diagram
Internal
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Real-Time Output Buffer Register Buffer Register Higher Bits Higher Bits (RTBL) (RTBH) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
µPD78058F(A)
INTERRUPT FUNCTIONS TEST FUNCTIONS
Interrupt Functions Non-maskable Maskable Software Table 6-1. Interrupt Source List (1/2)
Interrupt Type Default Priority Note Interrupt Source Name INTWDT Trigger Watchdog timer overflow (watchdog timer mode selected) Watchdog timer overflow (interval timer mode selected) input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H serial interface channel transfer serial interface channel transfer Generation serial interface channel UART receive error serial interface channel UART reception serial interface channel 3-wire transfer serial interface channel UART transmission 001CH Internal 0014H 0016H 0018H Internal/ External Internal Vector Table Address 0004H Basic Configration Type Note
There interrupt functions three different sources, shown below.
Non-maskable
Maskable
INTWDT
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTSER
INTSR
001AH
INTCSI2
INTST
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest order lowest. Basic configuration types correspond Fig. 6-1, respectively.
µPD78058F(A)
Table 6-1. Interrupt Source List (2/2)
Interrupt Source Name INTTM3 Trigger Reference time interval signal from watch timer Generation match signal 16-bit timer register capture/compare register (CR00) Generation match signal 16-bit timer register capture/compare register (CR01) Generation match signal 8-bit timer/event counter Generation match signal 8-bit timer/event counter conversion converter instruction execution Vector Table Address 001EH Basic Configration Type
Note
Interrupt Type
Default Priority Note
Internal/ External Internal
Maskable
INTTM00
0020H
INTTM01
0022H
INTTM1
0024H
INTTM2
0026H
Software
INTAD
0028H 003EH
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78058F(A)
Figure 6-1. Interrupt Function Basic Configuration(1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detection Circuit
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78058F(A)
Figure 6-1. Interrupt Function Basic Configuration(2/2)
External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0)
Interrupt Request
Edge Detection Circuit
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag
In-service priority flag Interrupt mask flag Priority specification flag
µPD78058F(A)
Test Functions
There sources test function shown Table 6-2. Table 6-2. Test Input Source List
Test Input Source Internal/external Name INTWT INTPT4 Watch timer overflow Port falling edge detection Trigger Internal External
Figure 6-2. Test Function Basic Configuration
Internal
Test Input
Standby Release Signal
Test input flag Test mask flag
µPD78058F(A)
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than internal ROM, SFR. Ports used external device connection.
STANDBY FUNCTION
There following standby functions reduce system power consumption. HALT mode operating clock stopped. average consumption current reduced intermittent operation combination with normal operating mode. STOP mode main system clock oscillation stopped. whole operation main system clock stopped, that system operates with ultra-low power consumption using only subsystem clock. Figure 8-1. Stand-by Function
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation Note HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT Mode Note (Clock supply stopped, oscillation)
Note power consumption reduced stopping main system clock. When operating subsystem clock, bit7 (MCC) processor clock control register (PCC) stop main system clock. STOP instruction cannot used. Caution When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program. Remark
RESET FUNCTION
There following reset methods.
External reset input RESET Internal reset watchdog time runaway time detection
µPD78058F(A)
INSTRUCTION
8-bit instruction MOV, XCH, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand #byte
Byte]
Note
saddr
!addr16
[DE]
[HL]
$addr16
None
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
ADDC SUBC
saddr ADDC SUBC !addr16
DBNZ
DBNZ
PUSH
[DE] [HL]
ROR4 ROL4
Byte]
MULU DIVUW
Note Except
µPD78058F(A)
16-bit instruction MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second instruction First instruction
#word ADDW SUBW CMPW MOVW MOVW MOVW MOVW
Note MOVW XCHW
sfrp MOVW
saddrp MOVW
!addr16 MOVW
MOVW
None
sfrp saddrp !addr16
MOVW Note MOVW MOVW MOVW MOVW
INCW, DECW PUSH,
Note Only when manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second instruction First instruction A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
MOV1
$addr16 BTCLR BTCLR BTCLR BTCLR BTCLR
None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
Call instruction/branch instruction CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second instruction First instruction Basic instruction Compound instruction
!addr16 CALL
!addr11 CALLF
[addr5] CALLT
$addr16 BTCLR DBNZ
µPD78058F(A)
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78058F(A)
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, XT2, RESET N-ch Open-drain Test Conditions Rating -0.3 +7.0 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Output voltage Analog input voltage High level output current
-0.3 -0.3
Analog input
AVSS AVREF0
P06, P37, P56, P57, P67, P120 P127 total P17, P27, P47, P55, P72, P130, P131 total
level output current
Note
Peak value Effective value
total
Peak value Effective value
P56, P57, total
Peak value Effective value
P17, P27, P47, P72, P130, P131 total P06, P37, P67, P120 P127 total Operating ambient temperature Storage temperature
Peak value Effective value Peak value Effective value
Tstg
+150
Note Effective value should calculated follows: [Effective value] [Peak value] duty Caution Product quality suffer absolute maximum rating exceeded even single parameter even momentarily. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded. Remark Unless specified otherwise, alternate characteristics same port characteristics.
µPD78058F(A)
MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS
Recommended Circuit
Resonator Ceramic resonator
Parameter Oscillator frequency (fX) Note Oscillation stabilization time Oscillator frequency (fX)
Test Conditions Oscillator voltage range After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Note
Crystal resonator
Note
Oscillation stabilization time input frequency (fX)
Note
External clock
Note
µPD74HCU04
input high/low level width (tXH
Notes Indicates only oscillation circuit characteristics. Refer CHARACTERISTICS" instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wiring area enclosed with broken line above figures should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78058F(A)
SUBSYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS +85°C,
Recommended Circuit
Resonator Ceramic resonator
Parameter Oscillator frequency (fXT
Test Conditions
MIN.
TYP.
MAX.
Unit
Note
32.768
Oscillation stabilization time input frequency (fXT
Note
External clock
Note
input high/low level width (tXTH XTL)
Notes Indicates only oscillation circuit characteristics. execution time.
Refer CHARACTERISTICS" instruction
Time required stabilize oscillation after reaches oscillator voltage MIN. Cautions When using subsystem clock oscillator, wiring area enclosed with broken line above figures should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator. subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone mulfunction noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD78058F(A)
CAPACITANCE 25°C,
Parameter Input capacitance Input/Output Symbol Test Conditions Measured pins retured Measured pins retured P06, P27, P47, P67, P120 P127, P130, P131 P17, P37, P57, P72, MIN. TYP. MAX. Unit
Remark Unless specified otherwise, alternate characteristics same port characteristics.
µPD78058F(A)
CHARACTERISTICS +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET (N-ch Open-drain) XT1/P07, MIN. TYP. MAX. Unit
VIH2 VIH3 VIH4 VIH5
Input voltage,
VIL1
P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET
VIL2 VIL3
VIL4 VIL5
XT1/P07,
Output voltage, high Output voltage,
-100
VOL1
P57, P06, P27, P47, P72, P130, P131 P17, P37, P67, P120 P127,
VOL2
SB0, SB1, SCK0
N-ch open-drain pull-up time
VOL3 Input leakage current, high LIH1
P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07,
LIH2 LIH3
Remark Unless specified otherwise, alternate characteristics same port characteristics.
µPD78058F(A)
CHARACTERISTICS
Parameter Input leakage current, Symbol LIL1 Test Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, VOUT VOUT P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
LIL2 LIL3 Output leakage current, high Output leakage current, Mask option pull-up resistor Software pull-up resistor
Note
Note When pull-up resistor included (specified mask option), -200 (MAX.) lowlevel input leakage current passed only clock interval wait) read instruction port6 (PM6) port mode register (PM6) executed. Other than interval, (MAX.) passed. Remark Unless specified otherwise, alternate characteristics same port characteristics.
µPD78058F(A)
CHARACTERISTICS +85°C,
Parameter Power supply current Note Symbol
IDD1
Test Conditions Crystal oscillation operating mode (fXX MHz) Note Crystal oscillation operating mode (fXX MHz) Note Note
Note
MIN.
TYP. 0.65 0.05
MAX. 19.5 1.95
Unit
Note Note
Crystal oscillation HALT mode (fXX MHz) Note Crystal oscillation HALT mode (fXX MHz) Note
32.768 Crystal oscillation operating mode Note 32.768 Crystal oscillation HALT mode Note STOP mode When feedback resister used STOP mode When feedback resister unused
Notes Passed through AVDD pins. include current which passed through converter, converter, on-chip pull-up resistor. operation (when oscillation mode selection register (OSMS) 00H) operation (when OSMS 01H) When main system clock stopped High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H) Remarks Main system clock frequency fX/2) Main system clock oscillator frequency
µPD78058F(A)
CHARACTERISTICS BASIC OPERATION +85°C,
Parameter Cycle time (Min. instruction execution time) Operating subsystem clock TI00 input high/ level width TI01 input high/ level width TI1, input frequency TI1, input high/low level width Interrupt input high/low level width RESET level width TIH1, TIL1 TIH00, TIL00 TIH01, TIL01 Symbol Operating main system clock Test Conditions fX/2Note fXNote MIN. Note Note INTP0 Note INTP1 INTP6,
Note
TYP.
MAX.
Unit
INTH, INTL
Notes When oscillation mode selection register When oscillation mode selection register combination with bits (SCS0) (SCS1) sampling clock select register (SCS), selection fsam possible between fXX/2 /32, fXX/64 /128 (when Remarks fXX: Main system clock frequency fX/2) Main system clock oscillation frequency
µPD78058F(A)
main system clock operation) main system clock operation)
Cycle Time Operation Guaranteed Range Cycle Time
Operation Guaranteed Range
Supply Voltage
Supply Voltage
µPD78058F(A)
READ/WRITE OPERATION When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol Test Conditions ASTH ADD1 ADD2 Data input time from RDD1 RDD2 Read data hold time low-level width RDL1 RDL2 WAIT input time from RDWT1 RDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT WRWT ASTRD ASTWR RDAST RDADH RDWD RDWD
WRADH
MIN. 0.85t 0.85t
MAX.
Unit
(2.85 2n)tCY 2n)tCY 2n)tCY (2.85 2n)tCY 2n)tCY (2.85 2n)tCY 0.85t 2tCY 2tCY (1.15 2n)tCY (2.85 2n)tCY (2.85 2n)tCY 0.85tCY 0.85tCY 0.85t 0.85tCY 1.15tCY 1.15tCY 1.15t 3.15t 3.15t 1.15t 1.15t 2n)tCY
WTRD WTWR
Remarks MCS: Oscillation mode selection register PCC2 PCC0: Processor clock control register TCY/4 indicates number waits.
µPD78058F(A)
When except PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol ASTH ADD1 ADD2 Data input time from RDD1 RDD2 Read data hold time low-level width RDL1 RDL2 WAIT input time from RDWT1 RDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT RDWD RDWD
tWRADH
Test Conditions
MIN. 0.4t
MAX.
Unit
2n)tCY 2n)tCY (1.4 2n)t (2.4 2n)t (1.4 2n)tCY (2.4 2n)tCY 2tCY 2tCY 2n)tCY (2.4 2n)tCY (2.4 2n)tCY 0.4t 1.4t 0.4t 0.6t 0.6t 2.6tCY 2.6tCY 2n)tCY
WRWT ASTRD ASTWR RDAST RDADH
WTRD WTWR
Remarks MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register CY/4 indicates number waits.
µPD78058F(A)
SERIAL INTERFACE Serial interface channel 3-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time
Symbol tKCY1
Test Conditions
MIN. 1600
TYP.
MAX.
Unit
SCK0 high/low-level width setup time SCK0) hold time (from SCK0) output delay time from SCK0
tKH1,
KCY1/2 tKCY1/2
tSIK1
tKSI1 Note
tKSO1
Note load capacitance SCK0 output line. (ii) 3-wire serial mode (SCK0. Internal clock input)
Parameter SCK0 cycle time
Symbol KCY2
Test Conditions
MIN. 1600
TYP.
MAX.
Unit
SCK0 high/low-level width setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time
KH2, tKL2
SIK2 KSI2 Note When using external device expansion function When using external device expansion function
1000
tKSO2
tR2,
Note load capacitance output line.
µPD78058F(A)
(iii) mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol KCY3 Test Conditions MIN. 3200 SCK0 high/low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) KH3, tKL3 tKCY3/2 KCY3/2 SIK3 KSI3 Note KCY3/2 KCY3 KCY3 KCY3 KCY3 1000 TYP. MAX. Unit
SB0, output tKSO3 delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width
Note load resistors load capacitance SCK0, SB0, output line.
µPD78058F(A)
(iv) mode (SCK0. Internal clock input)
Parameter SCK0 cycle time Symbol KCY4 Test Conditions MIN. 3200 SCK0 high/low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output tKSO4 delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width SCK0 rise, fall time When using external device expansion function When using external device expansion function Note KCY4 KCY4 KCY4 KCY4 1000 1000 KH4, tKL4 1600 SIK4 KSI4 tKCY4/2 TYP. MAX. Unit
Note load resistors load capacitance output line.
µPD78058F(A)
2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol KCY5 Note Test Conditions MIN. KCY5/2 tKCY5/2 KCY5/2 SB0, setup time SCK0) SB0, hold time (from SCK0) SIK5 KSI5 TYP. MAX. Unit
SCK0 high-level width SCK0 low-level width
SB0, output tKSO5 delay time from SCK0
Note load resistors load capacitance SCK0, SB0, output line. (vi) 2-wire serial mode (SCK0. Internal clock input)
Parameter SCK0 cycle time SCK0 high-level width Symbol tKCY6 tKH6 Test Conditions MIN. 1600 KCY6/2 tR6,
Note
TYP.
MAX.
Unit
SCK0 low-level width tKL6 SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time tSIK6 tKSI6
tKSO6
1000
When using external device expansion function When using external device expansion function
Note load resistors load capacitance output line.
µPD78058F(A)
Serial interface channel 3-wire serial mode (SCK1.Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 SCK1 high/low-level width tKH7, KCY7/2 KCY7/2 setup time SCK1) tSIK7 hold time (from SCK1) output delay time from SCK1 tKSI7
tKSO7
TYP.
MAX.
Unit
Note
Note load capacitance SCK1 output line. (ii) 3-wire serial mode (SCK1.External clock output)
Parameter SCK1 cycle time Symbol KCY8 Test Conditions MIN. 1600 SCK1 high/low-level width KH8, tKL8 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time When using external device expansion function When using external device expansion function 1000 SIK8 KSI8
KSO8
TYP.
MAX.
Unit
Note
Note load capacitance output line.
µPD78058F(A)
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 SCK1 high/low-level width tKH9, KCY9/2 KCY9/2 setup time SCK1) tSIK9 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tSPS tKSI9
tKSO9
TYP.
MAX.
Unit
Note
KCY9/2 KCY9/2 tKCY9/2 tKCY9/2
tSBD
tSBW
tBYS
tBYH
2tKCY9
Note load capacitance SCK1 output line. (iv) 3-wire serial mode with automatic transmit/receive function (SCK1. External clock output)
Parameter SCK1 cycle time Symbol KCY10 Test Conditions MIN. 1600 SCK1 high/low-level width KH10, KL10 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time SIK10 KSI10
tKSO10
TYP.
MAX.
Unit
Note
1000
tR10,
When using external device expansion function When using external device expansion function
Note load capacitance output line.
µPD78058F(A)
Serial interface channel 3-wire serial mode (SCK2.Internal clock output)
Parameter SCK2 cycle time Symbol KCY11 Test Conditions MIN. 1600 SCK2 high/low-level width KH11, KL11 KCY11/2 tKCY11 setup time SCK2) SIK11 hold time (from SCK2) output delay time from SCK1 KSI11
tKSO11
TYP.
MAX.
Unit
Note
Note load capacitance SCK2 output line. (ii) 3-wire serial mode (SCK2.External clock output)
Parameter SCK2 cycle time Symbol KCY12 Test Conditions MIN. 1600 SCK2 high/low-level width KH12 tKL12 setup time SCK2) hold time (from SCK2) output delay time from SCK2 SCK2 rise, fall time SIK12 KSI12
KSO12
TYP.
MAX.
Unit
Note
1000
R12, tF12
When using external device expansion function
Note load capacitance output line.
µPD78058F(A)
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 Unit
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol KCY13 Test Conditions MIN. 1600 ASCK high-/low-level width KH13, KL13 Transfer rate 39063 19531 ASCK rise, fall time R13, When using external device expansion function 1000 TYP. MAX. Unit
µPD78058F(A)
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
Input
1/fXT
tXTL Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI tTIL1 tTIH1
TI1,
µPD78058F(A)
Read/Write Operation External Fetch Wait)
Lower 8-Bit Address tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External Fetch (Wait Insertion)
Lower 8-Bit Address tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78058F(A)
External Data Access Wait)
Lower 8-Bit Address tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWDWR tASTWR tWRL tWRADH tWDS tWDH
External Data Access (Wait Insertion)
Lower 8-Bit Address tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWRWD tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78058F(A)
Serial Transfer Timing 3-wire Serial Mode
tKCYm tKLm SCK0 SCK2 tSIKm tKSIm tKHm
tKSOm
Input Data
Output Data
Mode (Bus Release Signal Transfer)
tKCY3,4 tKL3,4 SCK0 tKSB tSBL tSBH tSBK tSIK3,4 tKSI3, tKH3,4
SB0, tKSO3,4
Mode (Command Signal Transfer)
tKCY3,4 tKL3,4 tKH3,4
SCK0 tKSB tSBK tSIK3,4 tKSI3,4
SB0, tKSO3,4
µPD78058F(A)
2-wire Serial Mode
tKCY5,6 tKL5,6 SCK0 tSIK5,6 tKSO5,6 SB0, tKSI5,6 tKH5,6
3-wire Serial Mode with Automatic Transmit/Receive Function
tSIK9,10
tKSI9,10 tKH9,10
tKSO9, SCK1
tR10
tF10
tKL9,10 tKCY9,10
tSBD
tSBW
3-wire Serial Mode with Automatic Transmit/Receive Function (Busy processing)
SCK1
Note
Note tBYS
10+n Note tBYH tSPS
BUSY (Active high)
Note signal actually driven here; shown such indicate timing.
µPD78058F(A)
UART Mode (External Clock Input)
KCY13 KL13 tR13 KH13 tF13
ASCK
CONVERTER CHARACTERISTICS +85°C, AVDD
Parameter Resolution Overall error
Note
Symbol
Test Conditions AVREF0 AVDD
MIN.
TYP.
MAX.
Unit
Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 AVSS
tCONV SAMP VIAN AVREF0 RAIREF0
19.1 12/fXX AVSS
AVREF0 AVDD
Note Overroll error excluding quantization error (±1/2 LSB). indicated ratio full-scale value. Caution pins which also function port pins (refer section Port Pins), perform following operations during conversion. these operations performed, total error ratings cannot kept (except segment output alternate-function pin). Rewrite output latch while used port pin. Change output level used output pin, even used port pin.
Remarks Main system clock frequency fX/2) Main system clock oscillation frequency CONVERTER CHARACTERISTICS +85°C, AVSS
Parameter Resolution Overall error Note
Note Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Settling time
Note AVREF1 AVREF1
Output resistance Analog reference voltage Resistance between REF1 AVSS
AVREF1 RAIREF1
Note DACS0, DACS1 Note
Notes denote converter output load resistance load capacitance, respectively. Value converter channel Remark DACSO, DACS1: conversion value setting register
µPD78058F(A)
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS +85°C)
Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR IDDDR VDDDR Subsystem clock stop feed-back resister disconnected Release RESET Release interrupt Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Release signal time Oscillation stabilization wait time
tSREL tWAIT
Note combination with bits (OSTS0 OSTS2) oscillation stabilization time select register, selection 212/fXX 214/f 217/f possible. Remark fXX: Main system clock frequency fX/2)
Main system clock oscillatior frequency
Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78058F(A)
Interrupt Input Timing
tINTL INTP0 INTP6
tINTH
RESET Input Timing
tRSL
RESET
µPD78058F(A)
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-4
Remark Dimensions materials product same those mass-production products.
µPD78058F(A)
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (C10535E). soldering methods conditions other than those recommended below, contact sales personnel. Table 13-1. Surface Mounting Type Soldering Conditions-
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Three times max. Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Three times max. Solder bath temperature 260°C max., Duration sec. max., Number times: once, Preheating temperature 120°C max. (package surface temperature) temperature: 300°C max. Duration: sec. max. (per device side) Recommended Condition Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
part heating
Caution
more than soldering method should avoided (except case partial heating).
µPD78058F(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using PD78058F(A). Language Processing Software
RA78K/0 Note CC78K/0 Note DF78054
Note Note
Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file common µPD78054 Subseries compiler library source file common 78K/0 Series
CC78K/0-L
PROM Writing Tools
PG-1500 PA-78P054GC PG-1500 controller
Note
PROM programmer Programmer adapters connected PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM IE-780308-R-EM EP-78230GC-R EV-9200GC-80 SM78K0 ID78K0
Note
In-circuit emulator common 78K/0 Series 78K/0 series common in-circuit emulator (for integrated debugger) Break board common 78K/0 Series Emulation board common PD78064 Subseries Emulation board common PD780308 Subseries Emulation probe common PD78234 Subseries Socket mounted target system board manufactured 80-pin plastic (GC-3B9 type) System simulator common 78K/0 Series Integrated debugger IE-78000-R IE-78000-R screen debugger
Note
SD78K/0 DF78054
Note Note
µPD78054 Subseries device file
Notes PC-9800 series (MS-DOS) based PC/ATand compatibles DOS/IBM DOS/MS-DOS) based HP9000 series 300(HP-UX based HP9000 series 700(HP-UX) based, SPARCstation (SunOS) based, EWS4800 series (EWS-UX/ based PC-9800 series (MS-DOS Windows) based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OS) based Remarks third party development tools, 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0 used combination with DF78054.
µPD78058F(A)
Real-Time
RX78K/0 Note MX78K/0
Note
Real-time 78K/0 Series Real-time 78K/0 Series
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200 Note Fuzzy knowledge data creation tool FT9080 Note 1/FT9085 Note Translator FI78K/0
Note
Fuzzy inference module Fussy inference debugger
FD78K/0
Note
Notes PC-9800 series (MS-DOS based PC/ATand compatibvles DOS/IBM DOSTM/MS-DOS) based HP9000 series (HP-UX) based HP9000 series (HP-UX) based, SPARCstation (SunOS) based, EWS4800 series (EWS-UX/ based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) based Remarks third party development tools, 78K/0 Series Selection Guide (U11126E). RX78K/0 used combination with DF78054.
µPD78058F(A)
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document (English) Under development This document Under development IEU-1372 Document (Japanese) U12068J U12325J U11796J IEU849 U10904J U10903J
Document Name
PD78058F, 78058FY Subseries User's Manual PD78058F(A) Data Sheet PD78P058F Data Sheet
78K/0 Series User's Manual, Operation 78K/0 Series Instruction 78K/0 Series Instruction Table
Caution
above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78058F(A)
Development Tool Related Documents (User's Manual)
Document (English) Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly language Structured assembly language CC78K Series Compiler Operation Language CC78K/0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) based PG-1500 Controller series DOS) based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM IE-780308-R-EM EP-78230 SM78K0 System Simulator, Windows based SM78K Series System Simulator ID78K0 Integrated Debugger, based ID78K0 Integrated Debugger, based ID78K0 Integrated Debugger, Windows based SD78K/0 Screen Debuffer PC-9800 Series (MS-DOS) based SD78K/0 Screen Debugger PC/AT DOS) based Reference External parts user open interface specification Reference Reference Guide Introduction Reference Introduction Reference Programming know-how EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 EEU-1443 U11362E EEU-1515 U10181E U10092E U11539E U11649E U10539E EEU-1414 U11279E Document (Japanese) EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 EEU-777 U11940J EEU-704 EEU-5008 EEU-810 U10057J EEU-867 EEU-905 U11362J EEU-985 U10181J U10092J U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
Document Name RA78K Series Assembler Package
Caution
above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78058F(A)
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real-time Basics Installation RA78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-1441 EEU-1458 EEU-858 EEU-921 Basics Document (English) EEU-1438 EEU-1444 Document (Japanese) U11537J U11536J EEU-5010 EEU-829 EEU-862
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Microcontroller Related Product Guide Third Party Document (English) C10943X C10535E C11531E C10983E MEI-1202 C10535J C11531J C10983J MEM-539 C11893J C11416J Document (Japanese)
Caution
above related documents subject change without notice. design purpose, etc., sure latest documents.
µPD78058F(A)
[MEMO]
µPD78058F(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78058F(A)
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78058F(A)
IEBus trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 series 300, HP9000 series, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NES-OS trademarks Sony Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD78058F(A) 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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