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µPD78062(A), 78063(A), 78064(A) 8-BIT SINGLE-CHIP MICROCONTROLLER


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INTEGRATED CIRCUIT
µPD78062(A), 78063(A), 78064(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD78062(A), 78063(A), 78064(A) 8-bit single-chip microcontrollers based µPD78062, 78063, 78064, respectively. device groups differ only quality assurance program defined NEC, with assurance program applied µPD78062(A), 78063(A), 78064(A) (called special grade) being stricter than that other devices (standard grade). µPD78062(A), 78063(A), 78064(A) members µPD78064 subseries 78K/0 series. These devices contain controller/driver, 8-bit resolution converters, timers, serial interface units, interrupt controller, other powerful peripheral hardware. one-time PROM version, EPROM version, various development tools these devices also available. one-time PROM EPROM versions operate same power supply voltage range accurate evaluation. detailed descriptions functions, refer following user's manuals. µPD78064 78064Y Subseries User's Manual IEU-1364 78K/0 Series User's Manual (Instruction) IEU-1372
FEATURES
Large on-chip
Item Part Number µPD78062(A) µPD78063(A) µPD78064(A) Program Memory (ROM) Kbytes Kbytes Kbytes Data Memory Internal High-Speed bytes 1024 bytes bits Display Package 100-pin plastic (fine pitch) 0.5-mm pitch) 100-pin plastic 0.65-mm pitch)
Instruction execution time varied from high speed (0.4 ultra-low speed (122 ports: (including segment signal output dual-function pins) controller/driver Supply voltages (Static display mode) (1/3 bias) (1/2 bias) 8-bit resolution converter channels Serial interface channels Timer: channels Supply voltage
information this document subject change without notice. Document U10335EJ1V0DS00 (1st edition) Date Published September 1995 Printed Japan
1992 1995
µPD78062(A), 78063(A), 78064(A)
related documents this publication include preliminary versions. However, preliminary versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customer must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact Sales Representative advance. Anti-radioactive design implemented this product.
94.11
IEBus trademarks Corporation. MS-DOS Windows trademarks Microsoft Corporation. PC/AT trademarks Corporation. HP9000 series 300, HP9000 series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc.
µPD78062(A), 78063(A), 78064(A)
APPLICATIONS
Control devices transport system, detector circuit-breakers, safety devices, sphygmomanometer, etc.
ORDERING INFORMATION
Part Number µPD78062GC (A)-xxx-7EA µPD78062GF (A)-xxx-3BA µPD78063GC (A)-xxx-7EA µPD78063GF (A)-xxx-3BA µPD78064GC (A)-xxx-7EA µPD78064GF (A)-xxx-3BA Remark Package 100-pin plastic (Fine pitch) 100-pin plastic 100-pin plastic 100-pin plastic 100-pin plastic (Fine pitch) (Fine pitch) Quality Grade Special Special Special Special Special Special
100-pin plastic
code suffix.
Please refer "Quality grade Semiconductor Devices" (Document number IEI-1209) published Corporation know specification quality grade devices recommended applications. Difference between µPD78062(A)/78063(A)/78064(A) µPD78062/78063/78064
Part number µPD78062(A), 78063(A), 78064(A) Item Quality grade Special µPD78062, 78063, 78064 Standard
µPD78062(A), 78063(A), 78064(A)
78K/0 SERIES LINE-UP
following shows products 78K/0 Series organized according their functions. names parallelograms subseries names.
Products mass production Products under development subseries bus. control pins pins pins pins pins pins pins 42/44 pins 78K/0 series µPD78078 µPD78070A µPD78054 µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 FIPdriving pins pins pins µPD780208 µPD78044A µPD78024 µPD78044A with enhanced I/O, C/D, display output total: µPD78024 with 6-bit counter added, display output total: Basic subseries driving, display output total: µPD78078Y µPD78070AY µPD78054Y µPD78018FY µPD78014Y µPD78002Y µPD78054 with timer added enhanced external interface ROM-less version µPD78078 µPD78014 with UART added, enhanced
Enabled low-voltage operation increased RAM, size options based µPD78014
µPD78002 with A/D, 16-bit timer added µPD78002 with added Basic subseries control On-chip UART, low-voltage (1.8 operation possible
pins
driving µPD78064 µPD78064Y IEBus
Subseries driving, on-chip UART
pins pins
µPD780908 µPD78098
µPD78098 with enhanced µPD78054 with IEBus controller added
following lists main functional differences among 78K/0 Series products.
Timer 8-bit 16-bit Watch
Function Subseries control µPD78078 µPD78070A µPD78054
Capacity
8-bit
8-bit
Serial Interface (UART:1ch)
MIN. Value
External Expansion
µPD78018F µPD78014
µPD780001 µPD78002 µPD78083 driving µPD780208 µPD78044A µPD78024 driving IEBus µPD780908 µPD78098 µPD78064
(UART:1ch)
(UART:1ch)
(UART:1ch)
µPD78062(A), 78063(A), 78064(A)
OVERVIEW FUNCTION
Part Number Item Internal memory Internal high-speed display
µPD78062 Kbytes bytes
µPD78063 Kbytes 1024 bytes bits
µPD78064 Kbytes
General registers Instruction cycle When main system clock selected When subsystem clock selected
bits registers bits registers banks) Instruction execution time variable µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 5.0MHz operation) 32.768 operation) 16-bit operation
Instruction
Multiply/divide bits bits,16 bits/8 bits) manipulate (set, reset, test, boolean operation) adjust, etc. Total CMOS input CMOS 8-bit resolution channels Segment signal output Maximum Maximum switchable channel channel channel channels channel channel Common signal output Bias
ports (including segment signal output pins) converter controller/driver
Serial interface
3-wire/SBI/2-wire mode selectable 3-wire/UART mode selectable 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Timer
Timer output
(14-bit output capability 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz,
Clock output
main system clock 5.0-MHz operation) 32.768 subsystem clock 32.768-kHz operation)
Buzzer output Maskable interrupts Vectored interrupts Non-maskable interrupts Software interrupts Test input Supply voltage Package
kHz, kHz, kHz, main system clock 5.0-MHz operation) Internal external Internal
Internal Internal external: 100-pin plastic (Fine pitch) 100-pin plastic
µPD78062(A), 78063(A), 78064(A)
CONTENTS
CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS
PORT PINS NON-PORT PINS CIRCUITS RECOMMENDED CONNECTION UNUSED PINS
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURE
PORT CLOCK GENERATOR TIMER/EVENT COUNTER CLOCK OUTPUT CONTROL CIRCUIT BUZZER OUTPUT CONTROL CIRCUIT CONVERTER SERIAL INTERFACE CONTROLLER/DRIVER
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS TEST FUNCTIONS
STANDBY FUNCTION RESET FUNCTION INSTRUCTION
ELECTRICAL SPECIFICATIONS CHARACTERISTIC CURVES (REFERENCE VALUES) PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78062(A), 78063(A), 78064(A)
CONFIGURATION (TOP VIEW)
100-pin plastic (Fine pitch) µPD78062GC (A)-xxx-7EA, 78063GC-xxx-7EA µPD78064GC (A)-xxx-7EA
P72/SCK2/ASCK
P113 P112 P111 P110 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET
P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 AVDD AVREF P100 P101 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ COM0 COM1 COM2
P71/SO2/TXD
P10/ANI0
XT1/P07
AVSS P117 P116 P115 P114
P70/SI2/RXD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24
COM3 BIAS VLC0
VLC1 VLC2
Cautions Connect directly (Internally Connected) VSS. Connect AVDD VDD. Connect AVSS VSS.
µPD78062(A), 78063(A), 78064(A)
100-pin plastic µPD78062GF (A)-xxx-3BA, 78063GF (A)-xxx-3BA µPD78064GF (A)-xxx-3BA
P25/SI0/SB0
P80/S39 P81/S38 P82/S37 P83/S36 P84/S35
P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24
P26/SO0/SB1 P27/SCK0 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK XT1/P07 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P110 P111 P112 P113 P114 P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2
VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0
P16/ANI6 P17/ANI7 AVDD
AVREF P100 P101
P13/ANI3 P14/ANI4 P15/ANI5
P102 P103
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ
Cautions Connect directly (Internally Connected) VSS. Connect AVDD VDD. Connect AVSS VSS.
µPD78062(A), 78063(A), 78064(A)
P05, Port0 Port1 Port2 Port3 Port7 Port8 Port9 Port10 Port11 Interrupt from Peripherals Timer Input Timer Input Timer Output Serial Serial Input Serial Output Serial Clock Receive Data Transmit Data Asynchronous Serial Clock Programmable Clock Buzzer Clock
P100 P103 P110 P117 INTP0 INTP5 TI00, TI01 TI1, SB0, SI0, SO0, SCK0, SCK2 ASCK
COM0 COM3 VLC0 VLC2 BIAS XT1, RESET ANI0 ANI7 AVDD AVSS AVREF
Segment Output Common Output Power Supply Power Supply Bias Control Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Analog Input Analog Power Supply Analog Ground Analog Reference Voltage Power Supply Ground Internally Connected
µPD78062(A), 78063(A), 78064(A)
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33
16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER
PORT1
TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER
PORT2
PORT3 WATCHDOG TIMER PORT7 WATCH TIMER
PORT8 78K/0 CORE
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE
PORT9
PORT10 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 SERIAL INTERFACE PORT11
P100 P103
P110 P117
ANI0/P10 ANI7/P17 AVDD AVSS AVREF INTP0/P00 INTP5/P05 CONVERTER CONTROLLER/ DRIVER INTERRUPT CONTROL S24/P97 S31/P90 S32/P97 S39/P80 COM0 COM3 VLC0 VLC2 BIAS fLCD RESET XT1/P07
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT CONTROL
SYSTEM CONTROL
Remark internal capacities vary depending product.
µPD78062(A), 78063(A), 78064(A)
FUNCTIONS
PORT PINS (1/2)
Alternate Name
Note
Input
Function Input only
After Reset Input
function INTP0/TI00 INTP1/TI01
Input/ output
Port 7-bit port.
Input/output specified bit-wise. When used input port, pull-up resistor connected software. Input
INTP2 INTP3 INTP4 INTP5
Input Port
Input only
Input
Input/ output
8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor connected software.
Note
ANI0 Input ANI7
Input/ output Input/ output Input/ output
Port 3-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor connected software. Input
SI0/SB0 SO0/SB1 SCK0
Port 8-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor connected software. Input
Port 3-bit input/output port. Input/output specified bit-wise. When used input port, pull-up resistor connected software. Input
SI2/RxD SO2/TxD SCK2/ ASCK
Notes
When using P07/XT1 pins input port, (FRC) processor clock control register. (the on-chip feedback resistor subsystem clock oscillator should used.) When using P10/ANI0 P17/ANI7 pins converter analog input, port input mode. However, pull-up resistor automatically disabled.
µPD78062(A), 78063(A), 78064(A)
PORT PINS (2/2)
Name
Port 8-bit input/output port
Function
Alternate After Reset function
Input/ output
Input/output specified bit-wise. When used input port pull-up resistor connected software. Input/output port/segment signal output function specified 2-bit unit control register. Port 8-bit input/output port Input/output specified bit-wise. When used input port, pull-up resistor connected software. Input/output port/segment signal output function specified 2-bit unit control register. Port 4-bit input/output port Input Input
Input/ output
P100 P103
Input/ output
Input/output specified bit-wise. When used input port, pull-up resistor connected software. direct drive capability. Port 8-bit input/output port
Input
P110 P117
Input/ output
Input/output specified bit-wise. When used input port, pull-up resistor connected software. Falling edge detection capability.
Input
µPD78062(A), 78063(A), 78064(A)
NON-PORT PINS (1/2)
Alternate
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5
Function
After Reset
function P00/TI00 P01/TI01
External interrupt input which effective edge (rising edge, Input falling edge, both rising edge falling edge) specified. Input
Input SCK0 SCK2 ASCK TI00 TI01 Input COM0 COM3 VLC0 VLC2 BIAS Output Output Output Output Output Input/ output Input/ output Input Output Input Output
Serial interface serial data input.
Input
P25/SB0 P70/RxD
Serial interface serial data output.
P26/SB1 Input P71/TxD P25/SI0 P26/SO0
Serial interface serial data input/output.
Input
Serial interface serial clock input/output. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input 16-bit timer (TM0). Capture trigger signal input capture register (CR00). External count clock input 8-bit timer (TM1). External count clock input 8-bit timer (TM2). 16-bit timer output (shared with 14-bit output). 8-bit timer output. Clock output (for main system clock, subsystem clock trimming). Buzzer output.
Input Input Input Input
P72/ASCK P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1
Input Input Input Input Output
controller/driver segment signal output. Input
controller/driver common signal output. drive voltage. Split resistors incorporated mask option. drive power supply.
Output
µPD78062(A), 78063(A), 78064(A)
NON-PORT PINS (2/2)
Input Input converter analog input. converter reference voltage input. converter analog power supply. Connect VDD. converter ground potential. Connect VSS. Input Input Main system clock oscillation crystal connection. Positive power supply. Ground potential. Internal connection. Connect directly pin. Input Subsystem clock oscillation crystal connection. System reset input. Function After Reset Input Input Alternate function
Name ANI0 ANI7 AVREF AVDD AVSS RESET
CIRCUITS RECOMMENDED CONNECTION UNUSED PINS input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1. Table 3-1. Input/Output Circuit Type Each (1/2)
Input/output Circuit Type
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 P17/ANI7 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2
Input
Recommended Connection when Used Connected
Input/output
Independently connected through resistor.
Input
Connected
10-A Input/output Independently connected through resistor.
µPD78062(A), 78063(A), 78064(A)
Table 3-1. Input/Output Circuit Type Each (2/2)
Input/output Name P33/TI1 P34/TI2 P35/PCL P36/BUZ P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P80/S39 P87/S32 P90/S31 P97/S24 P100 P103 P110 P117 COM0 COM3 VLC0 VLC2 BIAS RESET AVREF AVDD AVSS Input Leave open. Connected Connected Connected Connected directly 17-A Output Leave open. Independently connected through resistor. Input/output Independently connected through resistor. Circuit Type Recommended Connection when Used
µPD78062(A), 78063(A), 78064(A)
Figure 3-1. Input/Output Circuits (1/2)
Type Type
pullup enable data P-ch IN/OUT output disable
Schmitt-Triggered Input with Hysteresis Characteristic
P-ch
N-ch
Type
Type 10-A
pullup enable data P-ch IN/OUT output disable N-ch open drain output disable N-ch data
pullup enable P-ch IN/OUT
P-ch
P-ch
input enable
Type
pullup enable data
P-ch P-ch IN/OUT
output disable Comparator
N-ch P-ch
N-ch VREF (Threshold Voltage) input enable
µPD78062(A), 78063(A), 78064(A)
Figure 3-1. Input/Output Circuits (2/2)
Type Type 17-A
feedback cut-off P-ch pullup enable data P-ch IN/OUT output disable input enable VLC0 P-ch
Type
P-ch
N-ch
VLC1 N-ch P-ch P-ch data P-ch P-ch N-ch VLC2 N-ch N-ch
VLC0 VLC1 N-ch data P-ch VLC2 N-ch
Type
VLC0 P-ch VLC1 N-ch N-ch P-ch
data P-ch VLC2 N-ch
N-ch
P-ch
µPD78062(A), 78063(A), 78064(A)
MEMORY SPACE
memory µPD78062(A)/78063(A)/78064(A) shown Figure 4-1.
Figure 4-1. Memory
FFFFH
Special Function Register (SFR) Bits
FF00H FEFFH FEE0H
General Registers Bits
Internal High-Speed RAMNote
mmmmH mmmmH-1 Data Memory Space FA80H FA7FH Display Bits FA58H FA57H Reserved Reserved
nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH Program Area 0080H 007FH CALLT Table Area 0040H 003FH Vector Table Area
nnnnH+1 nnnnH
Program Memory Space
Internal ROMNote
0000H
0000H
Note
capacity internal internal high-speed differs according product. (refer following table.)
Part Number µPD78062(A) µPD78063(A) µPD78064(A) Last Address Internal nnnnH 3FFFH 5FFFH 7FFFH Start Address Internal High-Speed mmmmH FD00H FB00H
µPD78062(A), 78063(A), 78064(A)
PERIPHERAL HARDWARE FUNCTION FEATURE
PORT
There kinds ports. CMOS input (P00, P07) CMOS input/output (P01 P05, Port Total
Table 5-1. Functions Ports
Name
Name P00, Dedicated input port
Function
Port
Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port. Input/output specifialbe bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port/segment signal output function specifiable 2-bit units control register. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Input/output port/segment signal output function specifiable 2-bit units control register. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Direct drive capability. Input/output port. Input/output specifiable bit-wise. When used input port, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Port Port Port Port
Port
Port
Port
P100 P103
Port
P110 P117
µPD78062(A), 78063(A), 78064(A)
CLOCK GENERATOR
There kinds clocks, main system clock subsystem clock. instruction execution time also changed. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 (during 5.0-MHz operation using main system clock) (during 32.768-kHz operation using subsystem clock) Figure 5-1. Clock Generator Block Diagram
XT1/P07
Subsystem Clock Oscillator
Watch Timer Clock Output Function Prescaler
Main System Clock Oscillator
Selector Scaler
Prescaler Standby Control Circuit
Clock
Peripheral Hardware
STOP Selector Clock (fCPU)
INTP0 Sampling Clock
TIMER/EVENT COUNTER Five timer/event counter channels incorporated. 16-bit timer/event counter channel 8-bit timer/event counter channels Watch timer channel Watchdog timer channel
Table 5-2. Timer/Event Counter Types Functions
16-bit Timer/ Event Counter Type Interval timer External event counter Timer output output Function Pulse width measurement Square wave output One-shot pulse output Interrupt request channel channel output output inputs output output
8-bit Timer/ Event Counter channels channels outputs outputs
Watch Timer channel
Watchdog Timer channel
µPD78062(A), 78063(A), 78064(A)
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/Compare Register (CR00) Pulse Output Control Circuit
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/22 TI00/P00/INTP0 Edge Detector Match Selector 16-Bit Timer Register (TM0) Clear
Output Control Circuit
TO0/P30
Selector INTTM01 INTP0
16-Bit Capture/Compare Register (CR01)
Internal
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal
INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match
Output Control Circuit
TO2/P32
fXX/2-fXX/29 fXX/211 TI1/P33 Clear fXX/2-fXX/29 fXX/211 TI2/P34 Output Control Circuit Internal Selector Selector Selector 8-Bit Timer Register (TM1) 8-Bit Timer Register (TM2) Clear
INTTM2
Selector
TO1/P31
µPD78062(A), 78063(A), 78064(A)
Figure 5-4. Watch Timer Block Diagram
fXX/27 Selec- Selector Prescaler 5-Bit Counter Selector INTWT
Selector
INTTM3 16-Bit Timer/Event Counter Controller/Driver
Figure 5-5. Watchdog Timer Block Diagram
Prescaler INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
µPD78062(A), 78063(A), 78064(A)
CLOCK OUTPUT CONTROL CIRCUIT Clocks following frequency output clock outputs: 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 (main system clock: operation) 32.768 (subsystem clock: 32.768 operation) Figure 5-6. Clock Output Circuit Block Diagram
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27
Selector
Synchronization Circuit
Output Control Circuit
PCL/P35
BUZZER OUTPUT CONTROL CIRCUIT
Clocks following frequency output buzzer outputs: kHz/2.4 kHz/4.9 kHz/9.8 (during operation using main system clock) Figure 5-7. Buzzer Output Control Circuit Block Diagram
fXX/29 fXX/210 fXX/2
Selector
Output Control Circuit
BUZ/P36
µPD78062(A), 78063(A), 78064(A)
CONVERTER Eight 8-bit resolution converter channels incorporated. following types start-up method available. Hardware start Software start Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive Approximation Register (SAR) Selector Sample Hold Circuit Voltage Comparator Selector AVDD AVREF
AVSS
INTP3/P03
Edge Detector
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
SERIAL INTERFACE clocked serial interface channels incorporated: Serial interface channel Serial interface channel Table 5-3. Serial Interface Channel Block Diagram
Function 3-wire serial mode (serial interface) mode 2-wire serial mode Asynchronous serial interface (UART) mode Serial Interface Channel
(MSB/LSB-first switchable) (MSB-first) (MSB-first)
Serial Interface Channel
(MSB/LSB-first switchable)
(Dedicated baud rate generator incorporated)
µPD78062(A), 78063(A), 78064(A)
Figure 5-9. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25 Selector SO0/SB1/P26 Serial Shift Register (SIO0) Output Latch
Selector
Release/Command/ Acknowledge Detector Interrupt Request Signal Generator
Busy/Acknowledge Output Circuit
SCK0/P27
Serial Clock Counter
INTCSI0
fXX/2-fXX/28 Serial Clock Control Circuit Selector
Figure 5-10. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RXD/SI2/P70 TXD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX-fXX/210
µPD78062(A), 78063(A), 78064(A)
CONTROLLER/DRIVER controller/driver with following functions incorporated. Selection types display mode segment signal outputs switched input/output ports units (P80/S39 P87/S32, P90/S31 P97/S24) Table 5-4. Display Mode Types Maximum Number Display Pixels
Bias Method Time Multiplexing Static Common Signal Used COM0 (COM1 COM3) COM0, COM1 COM0 COM2 COM0 COM2 COM0 COM3 segments commons) Maximum Number Display Pixels segments common) segments commons) segments commons)
Figure 5-11. Controller/Driver Block Diagram
Internal
Prescaler Display Data Memory Timing Controller Segment Data Selector Port Output Data Drive Voltage Generator Segment Driver Common Driver LCDCL Selector
S24/P97
S39/P80
COM0 COM1 COM2 COM3
VLC2
VLC1
VLC0
BIAS
µPD78062(A), 78063(A), 78064(A)
INTERRUPT FUNCTIONS TEST FUNCTIONS
INTERRUPT FUNCTIONS
There twenty interrupt functions three different kinds, shown below. Non-maskable interrupt Maskable interrupts Software interrupt
µPD78062(A), 78063(A), 78064(A)
Table 6-1. Interrupt Source List
Interrupt Type Nonmaskable
Default Priority Note
Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 input edge detection INTP3 INTP4 INTP5 INTCSI0 INTSER INTSR Serial interface channel transfer termination Serial interface channel UART reception error generation Serial interface channel UART reception termination Serial interface channel 3-wire transfer termination Serial interface channel UART transmission termination Reference time interval signal from watch timer 16-bit timer register capture/compare register (CR00) match signal generation 16-bit timer register capture/compare register (CR01) match signal generation 8-bit timer/event counter match signal generation 8-bit timer/event counter match signal generation converter conversion termination instruction execution Trigger Watchdog timer overflow (with watchdog timer mode selected)
Internal/ External
Vector Table Address
Basic Configuration Type Note
Internal Watchdog timer overflow (with interval timer mode selected)
0004H 0006H 0008H 000AH
External
000CH 000EH 0010H 0014H 0018H
Maskable
INTCSI2 INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD
001AH
001CH Internal 001EH 0020H 0022H 0024H 0026H 0028H Internal 003EH
Software
Notes
Default priority priority order when more than maskable interrupt generated simultaneously. highest priority lowest priority. Basic configuration types correspond those shown next page.
µPD78062(A), 78063(A), 78064(A)
Figure 6-1. Basic Configuration Interrupt Functions (1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTPO)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78062(A), 78063(A), 78064(A)
Figure 6-1. Basic Configuration Interrupt Functions (2/2) External maskable interrupt (except INTPO)
Internal
External Interrupt Mode Register (INTM0, INTM1)
Interrupt Request
Edge Detector
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
µPD78062(A), 78063(A), 78064(A)
TEST FUNCTIONS There test functions shown Table 6-2. Table 6-2. Test Input Source List
Test Input Source Name INTWT INTPT11 Trigger Watch timer overflow Port falling edge detection Internal/External Internal External
Figure 6-2. Basic Configuration Test Function
Internal
Test Input Signal
Standby Release Signal
Test input flag Test mask flag
µPD78062(A), 78063(A), 78064(A)
STANDBY FUNCTION
standby function function reduce current consumption. following kinds standby functions provided. HALT mode Halts operating clock reduce average current consumption intermittent operation along with normal operation. STOP mode Halts main system clock oscillation. Halts operations with main system clock sets ultra-low current consumption state with subsystem clock only. Figure 7-1. Standby Function
CSS=1 Main System Clock Operation CSS=0 STOP Instruction Interrupt Request STOP Mode Main System Clock Oscillation Halted Interrupt Request HALT Instruction Interrupt Request HALT Instruction Subsystem Clock OperationNote
HALT Mode Clock Supply Halted, Oscillation Maintained
HALT Mode Clock Supply Halted, Oscillation Maintained
Note
Note
Halting main system clock enables current consumption reduced. When operated subsystem clock, main system clock should halted setting. STOP instruction available.
Caution When main system clock stopped system operated subsystem clock, main system clock should returned after securing oscillation stabilization time program.
RESET FUNCTION
There following kinds resetting methods. External reset RESET pin. Internal reset watchdog timer runaway time detection.
mPD78062(A), 78063(A), 78064(A)
INSTRUCTION
8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBS, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
operand #byte operand ADDC SUBC ADDC SUBC ADDC SUBC saddr ADDC SUBC !addr16 [DE] [HL] [HL+byte] [HL+B] [HL+C] MULL DIVUW ROR4 ROL4 PUSH DBNZ DBNZ ADDC SUBC ADDC SUBC ADDC SUBC rNote saddr !addr16 [DE] [HL]
[HL+byte] [HL+B] $addr16 [HL+C]
RORC ROLC
None
ADDC SUBC
Note Except
mPD78062(A), 78063(A), 78064(A)
16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
operand #word operand ADDW SUBW CMPW sfrp saddrp !addr16 MOVW MOVW MOVW MOVW MOVWNote MOVW MOVW MOVW MOVW
INCW, DECW PUSH,
rpNote MOVW XCHW
sfrp MOVW
saddrp MOVW
!addr16 MOVW
MOVW
None
Note Only when manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
operand A.bit operand A.bit MOV1 BTCLR sfr.bit MOV1 BTCLR saddr.bit MOV1 BTCLR PSW.bit MOV1 BTCLR [HL].bit MOV1 BTCLR MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 MOV1 AND1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PSW.bits [HL].bit $addr16 None
Call instruction/branch instruction CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DNZB
Operand Operand Basic instruction Compound Instruction CALL CALLF CALLT BNC, BTCLR DBNZ !addr16 !addr11 [addr5] $addr16
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78062(A), 78063(A), 78064(A)
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol AVDD
Test Conditions
Rating -0.3 +7.0 -0.3 -0.3 -0.3 +0.3 -0.3 -0.3
Unit
Supply voltage AVREF AVSS Input voltage Output voltage Analog input voltage Output current, high Total P05, P07, P17, P100, P101 P110 P117 Total P27, P37, P72, P87, P97, P102 P103 Peak value R.m.s. value Total P05, P17, P100, P101 P110 P117 Output current, Note Total P37, P102 P103 Total P27, P77, Operating ambient temperature Storage temperature Peak value R.m.s. value Peak value R.m.s. value Tstg Peak value R.m.s. value +150 Analog input
AVSS AVREF
Note r.m.s. value should calculated follows: [R.m.s. value] [Peak value] Duty Caution product quality damaged even value only above parameters exceeds absolute maximum rating value exceeds absolute maximum rating instant. That absolute maximum rating rating value which cause product damaged physically. absolute maximum rating values must therefore observed when using product.
µPD78062(A), 78063(A), 78064(A)
CAPACITANCE
Parameter Input capacitance Output capacitance capacitance Symbol COUT Test Conditions unmeasured pins returned MIN. TYP. MAX. Unit
Remark Unless specified otherwise, characteristics dual-function pins same those port pins.
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS
Recommended circuit
Resonator
Parameter Oscillator frequency Note Oscillation stabilization time Note
Test conditions Oscillator voltage range After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Ceramic resonator
Crystal resonator
Oscillator frequency Note
Oscillation stabilization time input frequency Note input
Note
External clock µPD74HCU04
high/low level width (tXH
Notes Indicates only oscillator characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release. Cautions When using main system clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same ground ground pattern which high current flows. fetch signal from oscillator. main system clock oscillator operated subsystem clock when main system clock stopped, reswitching main system clock should performed after stable oscillation time been obtained program.
µPD78062(A), 78063(A), 78064(A)
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS +85°C,
Resonator Parameter Oscillator frequency (fXT) Note1 Test Conditions MIN. TYP. MAX. Unit
Recommended Circuit
Crystal resonator
32.768
Oscillation stabilization time Note2
External clock
input frequency (fXT) Note1
input high-/low-level width (tXTH/tXTL)
Notes
Indicates only oscillator characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reached minimum oscillation voltage range. When using subsystem clock oscillator, wiring area enclosed with dotted line should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same ground ground pattern which high current flows. fetch signal from oscillator.
Cautions
subsystem clock oscillator designed amplification circuit provide consumption current, causing misoperation noise more frequently than main system clock oscillation circuit. Special care should therefore taken about wiring method when subsystem clock used.
µPD78062(A), 78063(A), 78064(A)
RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR
Recommended Manufacturer Part Number Frequency (MHz) Circuit Constant (pF) Murata Mfg. Co., Ltd. CSA5.00MG CST5.00MGW EF0GC5004A4 Matsushita Electronics Components Co., Ltd. EF0EC5004A4 EF0EN5004A4 EF0S5004B5 KBR-5.0MSA Kyocera Corporation PBRC5.00A KBR-5.0MKS KBR-5.0MWS 5.00 5.00 5.00 5.00 5.00 5.00 5.00 Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in Round lead type Lead type Chip type Lead type Chip type Lead type Chip type 5.00 5.00 5.00 Built-in Built-in (pF) Built-in Built-in Oscillator Voltage Range MIN. MAX. Lead type Remarks
SUBSYSTEM CLOCK: CRYSTAL RESONATOR
Recommended Manufacturer Part Number Frequency (kHz) (pF) Kyocera Corporation KF-38G-12P0200 (Load capacitance 32.768 Circuit Constant (pF) Oscillator Voltage Range MIN. MAX.
Caution
operation oscillator constants guaranteed, their reliability. require higher reliability, contact oscillator manufacturer directly.
µPD78062(A), 78063(A), 78064(A)
CHARACTERISTICS
Parameter
Symbol
Test Conditions P17, P32,
MIN. 0.7VDD 0.8VDD
TYP.
MAX. 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.2VDD 0.1VDD 0.1VDD
Unit
VIH1
P37, P87, P97, P100 P103 P05, P27,
0.8VDD 0.85VDD
VIH2 Input voltage, high VIH3
P33, P34, P72, P110 P117, RESET 0.8VDD 0.9VDD 0.9VDD
VIH4
XT1/P07,
VNote
P17, P32, VIL1 P37, P87, P97, P100 P103 P05, P27, VIL2 Input voltage, VIL3 P33, P34, P72, P110 P117, RESET
VIL4
XT1/P07,
VNote
Output voltage, high
-100 P100 P103
VOL1 Output voltage,
P05, P17, P27, P37, P72, P87, P97, P110 P117
VOL2 VOL3
SB0, SB1, SCK0
open-drain, pull-up
0.2VDD
Note When P07/XT1 used P07, inverse phase should input XT2. Remark Unless specified otherwise, characteristics dual-function pins same those port pins.
µPD78062(A), 78063(A), 78064(A)
CHARACTERISTICS
Parameter Symbol Test Conditions P05, P17, P27, P37, P72, P87, P97, P100 P103, P110 P117 XT1/P07, P05, P17, P27, P37, P72, P87, P97, P100 P103, P110 P117 XT1/P07, P05, Software pull-up resistor P17, P27, P37, P72, P87, P97, P100 P103, P110 P117 5.00 MHz, Crystal oscillation (fXX MHz)Note operating mode 5.00 MHz, Crystal oscillation (fXX MHz)Note operating mode
Note
MIN.
TYP.
MAX.
Unit
Input leakage current, high
ILIH1
ILIH2
Input leakage current,
ILIL1
ILIH2 Output leakage current, high Output leakage current, ILOH ILOL
%Note
Note Note Note Note
0.35
1.05 19.5 1500 1950
IDD1
Supply current
IDD2
5.00 MHz, Crystal oscillation (fXX MHz)Note HALT mode 5.00 MHz, Crystal oscillation (fXX MHz)Note HALT mode
Notes
including currents flowing on-chip pull-up resistors split resistors. Main system clock operation (when oscillation mode selection register 00H) Main system clock operation (when oscillation mode selection register 01H) High-speed mode operation (when processor clock control register 00H) Low-speed mode operation (when processor clock control register 04H)
Remark Unless specified otherwise, characteristics dual-function pins same those port pins.
µPD78062(A), 78063(A), 78064(A)
CHARACTERISTICS
Parameter Symbol Test Conditions IDD3 32.768 kHz, Crystal oscillation operating modeNote 32.768 kHz, Crystal oscillation HALT modeNote STOP mode When feedback resistor connected STOP mode When feedback resistor disconnected IDD4 Supply currentNote IDD5 MIN. TYP. 0.05 0.05 MAX. 12.5 Unit
IDD6
Notes including currents flowing on-chip pull-up resistors split resistors. When main system clock stopped.
µPD78062(A), 78063(A), 78064(A)
CHARACTERISTICS Static Display Mode (VDD
Parameter drive voltage split resistor output voltage deviationNote (common) output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS VLCD0 VLCD Test Conditions MIN. TYP. MAX. ±0.2 ±0.2 Unit
Note
voltage deviation difference from output voltage corresponding ideal value segment common outputs (VLCDn;
Bias Method (VDD
Parameter drive voltage split resistor output voltage deviationNote (common) output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS VLCD0 VLCD VLCD1 VLCD VLCD2 VLCD Test Conditions MIN. TYP. MAX. ±0.2 ±0.2 Unit
Note
voltage deviation difference from output voltage corresponding ideal value segment common outputs (VLCDn;
Bias Method (VDD
Parameter drive voltage split resistor output voltage deviationNote (common) output voltage deviationNote (segment) Symbol VLCD RLCD VODC VODS VLCD0 VLCD VLCD1 VLCD VLCD2 VLCD1 Test Conditions MIN. TYP. MAX. ±0.2 ±0.2 Unit
Note
voltage deviation difference from output voltage corresponding ideal value segment common outputs (VLCDn;
µPD78062(A), 78063(A), 78064(A)
CHARACTERISTICS Basic Operation
Parameter Cycle time (Minimum instruction execution time) TI1, input frequency TI1, input high/ low-level width Interrupt input high/low-level width RESET low-level width
Symbol
Test Conditions Operating main system clock (fXX MHz)
Note1
MIN. 40Note3 8/fsamNote4
TYP.
MAX.
Unit
Operating main system clock (fXX MHz)
Note2
Operating subsystem clock tTIH, tTIL tINTH, tINTL tRSL INTP0 INTP1 INTP5, P110 P117
Notes
Main system clock operation (when oscillation mode selection register 00H) Main system clock operation (when oscillation mode selection register 01H) This value when external clock used. value (min.) when crystal resonator used. combination with bits (SCS0) (SCS1) sampling clock select register, selection fsam possible between XX/2N, /32, XX/64 /128 (when main system clock operation)
main system clock fX/2 operation)
Cycle Time
Guaranteed Operation Range
Cycle Time
Guaranteed Operation Range
Supply Voltage
Supply Voltage
µPD78062(A), 78063(A), 78064(A)
Serial Interface Serial interface channel 3-wire serial mode (SCK0. Internal clock output)
Parameter Symbol Test Conditions MIN. 1600 3200 SCK0 high/low-level width tKH1, tKL1 tSIK1 tKCY1/2 tKCY1/2 hold time (from SCK0÷) output delay time from tKSI1 tKSO1 pFNote TYP. MAX. Unit
SCK0 cycle time
tKCY1
setup time SCK0÷)
Note load capacitance SCK0, output line. (ii) 3-wire serial mode (SCK0.External clock input)
Parameter
Symbol
Test Conditions
MIN. 1600 3200 1600
TYP.
MAX.
Unit
SCK0 cycle time
tKCY2
tKH2 SCK0 high/low-level width tKL2 tSIK2 tKSI2 tKSO2
setup time SCK0÷) hold time (from SCK0÷) output delay time from SCK0 rise, fall time
pFNote
1000
Note load capacitance output line.
µPD78062(A), 78063(A), 78064(A)
(iii) mode (SCK0.Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 3200 SCK0 high/low-lev width SB0, setup time SCK0÷) SB0, hold time (from SCK0÷) SB0, output delay time from SB0, from SCK0÷ from SB0, SB0, high-level width SB0, low-level width tKSO3 tKSB tSBK tSBH tKH3, tKL3 tSIK3 tKCY3/2 tKCY3/2 tKSI3 tKCY3 Test Conditions MIN. TYP. MAX. Unit
pFNote
tKCY3 tKCY3 tKCY3
1000
tSBL
tKCY3
Note load resistance load capacitance SCK0, output line. (iv) mode (SCK0.External clock input)
Parameter SCK0 cycle time Symbol tKCY4 3200 SCK0 high/low-lev width SB0, setup time SCK0÷) SB0, hold time (from SCK0÷) SB0, output delay time from SB0, from SCK0÷ from SB0, SB0, high-level width SB0, low-level width SCK0 rise, fall time tKSO4 tKSB tSBK tSBH tKH4, tKL4 tSIK4 1600 tKSI4 tKCY4 Test Conditions MIN. TYP. MAX. Unit
pFNote
tKCY4 tKCY4 tKCY4
1000
tSBL
tKCY4 1000
Note load resistance load capacitance output line.
µPD78062(A), 78063(A), 78064(A)
2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0÷) SB0, hold time (from SCK0÷) SB0, output delay time from Symbol tKCY5 tKH5 tKL5 pFNote tSIK5 Test Conditions MIN. 1600 3200 tKCY5/2 tKCY5/2 tKCY5/2 tKCY5/2 tKSI5 tKSO5 TYP. MAX. Unit
Note load resistance load capacitance SCK0, output lines. (vi) 2-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0÷) SB0, hold time (from SCK0÷) SB0, output delay time from SCK0 rise, fall time Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 pFNote Test Conditions MIN. 1600 3200 1300 1600 tKCY6 1000 TYP. MAX. Unit
Note load resistance load capacitance output lines.
µPD78062(A), 78063(A), 78064(A)
Serial interface channel 3-wire serial mode (SCK2. Internal clock output)
Parameter Symbol Test Conditions SCK2 cycle time tKCY7 tKH7, tKL7 setup time SCK2÷) tSIK7 MIN. 1600 3200 SCK2 high/low-level width tKCY1 /2-50 tKCY1 /2-100 hold time (from SCK2÷) output delay time from tKSI7 tKSO7 pFNote TYP. MAX. Unit
Note load capacitance SCK2 output lines. (ii) 3-wire serial mode (SCK2.External clock input)
Parameter
Symbol
Test Conditions
MIN. 1600 3200 1600
TYP.
MAX.
Unit
SCK2 cycle time
tKCY8
tKH8 SCK2 high/low-level width tKL8 tSIK8 tKSI8 tKSO8
setup time SCK2÷) hold time (from SCK2÷) output delay time from SCK2 rise, fall time
pFNote
1000
Note load capacitance output line.
µPD78062(A), 78063(A), 78064(A)
(iii) UART mode (Dedicated baud rate generator output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX. 78125 39063 19531
Unit
Transfer rate
(iv) UART mode (External clock input)
Parameter Symbol Test Conditions ASCK cycle time tKCY9 Transfer rate MIN. 1600 3200 ASCK high/low-level width tKH9 tKL9 1600 39063 19531 9766 ASCK rise, fall time 1000 TYP. MAX. Unit
µPD78062(A), 78063(A), 78064(A)
Timing Test Point (Excluding Input)
0.8VDD 0.2VDD
Test Points
0.8VDD 0.2VDD
Clock Timing
1/fX
Input
1/fXT
tXTL Input
tXTH
Timing
1/fTI
tTIL
tTIH
µPD78062(A), 78063(A), 78064(A)
Serial Transfer Timing 3-wire serial mode:
tKCYm
tKLm SCK0, SCK2 tSIKm tKSm
tKHm
SI0, tKSOm
Input Data
SO0,
Output Data
mode (bus release signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBL tSBH tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
mode (command signal transfer):
tKCY3, tKL3, SCK0 tKSB tSBK tSIK3, tKSI3, tKH3,
SB0, tKSO3,
µPD78062(A), 78063(A), 78064(A)
2-wire serial mode:
tKL5, SCK0
tKCY5, tKH5,
tSIK5, tKSO5, SB0,
tKSI5,
UART mode:
tKCY9 tKL9 ASCK tKH9
Converter AVDD AVSS
Parameter Resolution AVREF Overall error
Note
Symbol
Test Conditions
MIN.
TYP.
MAX. ±0.6 ±1.4
Unit
Conversion time Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance
tCONV tSAMP VIAN AVREF RAIREF
19.1 12/fXX AVSS
AVREF AVDD
Note Quantization error (±1/2 LSB) included. This expressed proportion full-scale value.
µPD78062(A), 78063(A), 78064(A)
DATA MEMORY STOP MODE SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
Parameter Data retention supply voltage Data retention supply current Release signal time Oscillation stabilization wait time tWAIT Release interrupt Note Symbol VDDDR VDDDR IDDDR Subsystem clock stopped feed-back resistor disconnected tSREL Release RESET 217/fx Test Conditions MIN. TYP. MAX. Unit
Note combination with bits (OSTS0 OSTS2) oscillation stabilization time select register, selection 212/ 214/f 217/f possible. Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (STOP Mode Release Standby Release Signal: Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78062(A), 78063(A), 78064(A)
Interrupt Input Timing
tINTL
tINTH
INTP0 INTP5
RESET Input Timing
tRSL
RESET
µPD78062(A), 78063(A), 78064(A)
CHARACTERISTIC CURVES (REFERENCE VALUES)
(Main System Clock: MHz)
10.0 PCC=00H
PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current (mA)
PCC=B0H
0.05 HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
32.768
0.001
Supply Voltage
µPD78062(A), 78063(A), 78064(A)
(Main System Clock: MHz)
10.0
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT Oscillation, Oscillation)
Supply Current (mA)
PCC=B0H
0.05 HALT Stop, Oscillation) STOP Stop, Oscillation)
0.01
0.005
32.768
0.001
Supply Voltage
µPD78062(A), 78063(A), 78064(A)
PACKAGE DRAWINGS
PLASTIC (FINE PITCH)
detail lead
NOTE
ITEM MILLIMETERS 16.0±0.2 14.0±0.2 14.0±0.2 16.0±0.2 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.10 1.45 0.125±0.075 5°±5° MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.057 0.005±0.003 5°±5° 0.067 MAX. P100GC-50-7EA-2
Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
Remark Dimensions materials products same those mass-produced products.
µPD78062(A), 78063(A), 78064(A)
PLASTIC
detail lead
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition. ITEM
P100GF-65-3BA1-2 MILLIMETERS 23.6 20.0 14.0 17.6 0.30 0.10 0.15 0.65 (T.P.) 0.15+0.10 -0.05 0.10 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.031 0.024 0.012+0.004 -0.005 0.006 0.026 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
Remark Dimensions materials products same those mass-produced products.
5°±5°
µPD78062(A), 78063(A), 78064(A)
RECOMMENDED SOLDERING CONDITIONS
µPD78062(A)/78063(A)/78064(A) should soldered mounted under conditions recommended table below. details recommended soldering conditions, refer information document "Semiconductor Device Mounting Technology Manual" (IE-1207). soldering methods conditions other than those recommended below, contact sales representative. Table 13-1. Surface Mounting Type Soldering Conditions (1/2) µPD78062GC(A)-xxx-7EA µPD78063GC(A)-xxx-7EA µPD78064GC(A)-xxx-7EA
Soldering Method Infrared reflow
100-pin plastic (Fine pitch) 100-pin plastic (Fine pitch) 100-pin plastic (Fine pitch)
Soldering Conditions Recommended Condition Symbol IR35-107-2
Package peak temperature: Duration: sec. max. above), Number times: Twice max., Time limit: daysNote (thereafter hours prebaking required precautions> second reflow should started after first reflow device temperature returned ordinary level. Flux washing with water must performed after first reflow.
Package peak temperature: Duration: sec. above), Number times: Twice max., Time limit: daysNote (thereafter hours prebaking required <precautions> second reflow should started after first reflow device temperature returned ordinary level. Flux washing with water must performed after first reflow.
VP15-107-2
Partial heating
temperature: max. Duration: sec. max. (per row)
Note storage period after dry-pack decapsulation, storage conditions max.
µPD78062(A), 78063(A), 78064(A)
Table 13-1. Surface Mounting Type Soldering Conditions (2/2) µPD78062GF(A)-xxx-3BA µPD78063GF(A)-xxx-3BA µPD78064GF(A)-xxx-3BA
Soldering Method Infrared reflow
100-pin plastic 100-pin plastic 100-pin plastic
Recommended Condition Symbol IR35-00-2
Soldering Conditions Package peak temperature: Duration: sec. max. above), Number times: Twice max. precautions> second reflow should started after first reflow device temperature returned ordinary level. Flux washing with water must performed after first reflow.
Package peak temperature: Duration: sec. above), Number times: Twice max. <precautions> second reflow should started after first reflow device temperature returned ordinary level. Flux washing with water must performed after first reflow.
VP15-00-2
Wave soldering
Solder bath temperature: max., Duration: sec. max., Number times: Once, Preliminary heat temperature: 120°C max. (Package surface temperature)
WS60-00-1
Partial heating
temperature: max. Duration: sec. max. (per row)
Caution more than soldering method should avoided (except case partial heating).
µPD78062(A), 78063(A), 78064(A)
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78062(A)/78063(A)/78064(A). Language Processing Software
RA78K/0 Notes CC78K/0 Notes DF78064 Notes CC78K/0-L Notes 78K/0 series common assembler package 78K/0 series common compiler package µPD78064 subseries device file 78K/0 series common compiler library source file
PROM Writing Tools
PG-1500 PA-78P064GC PA-78P064GF PA-78P064KL-T PG-1500 controller Notes PG-1500 control program Programmer adapters connected PG-1500 PROM programmer
Debugging Tools
IE-78000-R IE-78000-R-BK IE-78064-R-EM EP-78064GC-R EP-78064GF-R EV-9500GC-100 EV-9200GF-100 EV-9900 SM78K0 Notes SD78K/0
Notes
78K/0 series common in-circuit emulator 78K/0 series common break board µPD78064 subseries evaluation emulation board µPD78064 subseries common emulation probes Adapter mounted user system board made 100-pin plastic Socket mounted user system board made 100-pin plastic Tool used when removing µPD78P064KL-T from EV-9200GF-100 78K/0 series common system simulator IE-78000-R screen debugger µPD78064 subseries device file
DF78064 Notes
Real-Time
RX78K/0 Notes MX78K0 Notes 78K/0 series real-time 78K/0 series
µPD78062(A), 78063(A), 78064(A)
Fuzzy Inference Development Support System
FE9000 Note FE9200 Note FT9080 Note FT9085 Note FI78K0 Note FD78K/0 Note Fuzzy knowledge data creation tool Translator Fuzzy inference module Fussy inference debugger
Notes
PC-9800 series (MS-DOSTM) based PC/AT(PC DOSTM) based HP9000 series 300TM, HP9000 series 700(HP-UXTM) based, SPARCstation(Sun OSTM) based, EWS-4800 series (EWS-UX/V) based PC-9800 series (MS-DOS WindowsTM) based. PC/AT Windows) based third party development tools, 78K/0 Series Selection Guide (IF-1185). RA78K/0, CC78K/0, SM78K0, SD78K/0 used combination with DF78064.
Remarks
µPD78062(A), 78063(A), 78064(A)
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document Name µPD78064/78064Y Subseries User's Manual 78K/0 Series User's Manual (Instruction) 78K/0 Series Application Note Floating-Point Operation Program Document (Japanese) IEU-817 IEU-849 IEA-718 Document (English) IEU-1364 IEU-1372 IEA-1289
Development Tool Related Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series Compiler PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK IE-78064-R-EM EP-78064 SM78K/0 System Simulator SD78K/0 Screen Debugger PC/AT DOS) Base Reference Basic Reference PC-9800 series (MS-DOS) base series DOS) base Operation Language Document (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-5008 EEU-810 EEU-867 EEU-905 EEU-934 EEU-5002 EEU-5024 EEU-993 Document (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 Planned EEU-1291 EEU-1398 EEU-1427 EEU-1443 EEU-1469 prepared EEU-1414 EEU-1413
Installation Software Related Documents (User's Manual)
Document Name Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy, Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-858 EEU-921 EEU-1441 EEU-1458 Document (Japanese) EEU-829 EEU-862 Document (English) EEU-1438 EEU-1444
Other Related Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Devices Quality Guarantee Guide Document (Japanese) IEI-635 IEI-616 IEI-620 MEI-603 Document (English) IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution above related documents subject change without notice. design purposes, etc., sure latest documents.
µPD78062(A), 78063(A), 78064(A)
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must Semiconductor adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.

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