µPD789800 8-BIT SINGLE-CHIP MICROCONTROLLER µPD789800 78K/0S
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INTEGRATED CIRCUIT
µPD789800
8-BIT SINGLE-CHIP MICROCONTROLLER
µPD789800 78K/0S series product designed keyboard (for ASSP). µPD789800 on-chip hardware compatible with keyboard, including (Universal Serial Bus) functions, regulator which powers driver/receiver, return signal detection circuit. µPD78F9801, product with on-chip flash memory which operate same supply voltage masked products various development tools also under development. Detailed descriptions functions, etc., given following user's manuals. sure read them design purposes. PD789800 Sub-Series User's Manual U12978E U11047E 78K/0S Series User's Manual, Instruction
FEATURES
On-chip functions Implements (Universal Serial Bus) connecting Host. Transfer speed: Mbps (when system clock operates MHz) On-chip regulator Controls port voltage using power supply (VREG ±0.3 dedicated driver/receiver. On-chip Internal bytes Internal high-speed RAM: bytes Minimum instruction execution time switched between high speed (0.33 speed (1.33 (when system clock operates MHz). port: Serial interface: channels function Timer: channels 8-bit timer counter Watchdog timer channel channel channel 8-bit timer/event counter channel Three-wire serial mode channel
On-chip return signal detection circuit Supply voltage: Operating ambient temperature -40°C +85°C (when operating) +70°C (when operating)
information this document subject change without notice. Before using this document, please confirm that this latest version.
Document U12627EJ1V0DS00 (1st edition) Date Published November 1998 CP(K) Printed Japan
mark
shows major revised points.
1997
µPD789800
APPLICATIONS
keyboards, etc.
ORDERING INFORMATION
Part number Remark indicates code suffix. Package 42-pin plastic shrink (600 mil) 44-pin plastic 0.8-mm pitch)
µPD789800
78K/0S SERIES DEVELOPMENT
78K/0S series products shown below. sub-series names indicated frames.
production Under development small-scale, generalpurpose applications 44-pin 42/44-pin 28-pin
µPD789046 µPD789026 µPD789014
small-scale, general-purpose applications function
Device developed adding subsystem clock µPD789026 Device developed enhancing timers µPD789014 expanding With built-in UART capable low-voltage (1.8 operation
44/48-pin 44/48-pin 44-pin 44-pin 30-pin 30-pin 28/30-pin 28/30-pin 28/30-pin 28/30-pin
µPD789217AY µPD789197AY µPD789177 µPD789167 µPD789156 µPD789146 µPD789134A µPD789124A µPD789114A µPD789104A
driving
oscillator version µPD789197AY With built-in EEPROMand µPD789177 Device developed enhancing function µPD789167 Device developed enhancing timers µPD789104A Device developed enhancing function PD789146 With built-in EEPROM µPD789104A Device developed enhancing function µPD789124A oscillator version µPD789104A Device developed enhancing function µPD789104A Device developed adding function multiplier µPD789026
78K/0S series
80-pin 80-pin 88/100-pin
µPD789417A µPD789407A µPD789830
ASSP
Device developed enhancing function µPD789407A Device developed adding function enhancing timers µPD789026 With built-in UART
44-pin 5-pin 42/44-pin
µPD789840 µPD789810 µPD789800
Device keypad, with built-in Device card, with built-in security circuit Device keyboard, with built-in function
µPD789800
following table lists major differences functions between sub-series.
Function size Sub-series Small-scale, µPD789046 generalµPD789026 purpose applications µPD789014 Small-scale, µPD789217AY generalpurpose applications µPD789197AY function µPD789177 µPD789167 µPD789156 µPD789146 µPD789134A µPD789124A µPD789114A µPD789104A driving µPD789417A µPD789407A µPD789830 ASSP µPD789840 µPD789800 µPD789810 K-24 K-16 K-16 K-24 UART: 8-bit 16-bit Clock pins pins RC-oscillator version, with built-in EEPROM With built-in EEPROM (UART: (UART: (USB: pins pins pins With built-in EEPROM (UART: pins pins With built-in EEPROM RC-oscillator version Timer
8-bit
10-bit
Serial interface
Minimum value
Remarks
(UART:
pins
µPD789800
FUNCTIONS
Item Internal memory High-speed Minimum instruction execution time General-purpose register Instruction bytes bytes 0.33 µs/1.33 (when system clock operates MHz) bits registers 16-bit operation manipulation (set, reset, test) etc. ports Serial interface CMOS I/O: pins these, pins switched N-ch open-drain pins.) (Universal Serial Bus) function channel Three-wire serial mode Timer 8-bit timer counter Watchdog timer Regulator Vector interrupt source Power supply voltage Operating ambient temperature Maskable Nonmaskable channel Function
channel channel
8-bit timer/event counter channel Incorporated (VREG ±0.3 Internal: external: Internal: -40°C +85°C (when operating) +70°C (when operating) Package 42-pin plastic shrink (600 mil) 44-pin plastic 0.8-mm pitch)
µPD789800
CONTENTS
CONFIGURATION (TOP VIEW). BLOCK DIAGRAM. FUNCTIONS
Port Pins Non-Port Pins Input/Output Circuits Handling Unused Pins
MEMORY SPACE. PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generator Timer. Serial Interface Regulator Return Signal Detection Circuit.
INTERRUPT FUNCTION. STANDBY FUNCTION. RESET FUNCTION. INSTRUCTION OVERVIEW
Legend Operations
ELECTRICAL CHARACTERISTICS PACKAGE DRAWINGS. RECOMMENDED SOLDERING CONDITIONS. APPENDIX DEVELOPMENT TOOLS. APPENDIX RELATED DOCUMENTS.
µPD789800
CONFIGURATION (TOP VIEW)
42-pin plastic shrink (600 mil)
P47/KR07 P46/KR06 P45/KR05 P44/KR04 P43/KR03 P42/KR02 P41/KR01 P40/KR00 RESET VSS0 VDD0 REGC USBDM USBDP P26/TI01/TO01/INTP0
VSS1 VDD1 P20/SCK10 P21/SO10 P22/SI10
Caution Connect (Internally Connected) directly VSS0 VSS1 pin.
µPD789800
44-pin plastic 0.8-mm pitch)
P26/TI01/TO01/INTP0
P20/SCK10
P21/SO10
P22/SI10
VDD1 VSS1
USBDP USBDM REGC VDD0 VSS0 RESET P40/KR00 P41/KR01
P47/KR07
P46/KR06
P45/KR05
P44/KR04
P43/KR03
Caution Connect (Internally Connected) directly VSS0 VSS1 pin. Internally connected
SCK10
P42/KR02
Serial clock input/output Serial data input Serial data output Timer input Timer output Power supply Ground Crystal
INTP0 Interrupt from peripherals KR00 KR07 return P00-P07 P10-P17 P20-P26 P40-P47 RESET REGC connection Port Port Port Port Reset Voltage regulator function
SI10 SO10 TI01 TO01 VDD0, VDD1 VSS0, VSS1
USBDM, USBDP Universal serial data
µPD789800
BLOCK DIAGRAM
KR00-KR07
RETURN0
8-bit TIMER00 PORT TI01/TO01/P26/INTP0 8-bit TIMER/ EVENT COUNTER01 78K/0S CORE PORT WATCHDOG TIMER PORT REGC REGULATOR VREG USBDM USBDP SCK10/P20 SO10/P21 SI10/P22 INTP0/P26 FUNCTION0 RESET PORT P40-P47 P20-P26 P10-P17 P00-P07
SERIAL INTERFACE10 VDD0 VDD1 VSS0 VSS1
SYSTEM CONTROL
INTERRUPT CONTROL
µPD789800
FUNCTIONS Port Pins
Port 8-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. P10-P17 Port 8-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. P23-P25 P40-P47 Port 7-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Only P26, CMOS output N-ch open-drain output specifiable bit. Port 8-bit input/output port Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Input INTP0/TI01/TO01 KR00 KR07 SI10 Input SCK10 SO10 Input Function When reset Input Also used
name P00-P07
µPD789800
Non-Port Pins
name INTP0 KR00 KR07 REGC Input Input Input Function External interrupt request input which effective edges (rising and/or falling edges) specified Input detecting return signals Internally generated power supply driving driver/receiver. Connect this through 220- resistor 0.1-µF capacitor. System reset input Serial clock input/output serial interface Serial data input serial interface Serial data output serial interface External count clock input 8-bit timer/event counter Timer output from 8-bit timer/event counter Serial data input/output (negative side) function. pull-up resistor (1.5 USBDM must connected REGC pin. Serial data input/output (positive side) function Connected crystal system clock oscillator Input Input Input Input Input Input Input P26/INTP0/TO01 P26/INTP0/TI01 When reset Input Input Also used P26/TI01/TO01 P40-P47
RESET SCK10 SI10 SO10 TI01 TO01 USBDM
Input Input Output Input Output
USBDP VDD0 VDD1 VSS0 VSS1
Input
Input Input
Positive supply voltage ports Positive supply voltage circuits other than ports Ground potential ports Ground potential circuits other than ports Internally connected. Connect this directly VSS0. internally connected. Leave this open.
µPD789800
Input/Output Circuits Handling Unused Pins
Table lists types input/output circuits each explains unused pins handled. Figure shows configuration each type input/output circuit. Table 3-1. Type Input/Output Circuit Each
name P00-P07 P10-P17 P20/ SCK10 P21/SO10 P22/SI10 P23, P26/INTP0/TI01/TO01 P40/ KR00 -P47/ KR07 USBDM USBDP RESET REGC Input 24-A Connect this REGC pin. Connect this VSS0 VSS1 resistors. Connect this directly VSS0 VSS1. Leave this open. Connect this USBDM pin. circuit type Input Recommended connection unused pins Connect these pins separately VDD0, VDD1, VSS0, VSS1 respective resistors. Output Leave these pins open.
µPD789800
Figure 3-1. Input/Output Circuits
Type Type
VDD0
Pull-up enable P-ch Output data VDD0
P-ch
P-ch IN/OUT
Schmitt trigger input with hysteresis
Output disable VSS0
N-ch
Type Pull-up enable P-ch Output data VDD0 P-ch
VDD0
Type 24-A
P-ch VREG
TXDXP RXDX IN/OUT TXDXN
P-ch IN/OUT N-ch
Output disable VSS0 Input enable
N-ch VSS0
Type VDD0 Pull-up enable VDD0 Output data P-ch IN/OUT Output disable P-ch
N-ch VSS0
µPD789800
MEMORY SPACE
Figure shows memory µPD789800. Figure 4-1. Memory
FFFFH Special function register bits FF00H FEFFH Internal high-speed bits FE00H FDFFH
Data memory space
Unusable
1FFFH 2000H 1FFFH Program area
Program memory space
Internal 8,192 bits
0080H 007FH CALLT table area 0040H 003FH Program area 0020H 0019H Vector table area
0000H
0000H
µPD789800
PERIPHERAL HARDWARE FUNCTIONS Ports
ports listed below. CMOS input/output ports (ports port pins these, pins (pins ports P25, P26) switched N-ch open-drain input/output pins. Table 5-1. Port Functions
Name Port name P00-P07 Function Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. Port P10-P17 Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. CMOS output N-ch open-drain output specifiable 8-bit units. Port P20-P24 Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. P25, Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software. Only P26, CMOS output N-ch open-drain output specifiable. Port P40-P47 Input/output port. Input output specifiable bit. When used input port, on-chip pull-up resistors specified software.
Clock Generator
µPD789800 on-chip system clock generator. possible change minimum instruction execution time. 0.33 1.33 (when system clock operates MHz) Figure 5-1. Block Diagram Clock Generator
Prescaler
System clock oscillator
Clock peripheral hardware Prescaler
Selector
Standby control circuit
Wait control circuit
clock (fCPU)
STOP
µPD789800
Timer
µPD789800 three on-chip timers. 8-bit timer counter Watchdog timer channel channel Table 5-2. Timer Operation
8-bit timer counter Operation mode Interval timer External event counter Function Timer output Square wave output Interrupt request channel 8-bit timer/event counter channel channel output output Watchdog timer channel
8-bit timer/event counter channel
Figure 5-2. Block Diagram 8-Bit Timer Counter
Internal
8-bit compare register (CR00) Match INTTM00
Selector
fX/2
fX/29
8-bit timer register (TM00) Clear
Internal
µPD789800
Figure 5-3. Block Diagram 8-Bit Timer/Event Counter
Internal
8-bit compare register (CR01) Match INTTM01 fX/28 TI01/P26 /INTP0/TO01
Selector
fX/2
8-bit timer register (TM01) Clear
Output control circuit
TO01/P26/INTP0/ TI01
Internal
Figure 5-4. Block Diagram Watchdog Timer
Prescaler Clear INTWDT maskable interrupt request RESET INTWDT nonmaskable interrupt request
7-bit counter
Serial Interface
channels serial interface chip. function µPD789800 supports Mbps transfer speed with system clock incorporates NRZI (Non Return Zero Invert) decode/encode function, stuffing function, (Cyclic Redundancy Check) function specified (Universal Serial Bus) communication protocol. Figure shows block diagram. Serial interface (SIO10) SIO10 following modes: Operation stop mode Three-wire serial mode (The first switched between LSB.) Figure shows block diagram.
Control circuit
Selector
µPD789800
Figure 5-5. Block Diagram Function
Internal Transmit reservation registers (HTXRSV, DTXRSV)
receiver enable register (USBMOD)
Data/handshake packet receive mode register (URXMOD)
Counter
Remote wake-up control register (REMWUP)
Transmit/receive pointers (USBPOB, USBPOW) Each handshake packet SYNC packet NRZI encoder Output latch Transmit buffer
USBDP
Selector
generation/detection resume reset detection control
USBDM
SYNC detection/USB clock generator clock
Receive bank switching detection buffer
Receive buffer
stuff/bit strip control circuit Overflow
timer (7-bit counter) Start
INTUSB
Compare register INTUSBRD ENDP detection circuit circuit
timer start reservation control register (USBTCL)
Receive result storage register (DRXRSL)
Packet receive status register (RXSTAT)
Internal
µPD789800
Figure 5-6. Block Diagram Serial Interface
Internal
SI10/P22
Serial shift register (SIO10)
SO10/P21 SCK10/P20 Serial clock counter Interrupt request signal generator INTCSI10
Selector
Selector
Serial clock control circuit
fX/22 fX/23
Regulator
µPD789800 incorporates regulator which powers driver/receiver. features follows: Generates VREG (3.3 ±0.3 from VDD0 VDD1 (4.0 outputs REGC pin. Supports power-saving mode, reducing current dissipation during STOP mode. Figure 5-7. Block Diagram Regulator Driver/Receiver
PD789800
VDD0 REGC VSS0 VDD0
Regulator
VREG
TXDP TXDM TXEN RXEN VSS0 USBDP driver/ receiver USBDM
Cautions settle VREG voltage, connect REGC 220- resistor 0.1-µF capacitor. Connect pull-up resistor (1.5 USBDM pin, REGC pin.
µPD789800
Return Signal Detection Circuit
µPD789800 incorporates return signal detection circuit that detect return signals input P40/KR00-P47/KR07 pins. Specify whether detect return signals P40/KR00-P47/KR07 pins means return mode register (KRM00). Inhibit interrupts before setting KRM00 (see Caution KRM00 1-bit memory operation instruction 8-bit memory operation instruction. (KRM000) corresponds KR00/P40-KR03/P43 pins. setting common these four pins. Bits (KRM004-KRM007) correspond KR04/P44-KR07/P47 pins respectively bit. Inputting RESET signal clears KRM00 00H. Figure shows format return mode register Figure shows block diagram falling edge detection circuit. Figure 5-8. Format Return Mode Register
Symbol KRM006 KRM005 KRM004 KRM000 Address FFF5H When reset
KRM00 KRM007
KRM00n detection
Selection return signal detection P4n/KR0n
Detection (detecting falling edges P4n/KR0n signals)
KRM000 detection
Selection return signal detection P40/KR00-P43/KR03 pins
Detection (detecting falling edges P40/KR00-P43/KR03 signals)
Cautions sure bits When KRM00 pull-up resistor forcibly connected corresponding pin. However, when placed output mode, pull-up resistor disconnected. Before setting KRM00, inhibit interrupts (set interrupt mask flag register (MK0) (KRMK00 After setting KRM00, clear interrupt request flag register (IF0) (KRIF00 then permit interrupts (clear (KRMK00 0)).
µPD789800
Figure 5-9. Block Diagram Falling Edge Detection Circuit
return mode register (KRM00)Note
P40/KR00 P41/KR01
Selector
P42/KR02 P43/KR03 P44/KR04 P45/KR05 P46/KR06 P47/KR07
Falling edge detection circuit
KRIF00 signal
KRMK00
Standby release signal
Note Register that selects used falling edge input
µPD789800
INTERRUPT FUNCTION
There types sources interrupt function shown below. Nonmaskable interrupt Maskable interrupts source sources Table 6-1. Interrupt Source List
Interrupt source Priority Note
Type interrupt Nonmaskable
Internal/ external Internal
Vector table address 0004H
Name INTWDT
Trigger Watchdog timer overflow (when watchdog timer mode selected)
Basic configuration Note type
Maskable
INTWDT
Watchdog timer overflow (when interval timer mode selected)
INTUSBINTUSBRT
timer overflow detection when token packet received
0006H 0008H
INTUSBRD
detection when data/handshake packet received
000AH
INTUSBST
detection when data/handshake packet sent
000CH
INTUSBRE
Detection transition from state state
000EH
INTP0 INTCSI10
Detection input edge three-wire interface transmission reception
External Internal
0010H 0012H
INTTM00
Generation 8-bit timer counter match signal
0014H
INTTM01
Generation 8-bit timer/event counter match signal
0016H
INTKR00
Detection return signal
External
0018H
Notes priority order priority when multiple maskable interrupts generated simultaneously. highest priority lowest priority. Types basic configuration correspond Figure 6-1, respectively.
µPD789800
Figure 6-1. Basic Configuration Interrupt Function Internal nonmaskable interrupt
Internal
Interrupt request
Vector table address generator
Standby release signal
Internal maskable interrupt
Internal
Interrupt request
Vector table address generator
Standby release signal
External maskable interrupt
Internal
INTM0, KRM00
Interrupt request
Edge detection circuit
Vector table address generator
Standby release signal
INTM0 External interrupt mode register KRM00 return mode register Interrupt request flag Interrupt enable flag Interrupt mask flag
µPD789800
STANDBY FUNCTION
standby function function reduce current consumption there kinds standby function shown below. HALT mode STOP mode: Stops operating clock CPU. Intermittent operation together with normal operation reduce average current consumption. Stops oscillation system clock. Stops entire operation system clock minimizes power consumption. Figure 7-1. Standby Function
System clock operation
HALT instruction Interrupt request STOP instruction
Interrupt request HALT mode Clock supply stopped, while oscillation continues
STOP mode Oscillation system clock stopped
RESET FUNCTION
system reset following ways. External reset RESET Internal reset detection inadvertent program loop time watchdog timer
µPD789800
INSTRUCTION OVERVIEW
instruction µPD789800 listed later.
Legend
9.1.1 Operand formats descriptions description made operand field each instruction conforms operand format instructions listed below (the details conform with assembly specification). more than operand format listed instruction, selected. Uppercase letters, pair used specify keywords, which must written exactly they appear. meanings these special characters follows: Immediate data specification Relative address specification Absolute address specification Indirect address specification Immediate data should described using appropriate values labels. specification values labels must accompanied pair Operand registers, expressed formats, described using both functional names etc.) absolute names (R0, other names listed Table 9-1). Table 9-1. Operand Formats Descriptions
Format saddr saddrp addr16 addr5 word byte Description (R0), (R1), (R2), (R3), (R4), (R5), (R6), (R7) (RP0), (RP1), (RP2), (RP3) Special function register symbol FE20H FF1FH: Immediate data label FE20H FF1FH: Immediate data label (even addresses only) 0000H FFFFH: Immediate data label (only even address 16-bit data transfer instructions) 0040H 007FH: Immediate data label (even addresses only) 16-bit immediate data label 8-bit immediate data label 3-bit immediate data label
µPD789800
9.1.2 Descriptions operation field NMIS register (8-bit accumulator) register register register register register register register register pair (16-bit accumulator) register pair register pair register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicate that nonmaskable interrupt being handled Contents memory location indicated parenthesized address register name Logical product (AND) Logical (OR) Exclusive Inverted data
Upper lower bits 16-bit register
addr16 16-bit immediate data label jdisp8 Signed 8-bit data (displacement value) 9.1.3 Description flag operation field (blank) change cleared cleared according result restored previous value
µPD789800
Operations
Flag Mnemonic #byte saddr, #byte sfr, #byte saddr saddr, sfr, !addr16 !addr16, PSW, #byte PSW, [DE] [DE], [HL] [HL], byte] byte], saddr [DE] [HL] byte] MOVW #word saddrp saddrp,
Note Note Note
Operand
Byte
Clock byte (saddr) byte byte (saddr) (saddr) (addr16) (addr16) byte (DE) (DE) (HL) (HL) byte) byte) (saddr) (sfr) (DE) (HL) byte) word (saddrp) (saddrp)
Operation
Note
Note
Notes Except when Except when Only when Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
µPD789800
Flag Mnemonic XCHW #byte saddr, #byte saddr !addr16 [HL] byte] ADDC #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] SUBC #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] Operand
Note
Byte
Clock byte
Operation
(saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr), (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte)
Note Only when Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
µPD789800
Flag Mnemonic #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] #byte saddr, #byte saddr !addr16 [HL] byte] ADDW SUBW CMPW #word #word #word saddr saddr INCW DECW RORC ROLC Operand Byte Clock byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) (saddr) byte (saddr) (addr16) (HL) byte) byte (saddr) byte (saddr) (addr16) (HL) byte) word word word rr+1 (saddr) (saddr) rr-1 (saddr) (saddr) (CY, Am-1 (CY, Am+1 Am-1 Am+1 Operation
Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
µPD789800
Flag Mnemonic SET1 saddr. sfr. PSW. [HL]. CLR1 saddr. sfr. PSW. [HL]. SET1 CLR1 NOT1 CALL !addr16 Operand Byte Clock (saddr. bit) sfr. PSW. (HL). (saddr. bit) sfr. PSW. (HL). 3)H, 3)L, addr16, CALLT [addr5] 1)H, 1)L, (00000000, addr5 (00000000, addr5), (SP), RETI (SP), NMIS PUSH PSW, rpH, rpL, (SP), (SP), MOVW !addr16 $addr16 addr16 jdisp8 Operation
Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
µPD789800
Flag Mnemonic $addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16 Operand Byte Clock Operation jdisp8 jdisp8 jdisp8 jdisp8 jdisp8 (saddr. bit) sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 saddr. bit, $addr16 jdisp8 sfr. jdisp8 jdisp8 PSW. jdisp8 (saddr. bit) sfr. bit, $addr16 bit, $addr16 PSW. bit, $addr16 DBNZ $addr16 jdisp8 sfr. jdisp8 jdisp8 PSW. then jdisp8 $addr16 then jdisp8 saddr, $addr16 (saddr) (saddr) then jdisp8 (saddr) HALT STOP Operation (Enable Interrupt) (Disable Interrupt) HALT Mode STOP Mode
Remark instruction clock cycle based clock (fCPU), specified processor clock control register (PCC).
µPD789800
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS 25°C)
Parameter Supply voltage Input voltage Output voltage Output high current Symbol Each Total pins Output current Each Total pins Operating ambient temperature Storage temperature Tstg Conditions Rated value -0.3 +6.5 -0.3 -0.3 +150 Unit
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values. Remark characteristics dual-function differ between port function secondary function, unless otherwise stated.
µPD789800
CHARACTERISTICS SYSTEM CLOCK OSCILLATION CIRCUIT -40°C +85°C,
Recommended circuit
Resonator Crystal
Parameter Oscillator frequency (fX)
Note
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation settling time
Note
External clock
input frequency (fX)
Note
input high/low level width
OPEN
(tXH, tXL)
Notes Only characteristics oscillation circuit indicated. characteristics instruction execution time.
description
Time required oscillation settle once reset sequence ends STOP mode deselected. resonator that settle oscillation before oscillation settling time expires. Caution When using system clock oscillation circuit, observe following conditions wiring that section enclosed dotted lines above diagrams, avoid influence wiring capacitance. Keep wiring short possible. allow signal wires cross another. Keep wiring away from wires that carry high, non-stable current. Keep grounding point capacitors same level VSS0. connect grounding point grounding wire that carries high current. extract signal from oscillation circuit.
µPD789800
CHARACTERISTICS -40°C +85°C,
Parameter Output high current Output current Input high voltage Symbol VIH1 VIH2 VIH3 VIH4 Input voltage VIL1 VIL2 VIL3 VIL4 Output high voltage VOH1 VOH2 Output voltage VOL1 VOL2 High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 High-level output leakage current Low-level output leakage current Software pull-up resistor Regulator output voltage Supply current
Note
Conditions Each Total pins Each Total pins P00-P07, P10-P17 RESET, P20-P26, P40-P47 USBDM, USBDP +70°C P00-P07, P10-P17 RESET, P20, P22, P40-P47 USBDM, USBDP +70°C Pins other than USBDM USBDP
MIN.
TYP.
MAX.
Unit
0.7VDD 0.8VDD
0.3VDD 0.2VDD
USBDM, USBDP +70°C, Note (connected VSS) Pins other than USBDM USBDP
Note
USBDM, USBDP +70°C, Note (connected VDD) Pins other than USBDM, USBDP USBDM, USBDP +70°C Pins other than USBDM, USBDP USBDM, USBDP +70°C VOUT VOUT 6.0-MHz crystal oscillation (operating mode) 6.0-MHz crystal oscillation (HALT mode) STOP mode VREG VREG
ILOH ILOL VREG IDD1 IDD2 IDD3
Note
When function disabled When function enabled +70°C)
Notes resistor connected line. power supply current does include current flowing through on-chip pull-up resistor. During high-speed mode operation (when processor clock control register (PCC) cleared 00H) Remark characteristics dual-function differ between port function secondary function, unless otherwise stated.
µPD789800
CHARACTERISTICS Basic operations -40°C +85°C,
Parameter
Cycle time (minimum instruction execution
Symbol
Conditions When MHz) When MHz)
MIN. 0.333 1.333
TYP. 0.333 1.333
MAX. 0.333 1.333
Unit
TI01 input frequency TI01 input high/low level width Interrupt input high/low level width RESET input level width
tTIH, tTIL
tINTH, tINTL
INTP0
tRSL
Serial interface function +70°C,
Parameter USBDM USBDP rise time USBDM USBDP fall time matching Differential output signal cross-over point Data transfer rate Transmission differential signal jitter Transmission width Reception width Reception reset width tEOPR1 tEOPR2 tURES1 tURES2 width eliminated width detected reset width eliminated reset width detected tRFM VCRS Symbol
Note
Conditions
MIN.
TYP.
MAX.
Unit
Note
Note
tR/tF
Note
tDRATE
When microcontroller operates system clock (fX)
Mbps
tUDJ1 tUDJ2 tEOPT1
Upon transferring next Upon transferring following next
-150 1.25
1.33
1.50
Note capacitance USBDM USBDP output lines.
µPD789800
Three-wire serial mode -40°C +85°C, SCK10 .Internal clock output (when MHz)
Parameter SCK10 cycle time Symbol tKCY1 When TPS100 When TPS100 SCK10 high/low level width SI10 setup time SI10 hold time tKH1, tKL1 tSIK1 tKSI1 When TPS100 When TPS100
Note
Conditions
MIN. 1,333
TYP. 1,333
MAX. 1,333
Unit
Note
Note
Note
Relative SCK10 Relative SCK10 When TPS100 When TPS100
Note
Note
SO10 output dalay
tKSO1
Relative SCK10
Note
Notes serial operation mode register (CSIM10) capacitance output line. (ii) SCK10 .External clock output
Parameter SCK10 cycle time SCK10 high/low level width SI10 setup time SI10 hold time SO10 output delay Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 Relative SCK10
Note
Conditions
MIN.
TYP.
MAX.
Unit
Note capacitance output line.
µPD789800
TIMING MEASUREMENT POINTS (except input function)
0.8VDD 0.2VDD Measurement points 0.8VDD 0.2VDD
CLOCK TIMING
1/fX VIH4 (MIN.) VIL4 (MAX.)
input
TIMING
tTIL tTIH
TI01
INTERRUPT INPUT TIMING
tINTL tINTH
INTP0
RESET INPUT TIMING
tRSL
RESET
µPD789800
SERIAL TRANSFER TIMING Function: USBDM USBDP rise/fall time
0.9VDD 0.1VDD
USBDM, USBDP
Transmission different signal jitter
1,333 USBDM, USBDP Next following next
tUDJ1
tUDJ2
Differential output signal cross-over point, transmission width, reception width, reception reset width
USBDM, USBDP
VCRS
tEOPT1, tEOPRm, tURESm
Three-Wire Serial Mode:
tKCYm tKLm tKHm
0.8VDD SCK10 0.2VDD
tSIKm SI10
tKSIm
Input data
tKSOm
SO10
Output data
µPD789800
DATA HOLD CHARACTERISTICS DATA MEMORY VOLTAGE STOP MODE -40°C +85°C)
Item Data hold supply voltage Release signal time Oscillation settling time
Note
Symbol VDDDR tSREL tWAIT Reset RESET
Conditions
MIN.
TYP.
MAX.
Unit
Note
Reset interrupt request
Notes
During oscillation settling time, operations disabled prevent them from becoming unstable upon start oscillation. 212/fX, 215/fX, 217/fX selected according setting bits (OSTS0 OSTS2) oscillation settling time selection register.
Remark System clock oscillation frequency DATA HOLD TIMING (STOP mode release RESET
Internal reset operation HALT mode STOP mode Data hold mode Operating mode
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
DATA HOLD TIMING (standby release signal: STOP mode release interrupt signal)
HALT mode STOP mode Data hold mode Operating mode
VDDDR STOP instruction execution Standby release signal (interrupt request)
tSREL
tWAIT
µPD789800
PACKAGE DRAWINGS
42PIN PLASTIC SHRINK (600 mil)
NOTES Each lead centerline located within 0.17 (0.007 inch) true position (T.P.) maximum material condition. Item center leads when formed parallel.
ITEM
MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15°
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15° P42C-70-600A-1
µPD789800
PLASTIC
detail lead
ITEM MILLIMETERS 13.2±0.2 10.0±0.2 10.0±0.2 13.2±0.2 0.37 +0.08 -0.07 0.16 (T.P.) 1.6±0.2 0.8±0.2 0.17 +0.06 -0.05 0.10 2.7±0.1 0.125±0.075 MAX. INCHES 0.520 +0.008 -0.009 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.520 +0.008 -0.009 0.039 0.039 0.015 +0.003 -0.004 0.007 0.031 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.002 -0.003 0.004 0.106 +0.005 -0.004 0.005±0.003 0.119 MAX. S44GB-80-3BS-1
NOTE Controlling dimension millimeter.
Each lead centerline located within 0.16 (0.007 inch) true position (T.P.) maximum material condition.
µPD789800
RECOMMENDED SOLDERING CONDITIONS
µPD789800 should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representatives. Table 12-1. Surface Mounting Type Soldering Conditions 44-pin plastic
Soldering method Infrared reflow Soldering conditions Package peak temperature: 235°C Duration: sec. max. 210°C above) Maximum allowable number reflow processes: Package peak temperature: 215°C Duration: sec. max. 200°C above) Maximum allowable number reflow processes: Solder bath temperature: 260°C max. Duration: sec. max. Number times: Once Preliminary heat temperature: 120°C max. (Package surface temperature) Terminal temperature: 300°C max. Duration: sec. max. (per device side) Symbol IR35-00-3
VP15-00-3
Wave soldering
WS60-00-1
Partial heating method
Caution more than soldering method should avoided (except partial heating method). Table 12-2. Insertion Type Soldering Conditions 42-pin plastic shrink (600 mil)
Soldering method Wave soldering (terminal only) Partial heating method Soldering conditions Solder bath temperature: 260°C max., Duration: sec. max. Terminal temperature: 300°C max., Duration: sec. max. (for each pin)
Caution Apply wave soldering terminals only. that solder does contact with chip directly.
µPD789800
APPENDIX DEVELOPMENT TOOLS
following development tools available developing systems using µPD789800. LANGUAGE PROCESSING SOFTWARE
RA78K0S
Notes Notes Notes
Assembler package common 78K/0S series compiler package common 78K/0S series Device file µPD789800 sub-series
CC78K0S
DF789801
FLASH MEMORY WRITE TOOLS
Flashpro FA-42CU FA-44GB
Note Note
Dedicated flash writer Flash memory write adapter
DEBUGGING TOOLS
IE-78K0S-NS In-circuit emulator IE-70000-MC-PS-B adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF Interface adapter IE-789801-NS-EM1 Emulation board NP-42CU
Note
In-circuit emulator debugging hardware software application system using 78K/0S Series. Supports integrated debugger (ID78K0S-NS). Used combination with adapter, emulation probe, interface adapter connecting host machine. This adapter supplying power from outlet VAC. This adapter needed when PC-9800 series (excluding notebook models) used host machine IE-78K0S-NS. (Compatible with bus) This card interface cable needed when notebook-type personal computer used host machine IE-78K0S-NS. (Compatible with PCMCIA socket) This adapter needed when PC/AT 78K0S-NS. (Compatible with bus)
compatibles used host machine
This adapter needed when personal computer with built-in used host machine IE-78K0S-NS. Emulation board emulating peripheral hardware inherent device. Used combination with in-circuit emulator. Board connecting in-circuit emulator target system. This 42-pin plastic shrink DIP. Board connecting in-circuit emulator target system. This 44-pin plastic QFP. System simulator common 78K/0S series Integrated debugger common 78K/0S series Device file µPD789800 sub-series
NP-44GB
Note Notes Notes
SM78K0S
ID78K0S-NS DF789801
Notes
REAL-TIME
MX78K0S
Notes
78K/0S series
Notes Based PC-9800 series (MS-DOS
Windows
Based PC/AT compatibles (Japanese/English Windows) Based HP9000 series 700(HP-UXTM), SPARCstation(SunOSTM, SolarisTM), NEWS(NEWS-OS Product manufactured Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Contact sales representative purchase. Remark RA78K0S, CC78K0S, SM78K0S used combination with DF789801.
µPD789800
APPENDIX RELATED DOCUMENTS
DOCUMENTS RELATED DEVICES
Document name µPD789800 Data Sheet µPD78F9801 Preliminary Product Information µPD789800 Sub-Series User's Manual 78K/0 Series User's Manual Instruction Document Japanese U12627J U12626J U12978J U11047J English This manual U12626E U12978E U11047E
DOCUMENTS RELATED DEVELOPMENT TOOLS (USER'S MANUAL)
Document name RA78K0S Assembler Package Operation Assembly Language Structured Assembly Language CC78K0S Compiler Operation Language SM78K0S System Simulator Windows Base SM78K Series System Simulator ID78K0S-NS Integrated Debugger Windows Base IE-78K0S-NS In-circuit Emulator IE-789801-NS-EM1 Emulation Board Reference
External Parts User Open Interface Specifications
Document Japanese U11622J U11599J U11623J U11816J U11817J U11489J U10092J U12901J U13549J U13390J English U11622E U11599E U11623E U11816E U11817E U11489E U10092E U12901E U13549E prepared
Reference
DOCUMENTS RELATED SOFTWARE INCORPORATED INTO PRODUCT (USER'S MANUAL)
Document name 78K/0S Series MX78K0S Basic Document Japanese U12938J English U12938E
OTHER DOCUMENTS
Document name PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Device Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide Products Related Micro-Computer: Other Companies Document Japanese C10943X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E English
Caution above documents revised without notice. latest versions when design application systems.
µPD789800
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
EEPROM trademark Corporation. MS-DOS Windows registered trademarks trademarks Microsoft Corporation United States and/or other countries. PC/AT trademark Corporation. HP9000 series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks SONY Corporation.
µPD789800
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J98.
µPD789800
[MEMO]
µPD789800
Some related documents preliminary versions. preliminary indicated this document.
Note, however, that whether related document
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
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