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µPD784217,784218 16/8-BIT SINGLE-CHIP MICROCONTROLLERS PD784


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INTEGRATED CIRCUIT
µPD784217,784218
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
PD784218 member PD784218 Subseries 78K/IV Series. Besides high-speed highperformance CPU, features various peripheral hardware such ROM, RAM, ports, 8-bit resolution converters, timer, serial interface, real-time output port, interrupts, etc. flash memory version, PD78F4218, which operate same supply voltage range mask version, various development tools under development. Detailed function descriptions provided following user's manuals. sure read them before designing.
PD784218, 784218Y Subseries User's Manual Hardware U12970E
78K/IV Series User's Manual Instructions U10905E
FEATURES
correction function Inherits peripheral functions µPD78078 Subseries Pin-compatible with PD784218Y Subseries Minimum instruction execution time (main system clock 12.5 MHz) (subsystem clock 32.768 kHz) High-capacity memory ROM: RAM: Kbytes (µPD784217) Kbytes µPD784218) 12,800 bytes PD784217, 784218) port: pins Timer/counter: 16-bit timer/counter unit 8-bit timer/counter units Serial interface: channels UART/IOE (3-wire serial I/O): channels (3-wire serial I/O): channel Standby function HALT/STOP/IDLE modes power-saving mode: HALT/IDLE modes (with subsystem clock) Clock division function Watch timer: channel Watchdog timer: channel Clock output function Selectable from XX/2 Buzzer output function Selectable from /211 XX/2 converter: 8-bit resolution channels converter: 8-bit resolution channels Supply voltage:
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, equipment, etc.
Unless otherwise specified, references this document µPD784218 refer µPD784217
µPD784218.
information this document subject change without notice.
Document U12303EJ1V0DS00 (1st edition) Date Published February 1999 CP(K) Printed Japan
mark
shows major revised points.
1997 1999
PD784217,784218
ORDERING INFORMATION
Part Number Package
Note Note
Internal (bytes) Internal (bytes)
100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin plastic LQFP (fine pitch) 100-pin plastic
12,800 12,800 12,800 12,800
Note Under development Remark indicates code suffix.
78K/IV SERIES LINEUP
Under mass production Under development supported
PD784038Y
Multi-master supported
µPD784225Y PD784225
80-pin correction added Multi-master supported
Standard models
PD784026
A/D, 16-bit timer, power management enhanced
PD784038
Internal memory capacity enhanced Pin-compatible with PD784026 Multi-master supported
PD784216Y PD784216
100-pin I/O, internal memory capacity enhanced
PD784218Y PD784218
Internal memory capacity enhanced correction added
PD784054 PD784046
ASSP models
PD784955
inverter control
On-chip 10-bit
PD784937
Function PD784908 enhanced Internal memory capacity enhanced correction added Multi-master supported
PD784908
On-chip controller IEBus
PD784928Y PD784928 PD784915
Software servo control On-chip analog circuit Timer enhanced Function PD784915 enhanced
Data Sheet U12303EJ1V0DS00
PD784217,784218
FUNCTIONS (1/2)
Part Number Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space port Total CMOS input CMOS N-ch open-drain Pins with ancillary Pins with pull-up resistor bits registers banks, bits registers banks (memory mapping) ns/320 ns/640 ns/1280 ns/2560 (main system clock: 12.5 MHz) (subsystem clock: 32.768 kHz) Kbytes 12,800 bytes Mbyte with program data spaces combined bits bits Timer/counter: bits) Timer register Capture/compare register Pulse output output Square wave output One-shot pulse output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Pulse output output Square wave output Kbytes
PD784217
µPD784218
functionsNote direct drive output Middlevoltage Real-time output port Timer/counter
Timer/counter bits) Timer/counter bits) Timer/counter bits) Timer/counter bits) Timer/counter bits) Timer/counter bits)
Timer register Compare register Timer register Compare register Timer register Compare register Timer register Compare register Timer register Compare register Timer register Compare register
Note pins with ancillary functions included pins.
Data Sheet U12303EJ1V0DS00
PD784217,784218
FUNCTIONS (2/2)
Part Number Item Serial interface converter converter Clock output Buzzer output Watch timer Watchdog timer Standby Interrupt Hardware source Software source Non-maskable Maskable UART/IOE (3-wire serial I/O): channels (on-chip baud rate generator) (3-wire serial I/O): channel 8-bit resolution channels 8-bit resolution channels Selectable from fXX/2, XX/22, fXX/23, fXX/24 fXX/25, fXX/26 fXX/27, Selectable from fXX/2 XX/211, XX/212, XX/213 channel channel HALT/STOP/IDLE modes power-saving mode (with subsystem clock): HALT/IDLE modes (internal: external: instruction, BRKCS instruction, operand error Internal: external: Internal: external: priority levels programmed. types service modes: vectored interrupt/macro service/context switching Supply voltage Package 100-pin plastic LQFP (fine pitch) 100-pin plastic
µPD784217
PD784218
Data Sheet U12303EJ1V0DS00
PD784217,784218
CONTENTS
DIFFERENCES AMONG MODELS µPD784218 SUBSERIES DIFFERENCES BETWEEN µPD784218 µPD784216 MAJOR DIFFERENCES FROM µPD78078 SUBSERIES CONFIGURATION (Top View) BLOCK DIAGRAM FUNCTIONS
Port Pins Non-port Pins Circuits Recommended Connection Unused Pins
ARCHITECTURE
Memory Space Registers 7.2.1 7.2.2 7.2.3 General-purpose registers Control registers Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generation Circuit Real-Time Output Port Timer/Counter Converter Converter Serial Interface 8.7.1 8.7.2 Asynchronous serial interface/3-wire serial (UART/IOE) Clocked serial interface (CSI)
Clock Output Function Buzzer Output Function
8.10 Edge Detection Function 8.11 Watch Timer 8.12 Watchdog Timer
INTERRUPT FUNCTION
Interrupt Sources Vectored Interrupt Context Switching Macro Service Application Example Macro Service
Data Sheet U12303EJ1V0DS00
PD784217,784218
LOCAL INTERFACE
10.1 Memory Expansion 10.2 Programmable Wait 10.3 External Access Status Function
STANDBY FUNCTION RESET FUNCTION CORRECTION INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
Data Sheet U12303EJ1V0DS00
PD784217,784218
DIFFERENCES AMONG MODELS µPD784218 SUBSERIES
only difference between PD784217 784218 lies internal memory capacity. PD78F4218 provided with 256-Kbyte flash memory instead mask PD784218. These differences described Table 1-1. Table 1-1. Differences among Models µPD784218 Subseries
Part Number Item Internal
µPD784217
Kbytes (mask ROM) 12,800 bytes None
PD784218
Kbytes (mask ROM)
µPD78F4218
Kbytes (Flash memory)
Internal Internal memory size switching register (IMS) Supply voltage clock Electrical specifications Recommended soldering conditions TEST
Provided Note
Main system clock, subsystem clock Refer individual data sheets.
Main system clock
Provided None
None Provided
Note Internal flash memory capacity internal capacity changed using internal memory size switching register (IMS). Caution There differences noise immunity noise radiation between flash memory mask versions. When pre-producing application with flash memory version then mass-producing with mask version, sure conduct sufficient evaluations commercial samples (not engineering samples) mask version.
Data Sheet U12303EJ1V0DS00
PD784217,784218
DIFFERENCES BETWEEN µPD784218 µPD784216
differences between PD784218 PD784216 summarized Table 2-1. Table 2-1. Differences between PD784218 PD784216
Part Number Item Internal Internal correction External access status function Kbytes 12,800 bytes Provided Provided
PD784218
Kbytes 8,192 bytes None None
PD784216
Data Sheet U12303EJ1V0DS00
PD784217,784218
MAJOR DIFFERENCES FROM µPD78078 SUBSERIES
Series Name Item Minimum instruction execution time When main system clock selected When subsystem clock selected Memory space port Total CMOS input CMOS N-ch open-drain Pins with ancillary functions Note Pins with pull-up resistor direct drive output Middle-voltage Timer/counter 16-bit 12.5 operation) 32.768 operation) Mbyte 8-bit operation) 32.768 operation) Kbytes
PD784218 Subseries
µPD78078 Subseries
16-bit timer/counter unit 8-bit timer/counter units UART/IOE (3-wire serial I/O) channels (3-wire serial I/O) channel
16-bit timer/counter unit 8-bit timer/counter units UART/IOE (3-wire serial I/O) channel (3-wire serial I/O, 2-wire serial I/O, SBI) channel (3-wire serial I/O, 3-wire serial with automatic transmit/receive function) channel None None None None HALT/STOP modes
Serial interface
Interrupt
Macro service Context switching Programmable priority
Provided Provided Provided levels HALT/STOP/IDLE modes power-saving mode: HALT/IDLE modes Provided Provided 100-pin plastic LQFP (fine pitch) 100-pin plastic
Standby function
correction External access status function Package
None None 100-pin plastic LQFP (fine pitch) 100-pin plastic 100-pin ceramic WQFN PD78P078 only)
Note pins with ancillary functions included pins.
Data Sheet U12303EJ1V0DS00
PD784217,784218
CONFIGURATION (Top View)
100-pin plastic LQFP (fine pitch)
Note
P120/RTP0 P121/RTP1 P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 AVDD Note AVREF0 P10/ANI0 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5 P84/A4 P83/A3
P11/ANI1
P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5
P16/ANI6 P17/ANI7 AVSS Note
Notes Under development Connect TEST directly Connect VDD. Connect VSS.
Data Sheet U12303EJ1V0DS00
P130/ANO0 P131/ANO1 AVREF1 P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0 P26/SO0 P27/SCK0 P80/A0 P81/A1 P82/A2
TEST Note P37/EXA P36/TI01 P35/TI00 P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103/TI8/TO8 P102/TI7/TO7 P101/TI6/TO6 P100/TI5/TO5 P67/ASTB P66/WAIT P65/WR P64/RD P63/A19
PD784217,784218
100-pin plastic
Note
P60/A16 P61/A17 P62/A18 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/TI00 P36/TI01 P37/EXA TEST Note P120/RTP0 P121/RTP1
P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 P85/A5
P84/A4 P83/A3 P82/A2 P81/A1 P80/A0 P27/SCK0 P26/SO0 P25/SI0 P24/BUZ P23/PCL P22/ASCK1/SCK1 P21/TxD1/SO1 P20/RxD1/SI1 P72/ASCK2/SCK2 P71/TxD2/SO2 P70/RxD2/SI2 AVREF1 P131/ANO1 P130/ANO0 AVSS Note P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 AVDD Note
Notes Under development Connect TEST directly Connect AVDD VDD. Connect AVSS
P122/RTP2 P123/RTP3 P124/RTP4 P125/RTP5 P126/RTP6 P127/RTP7 RESET P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6
Data Sheet U12303EJ1V0DS00
PD784217,784218
A19: AD7: ANI0 ANI7: ANO0, ANO1: ASCK1, ASCK2: ASTB: REF0, AVREF1: BUZ: EXA: INTP0 INTP6: NMI: P06: P17: P27: P37: P47: P57: P67: P72: P87: P95: Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Buzzer Clock External Access Status Output Interrupt from Peripherals Non-maskable Interrupt Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 P100 P103: P120 P127: P130, P131: PCL: RESET: RTP0 RTP7: RxD1, RxD2: SCK0 SCK2: SI2: SO2: TEST: TI00, TI01, TI1, TI2, TI8: TxD1, TxD2: WAIT: XT1, XT2: Timer Input Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) TO2, Timer Output Port10 Port12 Port13 Programmable Clock Read Strobe Reset Real-time Output Port Receive Data Serial Clock Serial Input Serial Output Test
Data Sheet U12303EJ1V0DS00
PD784217,784218
BLOCK DIAGRAM
INTP2/NMI INTP0, INTP1, INTP3 INTP6 TI00 TI01
PROGRAMMABLE INTERRUPT CONTROLLER TIMER/COUNTER BITS) TIMER/COUNTER1 BITS) TIMER/COUNTER2 BITS) TIMER/COUNTER5 BITS) TIMER/COUNTER6 BITS) TIMER/COUNTER7 BITS) TIMER/COUNTER8 BITS)
UART/IOE1 BAUD-RATE GENERATOR UART/IOE2 BAUD-RATE GENERATOR CLOCKED SERIAL INTERFACE
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 SCK0
TI5/TO5
WAIT ASTB
TI6/TO6
78K/IV CORE
TI7/TO7
PORT0 PORT1
P100 P103 P120 P127 P130, P131 RESET
TI8/TO8
PORT2 PORT3
WATCH TIMER
PORT4 PORT5
WATCHDOG TIMER
PORT6 PORT7
RTP0 RTP7 ANO0 ANO1 AVREF1 AVSS ANI0 ANI7 AVREF0 AVDD AVSS
REAL-TIME OUTPUT PORT
PORT8 PORT9
CONVERTER
PORT10 PORT12
CONVERTER CLOCK OUTPUT CONTROL BUZZER OUTPUT
PORT13
SYSTEM CONTROL TEST
Remark internal capacity differs depending product.
Data Sheet U12303EJ1V0DS00
PD784217,784218
FUNCTIONS Port Pins (1/2)
Name Input Alternate Function INTP0 INTP1 INTP2/NMI INTP3 INTP4 INTP5 INTP6 ANI0 ANI7 Port (P1): 8-bit input port Port (P2): 8-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software. Function Port (P0): 7-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software.
RxD1/SI1 TxD1/SO1 ASCK1/SCK1 SCK0
TI00 TI01
Port (P3): 8-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software.
Port (P4): 8-bit port input output mode 1-bit units. pins input mode connected internal pull-up resistors means software. directly drive LEDs. Port (P5): 8-bit port input output mode 1-bit units. pins input mode connected internal pull-up resistors means software. directly drive LEDs.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Port Pins (2/2)
Name Alternate Function WAIT ASTB RxD2/SI2 Port (P7): 3-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software. Function Port (P6): 8-bit port input output mode 1-bit units. pins input mode connected internal pull-up resistors means software.
TxD2/SO2
ASCK2/SCK2
Port (P8): 8-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software. Interrupt control flag (KRIF) when falling edge detected this port. Port (P9): N-ch open-drain middle-voltage port 6-bit port input output mode 1-bit units. directly drive LEDs. Port (P10): 4-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software. Port (P12): 8-bit port input output mode 1-bit units. Regardless input mode/output mode specification, on-chip pullup resistor specified 1-bit units means software. Port (P13): 2-bit port input output mode 1-bit units.
P100 P101 P102 P103 P120 P127
TI5/TO5 TI6/TO6 TI7/TO7 TI8/TO8
RTP0 RTP7
P130, P131
ANO0, ANO1
Data Sheet U12303EJ1V0DS00
PD784217,784218
Non-port Pins (1/2)
Name TI00 TI01 RxD1 RxD2 TxD1 TxD2 ASCK1 ASCK2 SCK0 SCK1 SCK2 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 Input Output Input Input Output Input Output Input Alternate Function P100/TO5 P101/TO6 P102/TO7 P103/TO8 P100/TI5 P101/TI6 P102/TI7 P103/TI8 P20/SI1 P70/SI2 P21/SO1 P71/SO2 P22/SCK1 P72/SCK2 P20/RxD1 P70/RxD2 P21/TxD1 P71/TxD2 P22/ASCK1 P72/ASCK2 P02/INTP2 P02/NMI Serial data input (UART1) Serial data input (UART2) Serial data output (UART1) Serial data output (UART2) Baud rate clock input (UART1) Baud rate clock input (UART2) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O0) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Non-maskable interrupt request input External interrupt request input Function External count clock input 16-bit timer register Capture trigger signal input capture/compare register External count clock input 8-bit timer register External count clock input 8-bit timer register External count clock input 8-bit timer register External count clock input 8-bit timer register External count clock input 8-bit timer register External count clock input 8-bit timer register 16-bit timer output (shared 14-bit output) 8-bit timer output (shared 8-bit output)
Data Sheet U12303EJ1V0DS00
PD784217,784218
Non-port Pins (2/2)
Name RTP0 RTP7 Output Output Output Alternate Function P120 P127 Function Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port that outputs data synchronization with trigger Low-order address/data when external memory connected Low-order address when external memory connected Middle-order address when external memory connected High-order address when external memory connected Strobe signal output read operation external memory Strobe signal output write operation external memory insert wait state(s) when external memory accessed Strobe output externally latch address information output ports through port access external memory Status signal output when external memory accessed System reset input Crystal connection main system clock oscillation
WAIT ASTB
Output
Output
Input Output
RESET ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS TEST
Output Input Input Input Input Output
Crystal connection subsystem clock oscillation
P130, P131
Analog voltage input converter Analog voltage output converter apply reference voltage converter apply reference voltage converter Positive power supply converter. Connect VDD. converter converter. Connect Positive power supply Connect this directly (this test).
Data Sheet U12303EJ1V0DS00
PD784217,784218
Circuits Recommended Connection Unused Pins
Table shows symbols indicating circuit types respective pins recommended connection unused pins. circuit diagram each type circuit, refer Figure 6-1. Table 6-1. Types Input/Output Circuits Recommended Connection Unused Pins (1/2)
Name P00/INTP0 P01/INTP1 P02/INTP2/NMI P03/INTP3 P06/INTP6 P10/ANI0 P17/ANI7 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 P23/PCL P24/BUZ P25/SI0 P26/SO0 P27/SCK0 P30/TO0 P32/TO2 P33/TI1, P34/TI2 P35/TI00, P36/TI01 P37/EXA P40/AD0 P47/AD7 P50/A8 P57/A15 P60/A16 P63/A19 P64/RD P65/WR P66/WAIT P67/ASTB P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P80/A0 P87/A7 P100/TI5/TO5 P101/TI6/TO6 P102/TI7/TO7 P103/TI8/TO8 P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 12-A
Data Sheet U12303EJ1V0DS00
Circuit Type
Recommended Connection Unused Pins Input Independently connect resistor Output: Leave open
10-A
Input
Connect Input Independently connect resistor Output: Leave open
13-D
PD784217,784218
Table 6-1. Types Input/Output Circuits Recommended Connection Unused Pins (2/2)
Name RESET AVREF0 AVREF1 AVDD AVSS TEST Connect Connect directly Circuit Type Input Connect Leave open Connect Connect Recommended Connection Unused Pins
Remark Because circuit type numbers standardized among Series products, they sequential some models (i.e., some circuits provided).
Data Sheet U12303EJ1V0DS00
PD784217,784218
Figure 6-1. Circuits
Type
Type 10-A
pullup enable data P-ch
P-ch
IN/OUT Schmitt trigger input with hysteresis characteristics open drain output disable N-ch
Type
Type 12-A
pullup enable data P-ch
P-ch
pullup enable data P-ch
P-ch
IN/OUT IN/OUT output disable input enable Analog output voltage Type 13-D P-ch N-ch
output disable
N-ch
input enable Type
N-ch
pullup enable data P-ch
P-ch data output disable N-ch IN/OUT
IN/OUT
output disable
N-ch
P-ch
Middle-voltage input buffer Type Type feedback cut-off P-ch
P-ch N-ch
Comparator VREF (Threshold voltage)
input enable
Data Sheet U12303EJ1V0DS00
PD784217,784218
ARCHITECTURE Memory Space
memory space Mbyte accessed. Mapping internal data area (special function registers internal RAM) specified LOCATION instruction. LOCATION instruction must always executed after reset cancellation, must used more than once. When LOCATION instruction executed Internal memory internal data area internal area mapped follows:
Part Number Internal Data Area 0CD00H 0FFFFH Internal Area 00000H 0CCFFH 10000H 2FFFFH 00000H 0CCFFH 10000H 3FFFFH
µPD784217 µPD784218
Caution
following areas that overlap internal data area internal cannot used when LOCATION instruction executed.
Part Number Unusable Area 0CD00H 0FFFFH (13,056 bytes)
µPD784217 µPD784218
External memory external memory accessed external memory expansion mode. When LOCATION instruction executed Internal memory internal data area internal area mapped follows:
Part Number Internal Data Area FCD00H FFFFFH Internal Area 00000H 2FFFFH 00000H 3FFFFH
µPD784217 µPD784218
External memory external memory accessed external memory expansion mode.
Data Sheet U12303EJ1V0DS00
execution LOCATION instruction
Figure 7-1. Memory µPD784217
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 bytes)
External memory (832 Kbytes)
Note
General-purpose registers (128 bytes)
FFE8
Internal (12,800 bytes)
Special FDFH Note FD0H
Internal (131,072 bytes)
function registers (SFR) (256 bytes)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U12303EJ1V0DS00
Internal (12,800 bytes)
Program/data area (12,288 bytes)
External memory (838,912 bytes)
Note
Note
Note
Program/data area
Note
Internal (52,480 bytes)
CALLF entry area Kbytes)
CALLT table area bytes) Vector table area bytes)
Internal (192 Kbytes)
Note
PD784217,784218
Notes Accessed external memory expansion mode. This 13,056-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 183,552 bytes, execution LOCATION instruction: 196,608 bytes Base area entry area reset interrupt. However, internal area used reset entry area.
Figure 7-2. Memory µPD784218
execution LOCATION instruction
execution LOCATION instruction
Special FDFH Note FD0H
function registers (SFR) (256 bytes)
External memory (768 Kbytes)
Note
General-purpose registers (128 bytes)
FFE8
Internal (12,800 bytes)
Special FDFH Note FD0H
Internal (196,608 bytes)
function registers (SFR) (256 bytes)
Macro service control word area bytes) Data area (512 bytes)
FFE0
Data Sheet U12303EJ1V0DS00
Internal (12,800 bytes)
Program/data area (12,288 bytes)
External memory (773,376 bytes)
Note
Note
Note
Program/data area
Note
Internal (52,480 bytes)
CALLF entry area Kbytes)
PD784217,784218
CALLT table area bytes) Vector table area bytes)
Internal (256 Kbytes)
Note
Notes Accessed external memory expansion mode. This 13,056-byte area used internal only when LOCATION instruction executed. execution LOCATION instruction: 249,088 bytes, execution LOCATION instruction: 262,144 bytes
Base area entry area reset interrupt. However, internal area used reset entry area.
PD784217,784218
Registers
7.2.1 General-purpose registers Sixteen 8-bit general-purpose registers available. 8-bit registers also used pairs 16-bit register. 16-bit registers, four used combination with 8-bit register address expansion 24-bit address specification registers. Eight banks these register sets available which selected using software context switching function. general-purpose registers except registers address expansion mapped internal RAM. Figure 7-3. General-Purpose Register Format
(R1) (RP0) (R3) (RP1) (RG4) (RP4)
(R0) (R2)
(RP5) (RG5) (R13) (R12)
(RP6) (RG6) (R15) (R14) banks (RG7) Parentheses (RP7) indicate absolute name.
Caution
Registers RP2, used registers, respectively, setting However, this function only recycling program 78K/III Series.
Data Sheet U12303EJ1V0DS00
PD784217,784218
7.2.2 Control registers Program counter (PC) program counter 20-bit register whose contents automatically updated when program executed. Figure 7-4. Program Counter (PC) Format
Program status word (PSW) This register holds status CPU. contents automatically updated when program executed. Figure 7-5. Program Status Word (PSW) Format
PSWH PSWL
Note
RBS2
RBS1
RBS0
Note This flag provided maintain compatibility with 78K/III Series. sure clear this flag except when software 78K/III Series used. Stack pointer (SP) This 24-bit pointer that holds first address stack. sure write higher bits this pointer. Figure 7-6. Stack Pointer (SP) Format
Data Sheet U12303EJ1V0DS00
PD784217,784218
7.2.3 Special function registers (SFRs) special function registers, such mode registers control registers internal peripheral hardware, registers which special functions allocated. These registers mapped 256-byte space addresses 0FF00H through 0FFFFH Note Note execution LOCATION instruction. FFF00H through FFFFFH execution LOCATION instruction. Caution access address this area which allocated. such address accessed mistake, µPD784218 deadlock status. This deadlock status cleared only inputting RESET signal. Table lists special function registers (SFRs). meanings symbols this table follows: Symbol Symbol indicating SFR. compiler (CC78K4). Indicates whether read-only, write-only, read/write. Read/write Read-only Write-only This symbol reserved NEC's assembler
(RA78K4). used variable #pragma command with
units manipulation units which value manipulated. SFRs that manipulated 16-bit units described operand sfrp instruction. specify address this SFR, describe even address. SFRs that manipulated 1-bit units described operand manipulation instruction. After reset Indicates status register when RESET signal been input.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Table 7-1. Special Function Register (SFR) List (1/4)
Address Note Special Function Register (SFR) Name Symbol Units Manipulation 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF0AH 0FF0CH 0FF0DH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF18H 0FF1AH 0FF1CH 0FF20H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF28H 0FF29H 0FF2AH 0FF2CH 0FF2DH Capture/compare register (16-bit timer/counter) Capture/compare register (16-bit timer/counter) Capture/compare control register 16-bit timer mode control register 16-bit timer output control register Prescaler mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register CRC0 TMC0 TOC0 PRM0 PM10 PM12 PM13 CR01 CR00 Port Port Port Port Port Port Port Port Port Port Port Port Port 16-bit timer register bits bits 0000H Note After Reset
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. Because each port initialized input mode after reset, "00H" actually read. output latch initialized "0".
Data Sheet U12303EJ1V0DS00
PD784217,784218
Table 7-1. Special Function Register (SFR) List (2/4)
Address Note Special Function Register (SFR) Name Symbol Units Manipulation 0FF30H 0FF32H 0FF33H 0FF37H 0FF38H 0FF3AH 0FF3CH 0FF40H 0FF42H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF60H 0FF61H 0FF62H 0FF63H 0FF64H 0FF65H 0FF66H 0FF67H 0FF68H 0FF69H 0FF6AH 0FF6BH 0FF6CH 0FF6DH 0FF6EH 0FF6FH 0FF70H 0FF71H 0FF72H 0FF73H Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Pull-up resistor option register Clock output control register Port function control register Pull-up resistor option register 8-bit timer register 8-bit timer register Compare register (8-bit timer/counter Compare register (8-bit timer/counter 8-bit timer mode control register 8-bit timer mode control register Prescaler mode register Prescaler mode register 8-bit timer register 8-bit timer register 8-bit timer register 8-bit timer register Compare register (8-bit timer/counter Compare register (8-bit timer/counter Compare register (8-bit timer/counter Compare register (8-bit timer/counter 8-bit timer mode control register 8-bit timer mode control register 8-bit timer mode control register 8-bit timer mode control register Prescaler mode register Prescaler mode register Prescaler mode register Prescaler mode register Asynchronous serial interface mode register Asynchronous serial interface mode register Asynchronous serial interface status register Asynchronous serial interface status register PU10 PU12 CR10 CR1W CR20 TMC1 TMC1W TMC2 PRM1 PRM1W PRM2 TM5W TM7W CR50 CR5W CR60 CR70 CR7W CR80 TMC5 TMC5W TMC6 TMC7 TMC7W TMC8 PRM5 PRM5W PRM6 PRM7 PRM7W PRM8 ASIM1 ASIM2 ASIS1 ASIS2 TM1W bits bits 0000H After Reset
Note When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Table 7-1. Special Function Register (SFR) List (3/4)
Address Note Special Function Register (SFR) Name Symbol Units Manipulation 0FF74H Transmit shift register Receive buffer register 0FF75H Transmit shift register Receive buffer register 0FF76H 0FF77H 0FF7AH 0FF80H 0FF81H 0FF83H 0FF84H 0FF85H 0FF86H 0FF87H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH 0FF8DH 0FF90H 0FF91H 0FF92H 0FF94H 0FF95H 0FF96H 0FF98H 0FF99H 0FF9AH 0FF9BH 0FF9CH 0FFA0H 0FFA2H 0FFA8H 0FFA9H 0FFAAH 0FFACH 0FFADH External type select register External access status enable register Serial operation mode register Serial operation mode register Serial operation mode register Serial shift register Serial shift register Serial shift register Real-time output buffer register Real-time output buffer register Real-time output port mode register Real-time output port control register Watch timer mode control register External interrupt rising edge enable register External interrupt falling edge enable register In-service priority register Interrupt select control register Interrupt mode control register Interrupt mask flag register Interrupt mask flag register EBTS EXAE CSIM0 CSIM1 CSIM2 SIO0 SIO1 SIO2 RTBL RTBH RTPM RTPC WEGP0 EGN0 ISPR SNMI MK0L MK0H FFFFH Baud rate generator control register Baud rate generator control register Oscillation mode select register converter mode register converter input select register conversion result register conversion value setting register conversion value setting register converter mode register converter mode register correction control register correction address pointer correction address pointer TXS1 RXB1 TXS2 RXB2 BRGC1 BRGC2 ADIS ADCR DACS0 DACS1 DAM0 DAM1 CORC CORAH CORAL bits bits 0000H Undefined After Reset
Note When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Table 7-1. Special Function Register (SFR) List (4/4)
Address Note Special Function Register (SFR) Name Symbol Units Manipulation 0FFAEH 0FFAFH 0FFC0H 0FFC2H 0FFC4H 0FFC7H 0FFCEH 0FFCFH 0FFD0H 0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH 0FFF0H 0FFF1H 0FFF2H 0FFF3H 0FFF4H 0FFF5H 0FFF6H 0FFF7H 0FFF8H 0FFF9H 0FFFAH Interrupt control register (INTWDTM) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTCSI0) Interrupt control register (INTSER1) Interrupt control register (INTSR1/INTCSI1) Interrupt control register (INTST1) Interrupt control register (INTSER2) Interrupt control register (INTSR2/INTCSI2) Interrupt control register (INTST2) Interrupt control register (INTTM3) Interrupt control register (INTTM00) Interrupt control register (INTTM01) Interrupt control register (INTTM1) Interrupt control register (INTTM2) Interrupt control register (INTAD) Interrupt control register (INTTM5) Interrupt control register (INTTM6) Interrupt control register (INTTM7) Interrupt control register (INTTM8) Interrupt control register (INTWT) Interrupt control register (INTKR) WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CSIIC0 SERIC1 SRIC1 STIC1 SERIC2 SRIC2 STIC2 TMIC3 TMIC00 TMIC01 TMIC1 TMIC2 ADIC TMIC5 TMIC6 TMIC7 TMIC8 WTIC KRIC Interrupt mask flag register Interrupt mask flag register Standby control register Watchdog timer mode register Memory expansion mode register Programmable wait control register Clock status register Oscillation stabilization time specification register External area MK1L MK1H STBC PWC1 OSTS bits bits FFFFH After Reset
Note When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed.
Data Sheet U12303EJ1V0DS00
PD784217,784218
PERIPHERAL HARDWARE FUNCTIONS Ports
ports shown Figure provided make various control operations possible. Table shows function each port. Ports through connected internal pull-up resistors software when inputting. Figure 8-1. Port Configuration
PORT
PORT
PORT
PORT
PORT
P100 P103 P120
PORT
PORT PORT
PORT PORT PORT PORT PORT
P127 P130 P131
Data Sheet U12303EJ1V0DS00
PD784217,784218
Table 8-1. Port Functions
Port Name Name Function Specification Pull-up Resistor Connection Software specified 1-bit units specified 1-bit units specified 1-bit units specified 1-port units
Port Port Port Port Port
input output mode 1-bit units Input port input output mode 1-bit units input output mode 1-bit units input output mode 1-bit units directly drive LEDs input output mode 1-bit units directly drive LEDs input output mode 1-bit units input output mode 1-bit units input output mode 1-bit units N-ch open-drain port input output mode 1-bit units directly drive LEDs input output mode 1-bit units input output mode 1-bit units input output mode 1-bit units
Port
specified 1-port units
Port Port Port Port
specified 1-port units specified 1-bit units specified 1-bit units
Port Port Port
P100 P103 P120 P127 P130, P131
specified 1-bit units specified 1-bit units
Clock Generation Circuit
on-chip clock generation circuit necessary operation provided. This clock generation circuit frequency divider. high-speed operation necessary, internal operating frequency lowered frequency divider reduce current consumption. Figure 8-2. Block Diagram Clock Generation Circuit
Subsystem clock oscillation circuit Prescaler Selector
Watch timer, clock output function
Main system clock oscillation circuit
Prescaler
Clock peripheral hardware
Frequency divider
STOP
Selector Standby control circuit Wait control circuit clock (fCPU)
Data Sheet U12303EJ1V0DS00
PD784217,784218
Figure 8-3. Example Using Main System Clock Oscillation Circuit Crystal/ceramic oscillation External clock
Crystal resonator ceramic resonator
External clock PD74HCU04
Figure 8-4. Example Using Subsystem Clock Oscillation Circuit Crystal oscillation External clock
32.768
External clock
µPD74HCU04
Caution
When using main system clock subsystem clock oscillation circuits, wire broken-lines portions Figures follows avoid adverse influence from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential VSS. ground capacitor ground pattern through which high current flows. fetch signals from oscillator. Note that subsystem clock oscillation circuit amplification factor reduce current consumption.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Real-Time Output Port
real-time output function transfer data advance real-time output buffer register output latch hardware soon timer interrupt external interrupt occurred order output data external device. pins that output data external device constitute port called real-time output port. Because real-time output port output signals without jitter, ideal controlling stepping motor, etc. Figure 8-5. Block Diagram Real-Time Output Port
Internal Real-time output port control register (RTPC) RTPOE BYTE EXTR
INTP2TRG INTTM1 INTTM2 Output trigger control circuit
High-order bits real-time output buffer register (RTBH)
Low-order bits real-time output buffer register (RTBL) Real-time output port mode register (RTPM)
Port output latch
Real-time output port output latch
P120
RTP0
RTPOE
P12n/RTPn output
P120/ RTP7 RTP0
Data Sheet U12303EJ1V0DS00
PD784217,784218
Timer/Counter
unit 16-bit timers/counters units 8-bit timers/counters provided. Because total eight interrupt requests supported, these timers/counters used eight units timers/counters. Table 8-2. Operations Timers/Counters
Name Item Count width bits bits Operation mode Interval timer External event counter Function Timer output output output Square wave output One-shot pulse output Pulse width measurement Number interrupt requests inputs 16-Bit Timer/ Counter 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit 8-Bit Timer/ Timer/ Timer/ Timer/ Timer/ Timer/ Counter Counter Counter Counter Counter Counter
Data Sheet U12303EJ1V0DS00
PD784217,784218
Figure 8-6. Block Diagram Timers/Counters 16-bit timer/counter
Clear Selector
fXX/4 fXX/16 INTTM3
16-bit timer register (TM0)
Selector TI01 Edge detection circuit INTTM00 Output control circuit 16-bit capture/compare register (CR00) INTTM01 TI00 Edge detection circuit 16-bit capture/compare register (CR01)
8-bit timer/counter
fXX/22 fXX/23 Selector fXX/24 fXX/25 fXX/2
Clear Output control circuit Selector
8-bit timer register (TMn)
fXX/29 Edge detection circuit
8-bit compare register (CRn0) INTTMn
INTTMn
Remarks OVF: overflow flag 8-bit timer/counter
TMn-1 fXX/22 fXX/23 fXX/24 fXX/25 fXX/27 fXX/29 Edge detection circuit 8-bit compare register (CRn0) INTTMn Selector Clear Output control circuit
8-bit timer register (TMn)
Remarks OVF: overflow flag
Data Sheet U12303EJ1V0DS00
PD784217,784218
Converter
converter converts analog input variable into digital signal. This microcontroller provided with converter with resolution bits channels (ANI0 through ANI7). This converter successive approximation type result conversion stored 8-bit conversion result register (ADCR). converter started following ways: Hardware start Conversion started trigger input (P03). Software start Conversion started setting converter mode register (ADM). analog input channel selected from ANI0 through ANI7 conversion. When conversion started means hardware start, conversion stopped after been completed. When conversion started means software start, conversion repeatedly executed, each time conversion been completed, interrupt request (INTAD) generated. Figure 8-7. Block Diagram Converter
Series resistor string ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 AVSS Successive approximation register (SAR) Selector Voltage comparator Sample hold circuit selector AVDD AVREF0
INTP3/P03
Edge detection circuit
Control circuit
INTAD
Edge detection circuit
conversion result register (ADCR) INTP3 Internal
Data Sheet U12303EJ1V0DS00
PD784217,784218
Converter
converter converts input digital signal into analog voltage. This microcontroller provided with voltage output type converter with resolution bits channels. conversion method R-2R resistor ladder type. conversion started setting DACE0 converter mode register (DAM0) DACE1 converter mode register (DAM1). converter operates following modes: Normal mode converter outputs analog voltage immediately after completed conversion. Real-time output mode converter outputs analog voltage synchronization with output trigger after completed conversion. Figure 8-8. Block Diagram Converter
DACS0 ANO0 AVREF1
Selector DACS1 ANO1
Selector AVSS
Data Sheet U12303EJ1V0DS00
PD784217,784218
Serial Interface
Three independent serial interface channels provided. Asynchronous serial interface (UART)/3-wire serial (IOE) Clocked serial interface (CSI) 3-wire serial (IOE) Therefore, communication with external system local communication within system simultaneously executed (refer Figure 8-9). Figure 8-9. Example Serial Interface UART 3-wire serial
PD784218 (master) PD4711A
[UART] RxD1 RS-232-C driver/receiver TxD1
µPD75108 (slave)
SCK1 INTPm Port [UART] RxD2 Note [3-wire serial I/O] Port
Port
PD4711A
RS-232-C driver/receiver
TxD2
Port
Note Handshake line
Data Sheet U12303EJ1V0DS00
PD784217,784218
8.7.1 Asynchronous serial interface/3-wire serial (UART/IOE) channels serial interfaces that select asynchronous serial interface mode 3-wire serial mode provided. Asynchronous serial interface mode this mode, data byte following start transmitted received. Because on-chip baud rate generator provided, wide range baud rates set. Moreover, clock input ASCK divided define baud rate. When baud rate generator used, baud rate conforming MIDI standard (31.25 kbps) also obtained. Figure 8-10. Block Diagram Asynchronous Serial Interface Mode
Internal Receive buffer register (RXB1, RXB2) RxD1, RxD2 Receive shift register (RX1, RX2) Transmit shift register (TXS1, TXS2)
TxD1, TxD2 Receive control parity check INTSR1, INTSR2 Transmit control parity append INTST1, INTST2
Baud rate generator
Selector ASCK1, ASCK2
fXX/25
Data Sheet U12303EJ1V0DS00
PD784217,784218
3-wire serial mode this mode, master device starts transfer making serial clock active communicates 1-byte data synchronization with this clock. This mode used communicate with device having conventional clocked serial interface. Basically, communication established using three lines: serial clocks (SCK1 SCK2), serial data inputs (SI1 SI2), serial data outputs (SO1 SO2). connect more devices, handshake line necessary. Figure 8-11. Block Diagram 3-wire Serial Mode
Internal
SI1,
Serial shift register (SIO1, SIO2)
SO1, SCK1, SCK2 Serial clock counter Serial clock control circuit Interrupt generation circuit INTCSI1, INTCSI2 INTTM2 fXX/8 fXX/16
Selector
Data Sheet U12303EJ1V0DS00
PD784217,784218
8.7.2 Clocked serial interface (CSI) this mode, master device starts transfer making serial clock active communicates 1-byte data synchronization with this clock. 3-wire serial mode This mode communicate with devices having conventional clocked serial interface. Basically, communication established this mode with three lines: serial clock (SCK0) serial data (SI0 SO0) lines. Generally, handshake line necessary check reception status. Figure 8-12. Block Diagram 3-wire Serial Mode
Internal
Serial shift register (SIO0)
SCK0 Serial clock counter Serial clock control circuit Interrupt generation circuit INTCSI0 INTTM2 fXX/8 fXX/16
Selector
Clock Output Function
Clocks following frequencies output clock output. 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 (main system clock: 12.5 MHz) 32.768 (subsystem clock: 32.768 kHz) Figure 8-13. Block Diagram Clock Output Function
fXX/2 Selector fXX/22 fXX/23 fXX/24 fXX/25 fXX/2
Synchronization circuit
Output control circuit
fXX/27
Data Sheet U12303EJ1V0DS00
PD784217,784218
Buzzer Output Function
Clocks following frequencies output buzzer output. kHz/3.1 kHz/6.1 kHz/12.2 (@12.5-MHz operation main system clock) Figure 8-14. Block Diagram Buzzer Output Function
Selector
fXX/210 fXX/211 fXX/212 fXX/213
Output control circuit
8.10 Edge Detection Function
interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 through INTP6) used only input interrupt requests also input trigger signals internal hardware units. Because these pins operate edge input signal, they have function detect edge. Moreover, noise elimination circuit also provided prevent erroneous detection noise.
Name INTP0 through INTP6 Detectable Edge Either both rising falling edges Noise Elimination analog delay
8.11 Watch Timer
watch timer following functions: Watch timer Interval timer watch timer interval timer functions used same time. Watch timer watch timer sets WTIF flag interrupt control register (WTIC) time intervals seconds using 32.768-kHz subsystem clock. Interval timer interval timer generates interrupt request (INTTM3) predetermined time intervals.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Figure 8-15. Block Diagram Watch Timer
Selector INTWT
fXX/2
Selector
Selector
5-bit counter
Prescaler
Selector
INTTM3 16-bit timer/counter
8.12 Watchdog Timer
watchdog timer provided detect runaway. This watchdog timer generates non-maskable maskable interrupt unless cleared software within specified interval time. Once enabled operate, watchdog timer cannot stopped software. Whether interrupt watchdog timer interrupt input from takes precedence specified. Figure 8-16. Block Diagram Watchdog Timer
fCLK
Timer
fCLK/221 fCLK/220 Selector fCLK/219 fCLK/217 INTWDT
Clear signal
Remark CLK: Internal system clock (fXX fXX/8)
Data Sheet U12303EJ1V0DS00
PD784217,784218
INTERRUPT FUNCTION
servicing response interrupt request, three types shown Table selected program. Table 9-1. Servicing Interrupt Request
Servicing Mode Vectored interrupt Entity Servicing Software Servicing Branches executes servicing routine (servicing arbitrary) Automatically switches register bank, branches executes servicing routine (servicing arbitrary) Firmware Executes data transfer between memory (servicing fixed) Contents Saves restores from stack Saves restores from fixed area register bank
Context switching
Macro service
Retained
Interrupt Sources
Table shows interrupt sources available. shown, interrupts generated types sources, execution instruction, BRKCS instruction, operand error. priority interrupt servicing four levels, that nesting controlled during interrupt servicing that which more interrupts that simultaneously occur should serviced first. When macro service function used, however, nesting always proceeds. default priority priority (fixed) service that performed more interrupt requests, having same priority, simultaneously generate (refer Table 9-2).
Data Sheet U12303EJ1V0DS00
PD784217,784218
Table 9-2. Interrupt Sources
Type Software Default Priority Source Name instruction BRKCS instruction Operand error Trigger Instruction execution Instruction execution result exclusive between operands byte byte when STBC, #byte instruction, WDM, #byte instruction, LOCATION instruction executed input edge detection Overflow watchdog timer Overflow watchdog timer input edge detection External Internal Internal External Internal/ External Macro Service
Non-maskable Maskable
(highest)
INTWDT INTWDINTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTSER1 INTSR1 INTCSI1 INTST1 INTSER2 INTSR2 INTCSI2 INTST2 INTTM3 INTTM00
3-wire transfer CSI0 Occurrence UART reception error ASI1 UART reception ASI1 3-wire transfer CSI1 UART transmission ASI1 Occurrence UART reception error ASI2 UART reception ASI2 3-wire transfer CSI2 UART transmission ASI2 Reference time interval signal from watch timer Signal indicating coincidence between 16-bit timer register capture/compare register (CR00) Signal indicating coincidence between 16-bit timer register capture/compare register (CR01) Occurrence coincidence signal 8-bit timer/counter Occurrence coincidence signal 8-bit timer/counter conversion converter Occurrence coincidence signal 8-bit timer/counter Occurrence coincidence signal 8-bit timer/counter Occurrence coincidence signal 8-bit timer/counter Occurrence coincidence signal 8-bit timer/counter Overflow watch timer Detection falling edge port
Internal
INTTM01
(lowest)
INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR
External
Remark Asynchronous Serial Interface Clocked Serial Interface
Data Sheet U12303EJ1V0DS00
PD784217,784218
Vectored Interrupt
Execution branches servicing routine using memory contents vector table address corresponding interrupt source address branch destination. that performs interrupt servicing, following operations performed: branching: Saves status (contents PSW) stack returning Restores status (contents PSW) from stack return main routine from interrupt service routine, RETI instruction used. branch destination address range FFFFH. Table 9-3. Vector Table Address
Interrupt Source instruction TRAP0 (operand error) INTWDT (non-maskable) Vector Table Address 003EH 003CH 0002H 0004H Interrupt Source INTSER2 INSR2 INTCSI2 INTST2 INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD INTTM5 INTTM6 INTTM7 INTTM8 INTWT INTKR 001CH 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 0038H 003AH Vector Table Address 001EH 0020H
INTWD(maskable) 0006H INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTSER1 INTSR1 INTCSI1 INTST1 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH
Data Sheet U12303EJ1V0DS00
PD784217,784218
Context Switching
When interrupt request generated when BRKCS instruction executed, predetermined register bank selected hardware. Context switching function that branches execution vector address stored advance register bank, stack current contents program counter (PC) program status word (PSW) register bank. branch destination address range FFFFH. Figure 9-1. Context Switching Operation When Interrupt Request Generated
0000B Transfer Register bank PC19-16 PC15-0 Save (bits through temporary register) Exchange Save Temporary register Save
Register bank
Switching register bank (RBS0 RBS2
Macro Service
This function transfer data between memory special function register (SFR) without intervention CPU. macro service controller accesses memory same transfer cycle directly transfers data without loading Because this function does save restore status CPU, load data, data transferred high speeds. Figure 9-2. Macro Service
Read Memory Write Macro service controller
Write Read
Internal
Data Sheet U12303EJ1V0DS00
PD784217,784218
Application Example Macro Service
Transmission serial interface
Transmit data storage buffer (memory) Data Data
Data Data
Internal
TxD1, TxD2
Transmit shift register TXS1, TXS2 (SFR)
Transmit control
INTST1, INTST2
Each time macro service requests INTST1 INTST2 generated, next transmit data transferred from memory TXS1 TXS2. When data (last byte) been transferred TXS1 TXS2 (when transmit data storage buffer become empty), vectored interrupt requests INTST1 INTST2 generated. Reception serial interface
Receive data storage buffer (memory) Data Data
Data Data
Internal
Receive buffer register RXB1, RXB2 (SFR)
RxD1, RxD2
Receive shift register
Reception control
INTSR1, INTSR2
Each time macro service requests INTSR1 INTSR2 generated, receive data transferred from RXB1 RXB2 memory. When data (last byte) been transferred memory (when receive data storage buffer become full), vectored interrupt requests INTSR1 INTSR2 generated.
Data Sheet U12303EJ1V0DS00
PD784217,784218
LOCAL INTERFACE
local interface connect external memory (memory mapped I/O) support memory space Mbyte (refer Figure 10-1). Figure 10-1. Example Local Interface Multiplexed mode
µPD784218
SRAM Data I/O1 I/O8 Address Address latch
ASTB
Separate mode
µPD784218
SRAM
Address
I/O1 I/O8
Data
Data Sheet U12303EJ1V0DS00
PD784217,784218
10.1 Memory Expansion
External program memory data memory connected stages: Kbytes Mbyte. connect external memory, ports through port used. external memory connected following modes: Multiplexed mode external memory connected using time-division address/data bus. number ports used when external memory connected reduced this mode. Separate mode external memory connected using address data independent each other. Because external latch circuit necessary, this mode useful reducing number components mounting area printed wiring board.
10.2 Programmable Wait
Wait state(s) inserted memory space (00000H through FFFFFH) while signals active. addition, there address wait function that extends active period ASTB signal gain address decode time.
10.3 External Access Status Function
P37/EXA outputs active-low external access status signal. This signal informs other devices connected with external external access status, disables data output external other devices, enables reception. external access status signal output while external memory accessed.
Data Sheet U12303EJ1V0DS00
PD784217,784218
STANDBY FUNCTION
This function reduce power dissipation chip, used following modes: HALT mode Stops supply operating clock CPU. This mode used combination with normal operation mode intermittent operation reduce average power dissipation. IDLE mode Stops entire system with oscillation circuit continuing operation. power dissipation this mode close that STOP mode. However, time required restore normal program operation from this mode almost same that from HALT mode. STOP mode Stops main system clock thereby stop internal operations chip. Consequently, power dissipation minimized with only leakage current flowing. Power-saving mode main system clock stopped with subsystem clock used system clock. operate subsystem clock reduce current consumption. Power-saving HALT mode This standby function power-saving mode stops operation clock CPU, reduce power dissipation entire system. Power-saving IDLE mode This standby function power-saving mode stops entire system except oscillation circuit, reduce power dissipation entire system. These modes programmable. addition, macro service started HALT mode power-saving HALT mode. HALT mode restored again after execution macro service processing.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Figure 11-1. Transition Standby Status
Macro service
serv
Sets power-saving HALT mode Power-saving HALT mode (standby) Interrupt request masked interrupt Interrupt request Note
Powersaving mode (operation subsystem clock)
Sets power-saving IDLE mode
NMI, INP0 INTP6 input, INTWT, return interrupt Note
Power-saving IDLE mode (standby)
tores saving norm erati
Interrupt request masked interrupt
inte
inte
Waits oscillation stabilization
oscillati ation time stabiliz
STOP (standby)
IDLE Interrupt request (standby) masked interrupt
Interrupt request masked interrupt
Interrupt request masked interrupt
HALT (standby)
Notes Only interrupt requests that masked INTP0 INTP6, INTWT, return interrupts (P80 P87) only when they unmasked Remark valid external input only. watchdog timer cannot used release standby mode (HALT mode/STOP mode/IDLE mode).
Normal operation (operation main system clock)
Macro service request processing macro service
Macro service
Data Sheet U12303EJ1V0DS00
inpu
PD784217,784218
RESET FUNCTION
When low-level signal input RESET pin, system reset, each hardware unit initialized (reset). During reset period, oscillation main system clock unconditionally stopped. Consequently, current consumption entire system reduced. When RESET signal goes high, reset status cleared, oscillation stabilization time (84.0 12.5 MHz) elapses, contents reset vector table program counter (PC), execution branches address program execution started from that branch address. Therefore, program reset started from address. Figure 12-1. Oscillation Main System Clock during Reset Period
Main system clock oscillation circuit Oscillation unconditionally stopped during reset period fCLK
RESET input Oscillation stabilization time
RESET input analog delay noise elimination circuit prevent malfunctioning noise. Figure 12-2. Accepting Reset Signal
Oscillation Analog stabilization delay time
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
Data Sheet U12303EJ1V0DS00
PD784217,784218
CORRECTION
correction function replace part program internal with program internal execution. using this function, instruction found internal avoided, program flow changed. correction used four places internal (program). Figure 13-1. Block Diagram Correction
Program counter (PC)
Coincidence Comparator
Correction branch processing request signal (CALLT instruction)
Correction address pointer
Correction address register (CORAH, CORAL)
CORENn CORCHm correction control register (CORC) Internal
Remark
Data Sheet U12303EJ1V0DS00
PD784217,784218
INSTRUCTION
8-bit instructions (The instructions parentheses combinations realized describing MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 14-1. Instruction List 8-Bit Addressing
Second Operand #byte First Operand (MOV)
Note
saddr saddr'
!addr16 !!addr24
[saddrp] [%saddrg]
PSWL PSWH
[WHL+] [WHL-]
None
Note
(MOV) (XCH)
(MOV) Note (XCH) Note
(XCH)
(MOV) (XCH)
Note
Note
(MOV) (XCH) (ADD) Note Note MULU DIVUW
(ADD) Note (ADD) Note (ADD) Notes (ADD) Note
Note
(MOV) (XCH)
Note
Note
Note
(ADD) Note
saddr
Note
(MOV) Note
Note
Note
DBNZ PUSH
(ADD) Note
Note
Note
(ADD) Note (MOV)
Note
!addr16 !!addr24 [saddrp] [%saddrg] mem3
Note
ROR4 ROL4
PSWL PSWH STBC, [TDE+] [TDE-]
DBNZ (MOV) (ADD) MOVM
Note Note
MOVBK Note
Notes operands ADDC, SUB, SUBC, AND, XOR, same that ADD. Either second operand used, second operand operand address. operands ROL, RORC, ROLC, SHR, same that ROR. operands XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same that MOVM. operands XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same that MOVBK. code length some instructions having saddr2 saddr this combination short.
Data Sheet U12303EJ1V0DS00
PD784217,784218
16-bit instructions (The instructions parentheses combinations realized describing MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 14-2. Instruction List 16-Bit Addressing
Second Operand #word First Operand (MOVW) ADDW
Note
saddrp saddrp'
sfrp
!addr16 !!addr24
[saddrp] [%saddrg]
[WHL+]
byte
None
Note
(MOVW) (XCHW)
(MOVW) (MOVW) Note (XCHW) (XCHW)
Note
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
(ADD) Note (ADDW) Note (ADDW) Notes (ADDW) Note MOVW ADDW
Note
(MOVW) (XCHW) (ADDW)
Note
MOVW XCHW ADDW
Note
MOVW XCHW ADDW
Note
MOVW XCHW ADDW
Note
MOVW
SHRW SHLW
MULW
Note
INCW DECW INCW DECW
saddrp
MOVW ADDW
Note
(MOVW) Note (ADDW)
Note
MOVW ADDW
Note
MOVW XCHW ADDW
Note
sfrp
MOVW ADDW
Note
MOVW
MOVW
Note
PUSH MOVTBLW
(ADDW) Note ADDW (MOVW)
!addr16 !!addr24 [saddrp] [%saddrg]
MOVW
MOVW
MOVW
PUSH
ADDWG SUBWG
post
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes operands SUBW CMPW same that ADDW. Either second operand used, second operand operand address. code length some instructions having saddrp2 saddrp this combination short. operands MULUW DIVUX same that MULW.
Data Sheet U12303EJ1V0DS00
PD784217,784218
24-bit instructions (The instructions parentheses combinations realized describing MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 14-3. Instruction List 24-Bit Addressing
Second Operand #imm24 First Operand (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH saddrg !!addr24 mem1 [%saddrg] MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] None
Note
Note Either second operand used, second operand operand address.
Data Sheet U12303EJ1V0DS00
PD784217,784218
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR, BFSET Table 14-4. Instruction List Manipulation Instruction Addressing
Second Operand saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit First Operand !addr16.bit !!addr24.bit MOV1 AND1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 NOT1 SET1 CLR1 None
Note
Note Either second operand used, second operand operand address.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Call return instructions/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 14-5. Instruction List Call Return Instructions/Branch Instructions Addressing
Operand Instruction Address Basic instruction
Note
$addr20 $!addr20 !addr16 !!addr20
[rp]
[rg]
!addr11 [addr5]
None
CALL
CALL RETCS RETCSB
CALL
CALL
CALL
CALL
CALL
CALLF
CALLF
BRKCS RETI RETB
Compound instruction
BTCLR BFSET DBNZ
Note operands BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same that Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, SWRS
Data Sheet U12303EJ1V0DS00
PD784217,784218
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVSS AVREF0 AVREF1 Input voltage Analog input voltage Output voltage Output current, Total Total P10, P12, Output current, high Total Total P10, P12, Operating ambient temperature Storage temperature converter reference voltage input converter reference voltage input Other than Analog input N-ch open drain Conditions Ratings -0.3 +6.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 AVSS AVREF0 -0.3 Unit
Tstg
+150
Caution
Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Operating Conditions Operating ambient temperature +85°C Power supply voltage clock cycle time: Figure 15-1 Figure 15-1. Power Supply Voltage Clock Cycle Time
Clock Cycle Time tCYK [ns]
Guaranteed operating range
Supply Voltage
Capacitance
Parameter Input capacitance Symbol Unmeasured pins Output capacitance returned Conditions Other than Port Port Other than Port Port capacitance Other than Port Port MIN. TYP. MAX. Unit
Data Sheet U12303EJ1V0DS00
PD784217,784218
Main System Clock Oscillator Characteristics +85°C)
Resonator Recommended Circuit Ceramic resonator crystal resonator Parameter Oscillation frequency (fX) 6.25 Test Conditions MIN. TYP. MAX. 12.5 Unit
External clock
input frequency (fX)
12.5 6.25
PD74HCU04
input high/lowlevel width tWXL) input rising/ falling time (tXR, tXF)
Cautions When using main system clock oscillator, wire broken-lines portions above figures follows avoid adverse influence from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched back main system clock after oscillation stabilization time secured program.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Subsystem Clock Oscillator Characteristics +85°C)
Resonator Recommended Circuit Crystal resonator Parameter Oscillation frequency Test Conditions MIN. TYP. 32.768 MAX. Unit
Oscillation stabilization time Note
External clock
input frequency
PD74HCU04
input high/lowlevel width (tXTH tXTL)
Note Time required stabilize oscillation after reaches oscillator voltage MIN. Cautions When using subsystem clock oscillator, wire broken-lines portions above figures follows avoid adverse influence from wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring near signal line through which high fluctuating current flows. Always make ground point oscillator capacitor same potential ground capacitor ground pattern through which high current flows. fetch signals from oscillator. When main system clock stopped system operated subsystem clock, subsystem clock should switched back main system clock after oscillation stabilization time secured program.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Characteristics +85°C, AVDD AVSS (1/2)
Parameter Input voltage, Symbol VIL1 VIL2 Note Total P06, P20, P22, P33, P34, P70, P72, P100 P103, RESET (N-ch open drain) Total P17, P130, P131 Total XT1, P25, Note Total P06, P20, P22, P33, P34, P70, P72, P100 P103, RESET (N-ch open drain) Total P17, P130, P131 Total XT1, P25, pins other than P47, P57, Total P47, VOL2 Output voltage, high VOH1 -100 Input leakage current, ILIL1 Except XT1, XT1, Except XT1, XT1, VOUT VOUT VDD-1.0 VDD-0.5 Conditions MIN. TYP. MAX. 0.3VDD 0.2VDD Unit
VIL3 VIL4 VIL5 VIL6 Input voltage, high VIH1 VIH2
0.7VDD 0.8VDD
0.3VDD 0.3VDD 0.2VDD 0.3VDD
VIH3 VIH4 VIH5 VIH6 Output voltage, VOL1
0.7VDD 0.7VDD 0.8VDD 0.7VDD
ILIL2 Input leakage current, high ILIH1
ILIH2 Output leakage current, Output leakage current, high ILOL1 ILOH1
Note P21, P23, P24, P26, P32, P37, P47, P57, P67, P71, P87, P120 P127
Data Sheet U12303EJ1V0DS00
PD784217,784218
Characteristics (2/2)
Parameter Supply current Symbol Operation mode Conditions 12.5 MHz, MHz, HALT mode 12.5 MHz, MHz, IDLE mode 12.5 MHz, MHz, Operation mode
Note
MIN.
TYP.
MAX.
Unit
kHz, kHz,
HALT mode
Note
kHz, kHz,
IDLE mode Note
kHz, kHz,
Data retention voltage Data retention current
VDDDR DDDR
HALT, IDLE modes STOP mode
Pull-up resistor
Note When main system clock stopped Remark Unless otherwise specified, characteristics alternate-function pins same those port pins.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Characteristics +85°C, AVDD AVSS Read/write operation (1/2)
Parameter Cycle time (Minimum instruction execution time) Address setup time ASTB) tSAST Symbol tCYK Conditions Address hold time (from ASTB) tHSTLA ASTB high-level width tWSTH Address hold time (from tHRA delay time from address tDAR Address float time (from Data input time from address tFRA tDAID Data input time from ASTB tDSTID Data input time from tDRID delay time from ASTB tDSTR Data hold time (from Address active time from tHRID tDRA ASTB delay time from tDRST low-level width tWRL delay time from address tDAW Address hold time (from tHWA Data output delay time from ASTB tDSTOD 0.5T 0.5T 0.5T 0.5T (1.5 (1.5 0.5T 0.5T 0.5T 0.5T (2.5 (2.5 (1.5 (1.5 0.5T 0.5T (0.5 (0.5 0.5T 0.5T (0.5 (0.5 0.5T 0.5T MIN. TYP. MAX. Unit
Remark tCYK main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12303EJ1V0DS00
PD784217,784218
Characteristics Read/write operation (2/2)
Parameter Data output delay time from delay time from ASTB Symbol DWOD Conditions MIN. TYP. MAX. Unit
DSTW
0.5T 0.5T (1.5 (1.5 0.5T 0.5T 0.5T 0.5T (1.5 (1.5
Data setup time
SODWR
Data hold time (from
HWOD
ASTB delay time from
DWST
low-level width
Remark (fXX main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12303EJ1V0DS00
PD784217,784218
Characteristics External wait timing
Parameter WAIT input time from address Symbol tDAWT WAIT input time from ASTB tDSTWT WAIT hold time from ASTB tHSTWT WAIT delay time from ASTB tDSTWTH WAIT input time from tDRWTL WAIT hold time from tHRWT WAIT delay time from tDRWTH Data input time from WAIT tDWTID delay time from WAIT tDWTR delay time from WAIT tDWTW WAIT input time from tDWWTL WAIT hold time from tHWWT WAIT delay time from tDWWTH Conditions 1.5T 1.5T (0.5 (0.5 (1.5 (1.5 0.5T 0.5T 0.5T 0.5T 0.5T 0.5T MIN. TYP. MAX. Unit
Remark (fXX main system clock frequency) (during address wait), otherwise, Number wait states
Data Sheet U12303EJ1V0DS00
PD784217,784218
Serial Operation +85°C, AVDD 3-wire serial mode (SCK: internal clock output)
Parameter Serial clock cycle time (SCK) Symbol KCY1 Conditions MIN. 3200 Serial clock high-/low-level width tKH1, (SCK) setup time SCK) SIK1 1500 hold time (from SCK) output delay time (from SCK) KSI1 KSO1 TYP. MAX. Unit
3-wire serial mode (SCK: external clock input)
Parameter Serial clock cycle time (SCK) Symbol KCY2 Conditions MIN. 3200 Serial clock high-/low-level width tKH2, (SCK) setup time SCK) SIK2 1600 hold time (from SCK) output delay time (from SCK) KSI2 KSO2 TYP. MAX. Unit
UART mode
Parameter ASCK cycle time Symbol KCY3 Conditions MIN. 1667 ASCK high-/low-level width KH3, TYP. MAX. Unit
Data Sheet U12303EJ1V0DS00
PD784217,784218
Other Operations +85°C, AVSS
Parameter high-/low-level width Symbol tWNIL tWNIH tWITL tWITH tWRSL tWRSH INTP0 INTP6 Conditions MIN. TYP. MAX. Unit
INTP input high-/low-level width
RESET high-/low-level width
Clock Output Operation +85°C, AVDD AVSS
Parameter cycle time high-/low-level width Symbol tCYCL tCLL tCLH rising/falling time tCLR tCLF Conditions 0.5T MIN. TYP. MAX. 31250 15615 Unit
Remark tCYK main system clock frequency) Divided frequency ratio software When using main system clock: When using subsystem clock:
Data Sheet U12303EJ1V0DS00
PD784217,784218
Converter Characteristics +85°C,
Parameter Resolution Total error
Note
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
AVREF0 AVDD REF0 (only when AVREF0 AVDD)
Conversion time Sampling time Analog input voltage Reference voltage Resistance between AVREF0 AVSS
CONV SAMP VIAN AVREF0 RAVREF0
24/fXX AVSS 29.4
AVREF0 AVDD
Note Quantization error (±1/2 LSB) included. Remark Main system clock frequency Converter Characteristics +85°C,
Parameter Resolution Total error AVREF1 AVREF1 REF1 Settling time Load conditions: AVREF1 AVREF1 AVREF1 Output resistance Reference voltage AVREF1 current AVREF1 REF1 only channel DACS0, Symbol Conditions MIN. TYP. MAX. Unit
Data Sheet U12303EJ1V0DS00
PD784217,784218
Data Retention Characteristics +85°C,
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR +4.5 VDDDR +2.5 rising time falling time retention time (from STOP mode setting) STOP release signal input time tRVD tFVD tHVD Conditions MIN. TYP. MAX. Unit
tDREL Crystal resonator Ceramic resonator
0.9V DDDR 0.1V DDDR VDDDR
Oscillation stabilization wait time tWAIT
Low-level input voltage High-level input voltage
RESET, P00/INTP0 P06/INTP6
Timing Test Points
0.8VDD Test Points
0.8VDD
0.45
Data Sheet U12303EJ1V0DS00
PD784217,784218
Timing Wave Form Read operation
(CLK) tCYK
(Output) tDAID
Higher address tHRA tDRA Hi-Z Data (Output) tHRID tFRA Hi-Z
Higher address
tDSTID (Input/output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tHSTHA
tWSTH tDSTR tDAR tDRID tWRL tDRWTL tDAWT tDRWTH tHRWT tDWTR tDWTID tDRST
(Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Data Sheet U12303EJ1V0DS00
PD784217,784218
Write operation
(CLK) tCYK
(Output) tDAID
Higher address tHWA tDAW Hi-Z Data (Output) tHWOD tFRA tSODWR Hi-Z
Higher address
tDSTOD (Input/output) Hi-Z Lower address (Output) tSAST ASTB (Output) tHSTLA
Lower address (Output)
tHSTHA
tWSTH tDSTW tDAW tDWOD tWWL tDWWTL tDAWT tDWWTH tHWWT tDWTW tDWTID tDWST
(Output)
WAIT (Input) tDSTWT tDSTWTH tHSTWT
Data Sheet U12303EJ1V0DS00
PD784217,784218
Serial Operation 3-wire serial mode
tKCY1, tKH1, tKL1, tKSO1, tKSI1, tSIK1, SI/SO
UART mode
tKCY3 tKH3 ASCK tKL3
Data Sheet U12303EJ1V0DS00
PD784217,784218
Clock Output Timing
tCLH
tCLL
CLKOUT tCLR tCYCL tCLF
Interrupt Input Timing
tWNIH
tWNIL
tWITH
tWITL
INTP0 INTP6
Reset Input Timing
tWRSH
tWRSL
RESET
Data Sheet U12303EJ1V0DS00
PD784217,784218
Clock Timing
tWXH
tWXL
1/fX
tXTH
tXTL
1/fXT
Data Retention Characteristics
STOP mode setting
tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
(Clearing falling edge)
(Clearing rising edge)
Data Sheet U12303EJ1V0DS00
PD784217,784218
PACKAGE DRAWINGS
PLASTIC LQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.08 (0.003 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 16.00±0.20 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.00±0.20 0.50±0.20 0.17 +0.03 -0.07 0.08 1.40±0.05 0.10±0.05 1.60 MAX. INCHES 0.630±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630±0.008 0.039 0.039 0.009±0.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.055±0.002 0.004±0.002 0.063 MAX. S100GC-50-8EU
Remark external dimensions material version same those mass-produced version.
Data Sheet U12303EJ1V0DS00
PD784217,784218
100PIN PLASTIC (14x20)
detail lead
ITEM MILLIMETERS 23.6±0.4 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX. INCHES 0.929±0.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.693±0.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.004±0.004 5°±5° 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline located within 0.15 (0.006 inch) true position (T.P.) maximum material condition.
Remark external dimensions material version same those mass-produced version.
Data Sheet U12303EJ1V0DS00
PD784217,784218
RECOMMENDED SOLDERING CONDITIONS
PD784218 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Caution Soldering conditions undetermined because these products under development. Table 17-1. Soldering Conditions Surface Mount Type 100-pin plastic LQFP (Fine pitch)
Recommended Condition Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: sec. Max. 210°C higher), Count: times less, Exposure limit: days Note (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: sec. Max. 200°C higher), Count: times less, Exposure limit: days Note (after that, prebake 125°C hours) temperature: 300°C Max., Time: sec. Max. (per row)
VP-15-107-2
Partial heating
Note After opening pack, keep place 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
100-pin plastic (Fine pitch)
Recommended Condition Symbol IR35-00-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: sec. Max. 210°C higher), Count: times less Package peak temperature: 215°C, Time: sec. Max. 200°C higher), Count: times less Solder bath temperature: 260°C Max., Time: sec. Max., Count: once, Preheating temperature: 120°C Max. (package surface temperature) temperature: 300°C Max., Time: sec. Max. (per row)
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
Caution
different soldering methods together (except partial heating).
Data Sheet U12303EJ1V0DS00
PD784217,784218
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using PD784218. Also refer Cautions Using Development Tools. Language Processing Software
RA78K4 CC78K4 DF784218 CC78K4-L Assembler package common 78K/IV Series compiler package common 78K/IV Series Device file common µPD784218 Subseries compiler library source file common 78K/IV Series
Flash Memory Writing Tools
Flashpro (Model number: FL-PR2), Flashpro (Model number: FL-PR3, PG-FP3) FA-100GF Dedicated flash programmer microcontroller incorporating flash memory
Adapter writing 100-pin plastic (GF-3BA type) flash memory. Connection must performed depending target product. Adapter writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must performed depending target product. Control program that runs personal computer attached Flashpro Flashpro III. Operates Windows TM95, etc.
FA-100GC
Flashpro controller, Flashpro controller
Debugging Tools When IE-78K4-NS in-circuit emulator used
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A Note In-circuit emulator common 78K/IV Series Power supply unit IE-78K4-NS Interface adapter used when PC-9800 series (except notebook type) used host machine supported) card cable when PC-9800 series notebook used host machine (PCMCIA socket supported) Interface adapter when using PC/ATand compatibles host machine (ISA supported) Interface adapter when using that incorporates host machine Emulation board emulate PD784218 Subseries Emulation probe 100-pin plastic (GF-3BA type) Emulation probe 100-pin plastic LQFP (GC-8EU type) Socket mounted target system board made 100-pin plastic (GF-3BA type) Conversion adapter connect NP-100GC target system board which 100pin plastic LQFP (GC-8EU type) mounted Integrated debugger IE-78K4-NS System simulator common 78K/IV Series Device file common µPD784218 Subseries
IE-70000-PC-IF-C IE-70000-PCI-IF Note IE-784225-NS-EM1 NP-100GF NP-100GC EV-9200GF-100 TGC-100SDW
ID78K4-NS SM78K4 DF784218
Note Under development
Data Sheet U12303EJ1V0DS00
PD784217,784218
When IE-784000-R in-circuit emulator used
In-circuit emulator common 78K/IV Series Interface adapter used when PC-9800 series (except notebook type) used host machine supported) Interface adapter cable used when PC-9800 series notebook type used host machine Interface adapter when using PC/AT compatibles host machine (ISA supported) Interface adapter when using that incorporates host machine Interface adapter cable used when used host machine Emulation board emulate µPD784218 Subseries
IE-784000-R IE-70000-98-IF-C
IE-70000-98N-IF
IE-70000-PC-IF-C IE-70000-PCI-IF Note IE-78000-R-SV3 IE-784225-NS-EM1 IE-784218-R-EM1 IE-784000-R-EM IE-78K4-R-EX3
Emulation board common 78K/IV Series Emulation probe conversion board necessary when using IE-784225-NS-EM1 IE-784000-R. necessary when IE-784218-R-EM1 used. Emulation probe 100-pin plastic (GF-3BA type) Emulation probe 100-pin plastic LQFP (GC-8EU type) Socket mounted target system board made 100-pin plastic (GF-3BA type) Conversion adapter connect NP-100GC target system board which 100pin plastic LQFP (GC-8EU type) mounted Integrated debugger IE-784000-R System simulator common 78K/IV Series Device file common PD784218 Subseries
EP-78064GF-R EP-78064GC-R EV-9200GF-100 TGC-100SDW
ID78K4 SM78K4 DF784218
Note Under development Real-time
RX78K/IV MX78K4 Real-time 78K/IV Series 78K/IV Series
Data Sheet U12303EJ1V0DS00
PD784217,784218
Cautions Using Development Tools ID78K4-NS, ID78K4, SM78K4 used combination with DF784218. CC78K4 RX78K/IV used combination with RA78K4 DF784218. FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, NP-100GC products made Naitou Densei Machidaseisakusho Co., Ltd. (TEL: +81-44-822-3813). Contact distributor regarding purchase these products. TGC-100SDW product made TOKYO ELETECH CORPORATION. further information, contact Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL: +81-3-3820-7112) Osaka Electronics Department (TEL: +81-6-6244-6672) third party development tools, 78K/IV Series Selection Guide (U13355E). host machine suitable each software follows:
Host Machine [OS] Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4 PC-9800 series [Windows] PC/AT compatibles [Japanese/English Windows] Note Note
Note Note
HP9000 Series [HP-UX SPARCstation[SunOSTM, SolarisTM] NEWS(RISC) [NEWS-OSTM]
Note DOS-based software
Data Sheet U12303EJ1V0DS00
PD784217,784218
APPENDIX RELATED DOCUMENTS
Documents related device
Document Name Japanese Document English This document U12439E U12970E U10905E U10095E
µPD784217, 784218 Data Sheet µPD78F4218 Preliminary Product Information µPD784218, 784218Y Subseries User's Manual Hardware µPD784218 Subseries Special Function Register Table
78K/IV Series User's Manual Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction 78K/IV Series Application Note Software Basics
U12303J U12439J U12970J U12918J U10905J U10594J U10595J U10095J
Documents related development tool (User's Manual)
Document Name Japanese RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 Compiler Language Operation IE-78K4-NS IE-784000-R IE-784218-R-EM1 IE-784225-NS-EM1 EP-78064 SM78K4 System Simulator Windows Based SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Reference U11334J U11162J U11743J U11571J U11572J U13356J U12903J U12155J U13742J EEU-934 U10093J U10092J Document English U11334E U11162E U11743E U11571E U11572E U13356E U12903E U12155E prepared EEU-1469 U10093E U10092E
ID78K4-NS Integrated Debugger Based ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based
U12796J U10440J U11960J
U12796E U10440E U11960E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Documents related embedded software (User's Manual)
Document Name Japanese 78K/IV Series Real-Time Basics Installation Debugger 78K/IV Series MX78K4 Basics U10603J U10604J U10364J U11779J Document English U10603E U10604E
Other documents
Document Name Japanese Package Manual (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Guide Prevent Damage Semiconductor Devices Electrostatic Discharge (ESD) Guide Quality Assurance Semiconductor Devices Guide Microcontroller-Related Products Third Parties U11416J MEI-1202 C10535J C11531J C10983J C11892J Document English C13388E C10535E C11531E C10983E C11892E
Caution
related documents listed above subject change without notice. sure latest version each document designing.
Data Sheet U12303EJ1V0DS00
PD784217,784218
[MEMO]
Data Sheet U12303EJ1V0DS00
PD784217,784218
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U12303EJ1V0DS00
PD784217,784218
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J98.
Data Sheet U12303EJ1V0DS00
PD784217,784218
IEBus trademark Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/ other countries. PC/AT trademark International Business Machines Corporation. HP9000 Series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. Solaris SunOS trademarks Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation. related documents indicated this publication include preliminary versions. However, preliminary versions marked such.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
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