µPD78056F,78058F 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTI

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µPD78056F,78058F 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTI

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INTEGRATED CIRCUIT
µPD78056F,78058F
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78056F,78058F reduce electromagnetic interference (EMI) noise comparison with conventional µPD78056F,78058F. PD78056F,78058F belong PD78058F Subseries products 78K/0 Series. These microcontrollers include variety peripheral hardware, such 8-bit resolution converter, 8-bit resolution converter, timer, serial interface, real-time output ports, interrupt functions. PD78P058FY, one-time PROM which operated same supply voltage range mask version, various development tools also available. Detailed function descriptions provided following user's manual. sure read them before designing.
PD78058F, 78058FY Subseries User's Manual: U12068E 78K/0 Series User's Manual-Instruction: U12326E
FEATURES noise reduction version (The overall peak level reduced dB.) Large on-chip
Items Products Data Memory
Internal HighSpeed Buffer Internal Expansion
Program Memory (ROM) Kbytes Kbytes
Packages 80-pin plastic resin thickness 80-pin plastic resin thickness 80-pin plastic TQFP (fine pitch) mm)Note
PD78056F PD78058F
1024 bytes
bytes
None 1024 bytes
Note This package available only PD78058F.
External memory expansion space: Kbytes Minimum instruction execution time varied from high-speed (0.4 ultra-low-speed (122 ports: (N-ch open-drain: 8-bit resolution converter: channels 8-bit resolution converter: channels Serial interface: channels Timer: channels Supply voltage:
APPLICATIONS
Cellular phones, pagers, printers, equipment, conditioners, cameras, PPC, fuzzy home appliances, vending machines, etc.
information this document subject change without notice. Document U11795EJ2V0DS00 (2nd edition) Date Published September 1997 Printed Japan mark shows major revised points.
1997
µPD78056F, 78058F
ORDERING INFORMATION
Part Number Package 80-pin 80-pin 80-pin 80-pin 80-pin plastic plastic plastic plastic plastic resin thickness resin thickness resin thickness resin thickness TQFP (fine pitch)
Caution
µPD78056FGC, µPD78058FGC come types packages (see Package Drawings). packages that supplied, consult your local sales representative. denotes code number.
Remark
µPD78056F, 78058F
78K/0 SERIES PRODUCT DEVELOPMENT
These products further development 78K/0 Series. designations appearing inside boxes subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44pin
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
µPD78075BY µPD78078Y µPD78070AY µPD780018AY µPD780058YNote µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y
noise reduction version µPD78078 timer added µPD78054 external interface function enhanced ROM-less versions PD78078 Serial PD78078Y enhanced only selected functions provided Serial PD78054 enhanced, noise reduction version noise reduction version µPD78054 UART converter were added µPD78014 enhanced converter PD780024 enhanced Serial PD78018F enhanced, noise reduction version noise reduction version PD78018F Low-voltage (1.8 operation versions PD78014 with several capacities available converter 16-bit timer were added µPD78002 converter added µPD78002 Basic subseries control On-chip UART, capable operating voltage (1.8
Inverter Control 64-pin 78K/0 series 64-pin 64-pin
PD780988 µPD780964 µPD780924
Inverter control, timer µPD780964 were enhanced were expanded converter PD780924 enhanced On-chip inverter control circuit UART, noise reduction version
FIPdrive 100-pin 100-pin 80-pin 80-pin
µPD780208 µPD780228 µPD78044H µPD78044F
PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total: N-ch open drain added µPD78044H, Display output total: Basic subseries driving FIP, Display output total:
drive 100-pin 100-pin 100-pin
µPD780308 µPD78064B µPD78064
µPD780308Y µPD78064Y
µPD78064 enhanced were expanded noise reduction version PD78064 Subseries driving LCDs, On-chip UART
IEBussupported 80-pin 80-pin
µPD78098B µPD78098
Meter control
noise reduction version PD78098 IEBus contorller added PD78098
80-pin
µPD780973
On-chip controller /driver automobile meter drive
64-pin
µPD78P0914
On-chip output, digital code decoder, Hsync counter
Note Under planning
µPD78056F, 78058F
major functional differences among subseries shown below.
Function Subseries Control µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 Inverter control drive µPD780988 µPD780964 µPD780924 µPD780208 µPD780228 µPD78044H µPD78044F drive µPD78064B µPD78064 IEBus Meter control µPD78P0914 Available µPD78098B µPD780973 supported µPD78098 K-32 K-60 K-60 K-32 (UAR: 1ch) (UART: 1ch) Available µPD780308 K-60 K-60 K-48 K-40 K-60 (time-division UART: (UART: 1ch) K-60 K-32 Note Note K-60 K-32 K-16 (UART: 1ch) (UART: 2ch) (UART 2ch) Available Available Capacity Timer 16-bit Watch 8-bit 10-bit 8-bit Serial Interface MIN. External Value Expansion (time-division UART: 1ch) K-60 K-60 K-32 (UART: 1ch, time-division 3-wire 1ch) (UART: 1ch) Available
8-bit
K-40 K-60 K-60
(UART: 1ch)
Notes 16-bit timer channel 10-bit timer channel 10-bit timer channel
µPD78056F, 78058F
OVERVIEW FUNCTION
Product Name Item Internal memory High-speed Buffer Expanded
PD78056F
PD78058F
Memory space General registers Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction
Kbytes Kbytes 1024 bytes bytes None 1024 Kbytes Kbytes bits registers bits registers banks) On-chip instruction execution time cycle modification function µs/0.8 s/1.6 µs/3.2 s/6.4 µs/12.8 5.0-MHz operation) 32.768-kHz operation) 16-bit operation Multiplication/division bits bits,16 bits bits) manipulation (set, reset, test, Boolean operation) correction, etc.
ports
Total CMOS input CMOS N-ch open-drain
converter converter Serial interface
8-bit resolution channels 8-bit resolution channels 3-wire serial I/O/SBI/2-wire serial I/O/I2 mode selectable: channel 3-wire serial mode (on-chip max. bytes automatic data transmit/receive function): channel 3-wire serial I/O/UART mode selectable: channel 16-bit timer/event counter channel 8-bit timer/event counter channels Watch timer channel Watchdog timer channel
Timer
Timer output Clock output
(14-bit output 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, (main system clock: 5.0-MHz operation) 32.768 (subsystem clock: 32.768-kHz operation) kHz, kHz, kHz, (main system clock: 5.0-MHz operation) Maskable Non-maskable Software Internal external Internal Internal external 85°C 80-pin plastic resin thickness 80-pin plastic resin thickness 80-pin plastic TQFP (fine pitch) Note
Buzzer output Vectoredinterrupt source
Test input Supply voltage Operating ambient temperature Package
Note µPD78058F only
µPD78056F, 78058F
CONTENTS CONFIGURATION (TOP VIEW) BLOCK DIAGRAM FUNCTIONS Port Pins Non-port Pins Circuits Recommended Connection Unused Pins
MEMORY SPACE PERIPHERAL HARDWARE FUNCTION FEATURES Ports Clock Generator Timer/Event Counter Clock Output Control Circuit Buzzer Output Control Circuit Converter Converter Serial Interfaces Real-Time Output Port Functions
INTERRUPT FUNCTIONS TEST FUNCTIONS Interrupt Functions Test Functions EXTERNAL DEVICE EXPANSION FUNCTIONS STANDBY FUNCTION RESET FUNCTION
INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78056F, 78058F
CONFIGURATION (TOP VIEW)
80-pin plastic resin thickness 80-pin plastic resign thickness
P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 XT1/P07 AVREF0
80-pin plastic TQFP (fine pitch)
P01/INTP1/TI01
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1
P00/INTP0/TI00
AVDD
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
Cautions Connect directly Internally Connected (IC) AVDD functions both converter power supply port power supply. When µPD78056F 78058F used applications where noise generated inside microcontroller needs reduced, connect another power supply which same potential VDD. functions both converter ground port ground. When µPD78056F 78058F used applications where noise generated inside microcontroller needs reduced, connect ground line other than
P64/RD
µPD78056F, 78058F
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD
Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12
AVREF0 AVREF1 AVSS BUSY INTP0 INTP6 P120 P127
P130, P131 RESET RTP0 RTP7 SB0, SCK0 SCK2 TI00, TI01 TI1, TI2, WAIT XT1,
Port13 Programmable Clock Read Strobe Reset Real-Time Output Port Receive Data Serial Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
µPD78056F, 78058F
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER WATCHDOG TIMER
PORT1
PORT2
PORT3
WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72
PORT4
SERIAL INTERFACE 78K/0 CORE SERIAL INTERFACE
PORT5
PORT6
PORT7
PORT12 SERIAL INTERFACE PORT13
P120 P127
P130, P131
ANI0/P10 ANI7/P17 AVREF0
CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127 AD0/P40 AD7/P47 A8/P50 A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67
ANO0/P130, ANO1/P131 AVREF1
CONVERTER
EXTERNAL ACCESS
INTP0/P00 INTP6/P06 BUZ/P36
INTERRUPT CONTROL BUZZER OUTPUT SYSTEM CONTROL CLOCK OUTPUT CONTROL
PCL/P35
AVDD AVSS
RESET XT1/P07
Remark internal capacity depends product.
µPD78056F, 78058F
FUNCTIONS
Port Pins (1/2)
After Reset Input Input Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6 Input Input/ output Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.Note Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input SCK1 BUSY SI0/SB0 SO0/SB1 SCK0 Input/ output Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Input Input/ output Port 8-bit input/output port. Input/output specified 8-bit unit. When used input port, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection. Input Input only Input Input ANI0 ANI7
Name
Note
Input Input/ output Port 8-bit port
Function Input only Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input/ output
Notes When using P07/XT1 pins input port, (FRC) processor clock control register. On-chip feedback resistor subsystem clock oscillator should used. When using P10/ANI0 P17/ANI7 pins converter analog input pins, on-chip pullup resistor cancelled automatically.
µPD78056F, 78058F
Port Pins (2/2)
After Reset Input Alternate Function
Name
Input/ output
Function Port 8-bit input/output port. driven directly. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/outport port. Input/output specified bit-wise. N-ch open-drain input/output port. On-chip pull-up resistor specified mask option. driven directly. When used input port, on-chip pull-up resistor used software.
Input/ output
Input
Input
WAIT ASTB
Input/ output
Port 3-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 8-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software. Port 2-bit input/output port. Input/output specified bit-wise. When used input port, on-chip pull-up resistor used software.
Input
SI2/RxD SO2/TxD SCK2/ASCK
P120 P127 Input/ output
Input
RTP0 RTP7
P130, P131
Input/ output
Input
ANO0, ANO1
Caution pins which also function port pins, perform following operations during conversion. these operations performed, total error ratings cannot kept (except segment output alternate-function pin). Rewrite output latch which used port pin. Change output level used output pin, even used port pin.
µPD78056F, 78058F
Non-port Pins (1/2)
Input Function External interrupt request input which effective edge (rising edge, falling edge, both rising edge falling edge) specified. After Reset Input Alternate Function P00/TI00 P01/TI01 Input Serial interface serial data input. Input P25/SB0 P70/RxD Output Serial interface serial data output. Input P26/SB1 P71/TxD Input /output Serial interface serial data input/output. Input P25/SI0 P26/SO0 P25/SI0 P26/SO0 Input /output Serial interface serial clock input/ output Input P72/ASCK Output Input Input Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) Output 16-bit timer (TM0) output (alternate function 14-bit output) 8-bit timer (TM1) output 8-bit timer (TM2) Output Output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Real-time output port which data output synchronization with trigger. Input /output Low-order address/data external memory expansion. Input Input Input Input Input Input Input Input Input Input Input P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1 P120 P127
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SDA0 SDA1 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01
RTP0 RTP7 Output
µPD78056F, 78058F
Non-port Pins (2/2)
After Reset Input Input Alternate Function Input Input
Name WAIT ASTB
Output Output
Function High-order address external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Output
Wait insertion external memory access. Strobe output which latches address information output port access external memory.
ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD AVSS RESET
Input Output Input Input Input Input Input
converter analog input. converter analog output. converter reference voltage input. converter reference voltage input. converter analog power supply (shared with port power supply) converter ground potential (shared with port ground potential) System reset input. Main system clock oscillation crystal connection.
Input Input
P130, P131
Subsystem clock oscillation crystal connection.
Input
Positive power supply (except port). Ground potential (except port). Internally connected. Connect directly VSS.
Cautions
functions both converter power supply port power supply. When µPD78056F 78058F used applications where noise generated inside microcontroller needs reduced, connect another power supply which same potential VDD. functions both converter converter ground port ground. When µPD78056F 78058F used applications where noise generated inside microcontroller needs reduced, connect AVSS ground line other than
µPD78056F, 78058F
Circuits Recommended Connection Unused Pins input/output circuit type each recommended connection unused pins shown Table 3-1. input/output circuit configuration each type, Figure 3-1.
Table 3-1. Input/Output Circuit Type Each (1/2)
Input/output Circuit Type
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7
Input Input/output
Recommended Connection when Used Connect Independently connect through resistor.
11-C
Input Input/output
Connect Independently connect through resistor.
P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7
10-C
Independently connect through resistor.
P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB
13-I
Independently connect through resistor. Independently connect through resistor. Independently connect through resistor.
µPD78056F, 78058F
Table 3-1. Input/Output Circuit Type Each (2/2)
Input/output Circuit Type
Name P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0 P131/ANO1 RESET AVREF0 AVREF1 AVDD
Input/ output
Recommended Connection when Used Independently connect through resistor.
12-B
Independently connect through resistor.
Input Leave open. Connect Connect
Connect another power supply which same potential VDD.
AVSS
Connect another ground line which same potential Connect directly
µPD78056F, 78058F
Figure 3-1. Input/Output Circuits (1/2)
Type
Type AVDD
pullup enable data AVDD P-ch
P-ch
IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic output disable N-ch AVSS
Type pullup enable AVDD data
AVDD
Type 10-C
AVDD
P-ch
pullup enable AVDD data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable N-ch AVSS
output disable
N-ch AVSS
input enable Type AVDD Type 11-C pullup enable data AVDD P-ch AVDD P-ch IN/OUT IN/OUT output disable N-ch AVSS input enable output disable Comparator N-ch P-ch AVSS AVSS N-ch VREF (Threshold Voltage)
pullup enable AVDD data P-ch
P-ch
µPD78056F, 78058F
Figure 3-1. Input/Output Circuits (2/2)
Type 12-B pullup enable AVDD data
AVDD
Type feed back cut-off P-ch
P-ch
P-ch IN/OUT
output disable AVSS input enable
N-ch
P-ch Analog Output Voltage N-ch AVSS
Type 13-I AVDD Mask Option IN/OUT data output disable N-ch AVSS AVDD
P-ch
Middle-High Voltage Input Buffer
µPD78056F, 78058F
MEMORY SPACE
Figure shows memory µPD78056F,78058F. Figure 4-1. Memory
FFFFH Special Function Registers (SFR) bits FF00H FEFFH FEE0H FEDFH
General Registers bits
FA7FH Prohibited F800H F7FFH
Internal High-Speed 1024 bits FB00H FAFFH Prohibited Data Memory Space FAE0H FADFH Buffer bits FAC0H FABFH Prohibited FA80H FA7FH
Internal Expanded 1024 bits F400H F3FFH Prohibited Note F000H nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH
Note
External Memory Program Memory Space nnnnH nnnnH 0080H 007FH
Program Area
CALLT Table Area 0040H 003FH Vector Table Area
Internal
Note
0000H
0000H
Notes PD78058F only When external device expansion function used with µPD78058F, internal capacity Kbytes less using memory size switching register (IMS). internal capacity internal high-speed capacity depend products (see table below).
Internal Last Address nnnnH BFFFH EFFFH
Target Product
PD78056F µPD78058F
µPD78056F, 78058F
PERIPHERAL HARDWARE FUNCTION FEATURES
Ports following types ports available. CMOS input (P00, P07) CMOS input/output (P01 P06, port port P67, port port port N-ch open-drain input/output (P60 P63) Total
Table 5-1. Port Functions
Name Port
Name P00, Dedicated input port pins
Function
Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software.
Port Port
Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software.
Port
Port
Input/output port pins. Input/output specifiable 8-bit units. When used input port pins, on-chip pull-up resistor used software. Test input flag (KRIF) falling edge detection.
Port
Input/output port pins. Input/output specifiable bit-wise. When used input port pins, on-chip pull-up resistor used software. direct drive capability.
Port
N-channel open-drain input/output port pins. Input/output specifiable bit-wise. On-chip pull-up resistor used mask option. direct drive capability.
Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software.
Port Port
P120 P127
Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software. Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software.
Port
P130, P131
Input/output port pins. Input/output specifiable bit-wise. When used input/output port pins, on-chip pull-up resistor used software.
µPD78056F, 78058F
Clock Generator types generators, main system clock generator subsystem clock generator, avaibable. minimum instruction execution time also changed. s/0.8 µs/1.6 s/3.2 s/6.4 µs/12.8 (main system clock: 5.0-MHz operation) (subsystem clock: 32.768-kHz operation) Figure 5-1. Clock Generator Block Diagram
XT1/P07 Subsystem Clock Oscillator Watch Timer, Clock Output Function Prescaler Main System Clock Oscillator Divider STOP Selector Prescaler Selector Standby Control Circuit Wait Control Circuit Clock (fCPU) Clock Peripheral Hardware
INTP0 Sampling Clock
Timer/Event Counter timer/event counter channels incorporated. 16-bit timer/event counter channel 8-bit timer/event counter channels Watch timer channel Watchdog timer channel Table 5-2. Operation Timer/Event Counter
16-Bit Timer/Event Counter Operation mode Interval timer External event counter Function Timer output output Pulse width measurement Square wave output One-shot pulse output Interrupt request Test input output output input output output input outputs outputs channel channel channels channels channel channel
8-Bit Timer/Event Counter
Watch Timer
Watchdog Timer
µPD78056F, 78058F
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX/2 fXX/2 TI00/P00/INTP0 Edge Detction Circuit Match Selector 16-Bit Timer Register (TM0) Clear
pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector INTTM01 INTP0
16-Bit Capture/ Compare Register (CR01)
Internal
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match fxx/2-fxx/2 fxx/2 TI1/P33 Selector 8-Bit Timer Register (TM1) Selector Clear 8-Bit Timer Register (TM2) Clear Selector Selector
Output Control Circuit
TO2/P32 INTTM2
fxx/2-fxx/2 fxx/2 TI2/P34
Output Control Circuit Internal
TO1/P31
µPD78056F, 78058F
Figure 5-4. Watch Timer Block Diagram
Selector XX/27 Selector
5-Bit Counter Selector
Prescaler
INTWT
Selector
INTTM3 16-Bit Timer/ Event Counter
Figure 5-5. Watchdog Timer Block Diagram
Prescaler
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
µPD78056F, 78058F
Clock Output Control Circuit Clock with following frequencies output clock output. 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 (main system clock: 5.0-MHz operation) 32.768 (subsystem clock: 32.768-kHz operation) Figure 5-6. Clock Output Control Block Diagram
Selector Synchronization Circuit Output Control Circuit PCL/P35
Buzzer Output Control Circuit Clock with following frequencies output buzzer output. kHz/2.4 kHz/4.9 kHz/9.8 (main system clock: 5.0-MHz operation)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
Selector Output Control Circuit BUZ/P36
µPD78056F, 78058F
Converter converter 8-bit resolution channels incorporated. following types conversion operation start-up methods available. Hardware start Software start Figure 5-8. Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive Approximation Register (SAR) AVSS Selector AVSS Selector Sample Hold Circuit Voltage Comparator AVDD AVREF0
INTP3/P03
Edge Detection Circuit
Control Circuit
INTAD INTP3
Conversion Result Register (ADCR)
Internal
µPD78056F, 78058F
Converter converter 8-bit resolution channels available. conversion method R-2R resistor ladder method.
Figure 5-9. Converter Block Diagram
AVREF1
ANOn
Selector DACSn Write AVSS INTTMX
Conversion Value Register (DACSn)
DAMm Converter Mode Register
Internal
Serial Interfaces channels clocked serial interface incorporated. Serial interface channel Serial interface channel Serial interface channel Table 5-3. Types Functions Serial Interface
Function 3-wire serial mode 3-wire serial mode with automatic transmission/reception function (serial interface) mode 2-wire serial mode Asynchronous serial interface (UART) mode (MSB first) (MSB first) Serial Interface Channel (MSB/LSB first switchable) Serial Interface Channel (MSB/LSB first switchable) (MSB/LSB first switchable) Serial Interface Channel (MSB/LSB first switchable)
(Dedicated baud rate generator incorporated)
µPD78056F, 78058F
Figure 5-10. Serial Interface Channel Block Diagram
Internal
SI0/SB0/P25 Selector SO0/SB1/P26 Serial Shift Register (SIO0) Output Latch
Selector
Release/Command Acknowledge Detection Circuit
Busy/Acknowledge Output Circuit
SCK0/P27
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI0
fXX/2-fXX/28 Serial Clock Control Circuit Selector
Figure 5-11. Serial Interface Channel Block Diagram
Internal
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial Shift Register (SIO1)
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
XX/2-f XX/28 Serial Clock Control Circuit Selector
µPD78056F, 78058F
Figure 5-12. Serial Interface Channel Block Diagram
Internal
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RxD/SI2/P70 TxD/SO2/P71
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
Receive Control Circuit
INTSER INTSR/INTCSI2 Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX-fXX/210
Real-Time Output Port Functions Data previously real-time output buffer register transferred output latch hardware concurrently with timer interrupt request external interrupt request generation order output off-chip. This real-time output function. Pins output off-chip called real-time output ports. using real-time output port, signal which jitter output. This most applicable control stepping motors, etc. Figure 5-13. Real-Time Output Port Block Diagram
Internal
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Real-Time Output Buffer Register Buffer Register Higher Bits Higher Bits (RTBH) (RTBL) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
µPD78056F, 78058F
INTERRUPT FUNCTIONS TEST FUNCTIONS
Interrupt Functions There interrupt functions different kinds, shown below. Non-maskable Maskable Software Table 6-1. Interrupt Source List (1/2)
Note
Interrupt Type
Default Priority
Interrupt Source Name INTWDT Trigger Watchdog timer overflow (watchdog timer mode selected) Watchdog timer overflow (interval timer mode selected) input edge detection
Internal/ External Internal
Vector Table Address 0004H
Basic Configuration Type Note
Non-maskable
Maskable
INTWDT
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTSER INTSR
External
0006H 0008H 000AH 000CH 000EH 0010H 0012H
serial interface channel transfer serial interface channel transfer Generation serial interface channel UART receive error serial interface channel UART reception serial interface channel 3-wire transfer serial interface channel UART transmission
Internal
0014H 0016H 0018H 001AH
INTCSI2
INTST
001CH
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78056F, 78058F
Table 6-1. Interrupt Source List (2/2)
Note
Interrupt Type
Default Priority
Interrupt Source Name INTTM3 Trigger Reference time interval signal from watch timer Generation match signal 16-bit timer register capture/compare register (CR00) Generation match signal 16-bit timer register capture/compare register (CR01) Generation match signal 8-bit timer/event counter Generation match signal 8-bit timer/ event counter conversion converter instruction execution
Internal/ External Internal
Vector Table Address 001EH
Basic Configuration Type Note
Maskable
INTTM00
0020H
INTTM01
0022H
INTTM1
0024H
INTTM2
0026H
Software
INTAD
0028H 003EH
Notes default priority priority order when more maskable interrupt requests generated simultaneously. highest order lowest. Basic configuration types correspond Figure 6-1, respectively.
µPD78056F, 78058F
Figure 6-1. Interrupt Function Basic Configuration (1/2) Internal non-maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Internal maskable interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
External maskable interrupt (INTP0)
Internal
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
Interrupt Request
Sampling Clock
Edge Detection Circuit
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
µPD78056F, 78058F
Figure 6-1. Interrupt Function Basic Configuration (2/2)
External maskable interrupt (except INTP0)
Internal
External Interrupt Mode Register (INTM0, INTM1)
Interrupt Request
Edge Detection Circuit
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
Software interrupt
Internal
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
µPD78056F, 78058F
Test Functions There test functions shown Table 6-2. Table 6-2. Test Input Source List
Test Input Source Name INTWT INTPT4 Watch timer overflow Port falling edge detection Trigger Internal/External Internal External
Figure 6-2. Test Function Basic Configuration
Internal
Test Input
Standby Release Signal
Test input flag Test mask flag
µPD78056F, 78058F
EXTERNAL DEVICE EXPANSION FUNCTIONS
external device expansion functions connect external devices areas other than internal ROM, SFR. Ports used external device connection.
STANDBY FUNCTION
There following standby functions reduce system power consumption. HALT mode operating clock stopped. average consumption current reduced intermittent operation combination with normal operating mode. main system clock oscillation stopped. whole operation main system clock stopped, that system operates with ultra-low power consumption using only subsystem clock.
STOP mode
Figure 8-1. Stand-by Function
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
HALT Instruction
Subsystem Clock Operation Note HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply stopped, oscillation)
HALT Mode Note (Clock supply stopped, oscillation)
Note
power consumption reduced stopping main system clock. When operating subsystem clock, (MCC) processor clock control register (PCC) stop main system clock. STOP instruction cannot used. When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
Caution
Remark
RESET FUNCTION
There following reset methods. External reset input RESET Internal reset watchdog time runaway time detection
µPD78056F, 78058F
INSTRUCTION
8-bit instructions MOV, XCH, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand #byte
Byte]
Note
saddr
!addr16
[DE]
[HL]
$addr16
None
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
ADDC SUBC
RORC ROLC
ADDC SUBC
saddr ADDC SUBC !addr16
DBNZ
DBNZ
PUSH
[DE] [HL]
ROR4 ROL4
Byte]
MULU DIVUW
Note Except
µPD78056F, 78058F
16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand #word ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVW Note MOVW MOVW MOVW MOVW
Note MOVW XCHW
sfrp MOVW
saddrp MOVW
!addr16 MOVW
MOVW
None
sfrp saddrp !addr16
INCW, DECW PUSH,
Note Only when manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BTCLR
Second Operand First Operand A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
MOV1
$addr16 BTCLR BTCLR BTCLR BTCLR BTCLR
None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
MOV1 AND1 XOR1
SET1 CLR1 NOT1
Call instruction/branch instructions CALL, CALLF, CALLT, BNC, BNZ, BTCLR, DBNZ
Second Operand First Operand Basic instruction Compound instruction
!addr16 CALL
!addr11 CALLF
[addr5] CALLT
$addr16 BTCLR DBNZ
µPD78056F, 78058F
Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, HALT, STOP
µPD78056F, 78058F
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17,P20 P27, toP37, P47, P57, P67, P72, P120 P127, P130, P131, RESET Output voltage Analog input voltage High level output current P06, P30-P37, P56, P57, P67, P120 P127 total P17, P27, P47, P55, P72, P130, P131 total level output current Note Peak value Effective value total Peak value Effective value P56, P57, total Peak value Effective value P17, P27, P47, P72, P130, P131 total P06, P37, P67, P120 P127 total Operating ambient temperature Storage temperature Peak value Effective value Peak value Effective value Analog input N-ch Open-drain -0.3 -0.3 AVSS -0.3 REF0 Test Conditions Rating -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Unit
Tstg
+150
Note
effective value should calculated follows: [Effective value] [Peak value] duty Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Caution
Remark Unless specified otherwise, alternate-function characteristics same port characteristics.
µPD78056F, 78058F
Main System Clock Oscillation Circuit Characteristics 85°C,
Recommended Circuit
Resonator Ceramic resonator
Parameter
Oscillator frequency (fX) Note Oscillation stabilization time
Note
Test Conditions Oscillator voltage range After reaches oscillator voltage range MIN.
MIN.
TYP.
MAX.
Unit
Crystal resonator
Oscillator frequency (fX)
Note
Oscillation stabilization time
Note
External clock
input
frequency (fX) input
Note
µPD74HCU04
high/low level width
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reset STOP mode release.
Cautions
When using main system clock oscillator, wiring area enclosed with broken line above figures should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same VSS. ground wiring ground pattern which high current flows. fetch signal from oscillator.
When main system clock stopped system operated subsystem clock, subsystem clock should switched again main system clock after oscillation stabilization time secured program.
µPD78056F, 78058F
Subsystem Clock Oscillation Circuit Characteristics +85°C,
Resonator Crystal resonator
Recommended Circuit
Parameter Oscillator frequency (fXT) Note Oscillation stabilization time Note input frequency (fXT) Note input high-/low-level width (tXTH tXTL)
Test Conditions
MIN.
TYP.
MAX.
Unit
32.768
External clock
Notes Indicates only oscillation circuit characteristics. Refer Characteristics" instruction execution time. Time required stabilize oscillation after reaches oscillator voltage MIN.
Cautions When using subsystem clock oscillator, wiring area enclosed with broken line above figures should carried follows avoid adverse effect from wiring capacitance. Wiring should short possible. Wiring should cross other signal lines. Wiring should placed close varying high current. potential oscillator capacitor ground should same ground wiring ground pattern which high current flows. fetch signal from oscillator.
subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone malfunction noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD78056F, 78058F
Capacitance 25°C,
Parameter Input capacitance capacitance Symbol Measured pins returned Measured pins returned P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 Test Conditions MIN. TYP. MAX. Unit
Remark
characteristics alternate-function pins same those port pins unless otherwise specified.
µPD78056F, 78058F
Characteristics +85°C,
Parameter Input voltage, high
Symbol VIH1 VIH2
Test Conditions P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET (N-ch Open-drain) XT1/P07,
MIN.
TYP.
MAX.
Unit
VIH3 VIH4 VIH5
VDD-0.5
Input voltage,
VIL1 VIL2
P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET
VIL3
VIL4 VIL5
XT1/P07,
Output voltage, high Output voltage,
-1mA -100
VDD-1.0 VDD-0.5
VOL1
P57,
P06, P17, P27, P37, P47, P67, P72, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 N-ch open-drain pull-up time(R
VOL3 Input leakage current, high LIH1
P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 RESET XT1/P07,
LIH2 LIH3
Remark
characteristics alternate-function pins port same unless specified otherwise.
µPD78056F, 78058F
Characteristics
Parameter Input leakage current, Symbol LIL1 Test Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, VOUT VOUT P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
LIL2 LIL3 Output leakage current, high Output leakage current, Mask option pull-up resistor Software pullup resistor
Note
Note
When pull-up resistor included (specified mask option), -200 (MAX.) lowlevel input leakage current flows only clock interval wait) when read instruction port (PM6) port mode register (PM6) executed. times other than this interval, (MAX.) current flows. characteristics alternate-function pins port pins same unless specified otherwise.
Remark
µPD78056F, 78058F
Characteristics +85°C,
Parameter Power supply current Note Symbol
IDD1
Test Conditions 5.0-MHz crystal oscillation Note operating mode Note (fXX MHz) Note 5.0-MHz crystal oscillation operating mode (fXX MHz) Note Note Note
MIN.
TYP. 0.65 0.05
MAX. 19.5 1.95
Unit
5.0-MHz crystal oscillation HALT mode (fXX MHz) Note 5.0-MHz crystal oscillation HALT mode (fXX MHz) Note
32.768-kHz crystal oscillation operating mode Note 32.768-kHz crystal oscillation HALT mode Note STOP mode When feedback resistor used
STOP mode When feedback resistor used
Notes Flows through AVDD pins. Does include current which flows through converter, converter, on-chip pull-up resistor. fx/2 operation (when oscillation mode selection register (OSMS) 00H) operation (when OSMS 01H) When main system clock stopped High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H) Remarks Main system clock frequency fX/2) Main system clock oscillator frequency
µPD78056F, 78058F
CHARACTERISTICS Basic Operation +85°C,
Parameter Cycle time (Min. instruction execution time) Operating subsystem clock TI00 input high-/ low-level width TI01 input high-/ low-level width TI1, input frequency TI1, input high-/low-level width Interrupt request input high-/low -level width RESET low-level width tRSL tTIH1, TIL1 tTIH00, TIL00 Symbol Test Conditions Operating main fX/2 system clock
Note
MIN. 2/fsam+0.1Note 2/fsam+0.2Note
TYP.
MAX.
Unit
Note
tTIH01, TIL01
fTI1
tINTH, INTL
INTP0 INTP1 INTP6,
2/fsam+0.1Note 2/fsam+0.2Note
Notes When oscillation mode selection register When oscillation mode selection register combination with bits (SCS0) (SCS1) sampling clock select register (SCS), selection fsam possible between fXX/2N, /32, fXX/64 /128 (when Remarks fXX: Main system clock frequency fX/2) Main system clock oscillation frequency
µPD78056F, 78058F
fX/2 main system clock operation)
main system clock operation)
Cycle Time Operation Guaranteed Range Cycle Time
Operation Guaranteed Range
Supply Voltage
Supply Voltage
µPD78056F, 78058F
Read/Write Operation When PCC2 PCC0 000B 85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol ASTH ADD1 ADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT WRWT tWTL tWDS tWDH ASTRD ASTWR RDAST (1.15+2n)t (2.85+2n)t CY-100 (2.85+2n)t CY-60 0.85t 0.85tCY 1.15tCY (2+2n)t CY-60 (2.85+2n)t CY-60 0.85tCY-50 2tCY-60 2tCY-60 (2+2n)tCY Test Conditions MIN. 0.85t 0.85t (2.85+2n)t CY-80 (4+2n)t CY-100 (2+2n)t CY-100 (2.85+2n)t CY-100 MAX. Unit
tRDADH
0.85t
1.15tCY
tRDWD tRDWD
tWRADH
0.85tCY 1.15t 1.15t 1.15tCY 3.15tCY 3.15t
WTRD WTWR
Remarks
MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) TCY/4 indicates number waits.
µPD78056F, 78058F
Except when PCC2 PCC0 000B 85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol ASTH ADD1 ADD2 Data input time from RDD1 RDD2 Read data hold time low-level width tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTB delay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tWRWT tWTL tWDH tWRL tASTRD ASTWR tRDAST tRDADH RDWD WRWD tWRADH tWTRD tWTWR (1+2n)t (2.4+2n)tCY-60 (2.4+2n)tCY-20 0.4tCY 1.4tCY 0.4t 0.6t 0.6t 2.6tCY 2.6t (1.4+2n)tCY-20 (2.4+2n)tCY-20 tCY-100 2tCY-100 2tCY-100 (2+2n)t Test Conditions MIN. 0.4t (3+2n)tCY-160 (4+2n)tCY-200 (1.4+2n)t CY-70 (2.4+2n)t CY-70 MAX. Unit
Remarks
MCS: Oscillation mode selection register (OSMS) PCC2 PCC0: Processor clock control register (PCC) TCY/4 indicates number waits.
µPD78056F, 78058F
Serial Interface +85°C, Serial interface channel 3-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time SCK0 high-/low-level width setup time SCK0) hold time (from SCK0) output delay time from SCK0 Symbol tKCY1 Test Conditions MIN. 1600 KH1, tKL1 KCY1/2-50 KCY1/2-100 SIK1 KSI1 TYP. MAX. Unit
tKSO1
Note
Note
load capacitance SCK0 output lines.
(ii) 3-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 SCK0 high-/low-level width setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time KH2, tKL2 SIK2 TYP. MAX. Unit
KSI2
KSO2
Note
When using external device expansion function When using external device expansion function
1000
Note
load capacitance output line.
µPD78056F, 78058F
(iii) mode (SCK0. Internal clock output)
Parameter SCK0 cycle time Symbol KCY3 Test Conditions MIN. 3200 SCK0 high-/low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width
tSBH
Note
TYP.
MAX.
Unit
KH3, SIK3
KCY3/2-50 tKCY3/2-150
KSI3
KCY3/2
KSO3
tKCY3 tKCY3
tKCY3
1000
tSBL
KCY3
Note
load resistacne load capacitance SCK0, SB0, output lines.
µPD78056F, 78058F
(iv) mode (SCK0. External clock input)
Parameter SCK0 cycle time Symbol KCY4 Test Conditions MIN. 3200 SCK0 high-/low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SB0, from SCK0 SCK0 from SB0, SB0, high-level width SB0, low-level width SCK0 rise, fall time SIK4 1600 KSI4 tKCY4/2 TYP. MAX. Unit
KSO4
Note
KCY4 KCY4
tKCY4
1000
tKCY4
When using external device expansion fanction When using external device expansion function
1000
Note
load resistance load capacitance output lines.
µPD78056F, 78058F
2-wire serial mode (SCK0. Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol KCY5
Note
Test Conditions
MIN. 1600 KCY5/2-160
TYP.
MAX.
Unit
tKCY5/2-50 tKCY5/2-100
SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0
SIK5
KSI5
KSO5
Note
load resistance load capacitance SCK0, SB0, output lines.
(vi) 2-wire serial mode (SCK0. External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time Symbol KCY6 SIK6 KSI6 KSO6 Test Conditions MIN. 1600 KCY6/2 TYP. MAX. Unit
Note
When using external device expansion function When using external device expansion function
1000
Note
load resistance load capacitance output lines.
µPD78056F, 78058F
Serial interface channel 3-wire serial mode (SCK1.Internal clock output)
Parameter SCK1 cycle time Symbol KCY7 Test Conditions MIN. 1600 SCK1 high-/low-level width KH7, tSIK7 tKCY7/2-50 tKCY7/2-100 hold time (from SCK1) output delay time from SCK1 tKSI7 tKSO7 Note TYP. MAX. Unit
setup time SCK1)
Note
load capacitance SCK1 output lines.
(ii) 3-wire serial mode (SCK1.External clock input)
Parameter SCK1 cycle time Symbol KCY8 Test Conditions MIN. 1600 SCK1 high-/low-level width tKH8, tKL8 tSIK8 tKSI8 tKSO8
Note
TYP.
MAX.
Unit
setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time
When using external device expansion function When using external device expansion function
1000
Note
load capacitance output line.
µPD78056F, 78058F
(iii) 3-wire serial mode with automatic transmit/receive function (SCK1. Internal clock output)
Parameter SCK1 cycle time Symbol KCY9 Test Conditions MIN. 1600 SCK1 high-/low-level width SIK9 tKCY9/2-50 tKCY9/2-100 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width Busy signal setup time busy signal detection timing) Busy signal hold time busy signal detection timing) SCK1 from busy inactive KSI9 KSO9
Note
TYP.
MAX.
Unit
setup time SCK1)
tKCY9/2-100 KCY9-30 KCY9/2+100 KCY9+30
2tKCY9
tSPS
Note
load capacitance SCK1 output lines.
(iv) 3-wire serial mode with automatic transmit/receive function (SCK1. External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. 1600 SCK1 high-/low-level width KH10, KL10 tSIK10 tKSI10 tKSO10 tR10, tF10
Note
TYP.
MAX.
Unit
setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time
When using external device expansion function When using external device expansion function
1000
Note
load capacitance output line.
µPD78056F, 78058F
Serial interface channel 3-wire serial mode (SCK2.Internal clock output)
Parameter SCK2 cycle time Symbol KCY11 Test Conditions MIN. 1600 SCK2 high-/low-level width KH11, KL11 SIK11 tKCY11 /2-50 tKCY11/2-100 hold time SCK2) output delay time from SCK2 KSI11 KSO11 Note TYP. MAX. Unit
setup time SCK2)
Note
load capacitance SCK2 output lines.
(ii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 Unit
(iii) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY12 Test Conditions MIN. 1600 ASCK high-/low-level width tKH12 tKL12 39063 19531 ASCK rise, fall time R12, when using external device expansion function 1000 TYP. MAX. Unit
Transfer rate
µPD78056F, 78058F
Timing Test Point (Excluding Input)
Test Points
Clock Timing
1/fX
-0.5
Input
1/fXT
tXTL Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL00, tTIL01 tTIH00, tTIH01
TI00, TI01
1/fTI tTIL1 tTIH1
TI1,
µPD78056F, 78058F
Read/Write Operation External Fetch Wait)
Lower 8-Bit Address tADS tASTH ASTB
Higher 8-Bit Address tADD1 Hi-z Instruction Code tRDD1 tRDADH tRDAST
tADH
tASTRD tRDL1 tRDH
External Fetch (Wait Insertion)
Lower 8-Bit Address tADS tASTH ASTB
Higher 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Instruction Code tRDADH
tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
µPD78056F, 78058F
External Data Access Wait)
Lower 8-Bit Address tADS tADH tASTH ASTB
Higher 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWRWD tASTWR tWRL tWRADH tWDS tWDH
External Data Access (Wait Insertion)
Lower 8-Bit Address tADS tADH tASTH ASTB
Higher 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Hi-z Write Data Hi-z
tASTRD tRDL2 tRDWD tWRWD tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
µPD78056F, 78058F
Serial Transfer Timing 3-wire Serial Mode
tKCYm tKLm SCK0 SCK2 tSIKm tKSIm tKHm
tKSOm
Input Data
Output Data
Mode (Bus Release Signal Transfer)
tKCY3,4 tKL3,4 SCK0 tKSB tSBL tSBH tSBK tSIK3,4 tKSI3, tKH3,4
SB0, tKSO3,4
Mode (Command Signal Transfer)
tKL3,4
tKCY3,4 tKH3,4
SCK0 tKSB tSBK tSIK3,4 tKSI3,4
SB0, tKSO3,4
µPD78056F, 78058F
2-wire Serial Mode
tKCY5,6 tKL5,6 SCK0 tSIK5,6 tKSO5,6 SB0, tKSI5,6 tKH5,6
3-wire Serial Mode with Automatic Transmit/Receive Function
tSIK9,10
tKSI9,10 tKH9,10
tKSO9,10 SCK1
tR10
tF10
tKL9,10 tKCY9,10
tSBD
tSBW
3-wire Serial Mode with Automatic Transmit/Receive Function (Busy Processing)
SCK1
Note
Note tBYS
10+n Note tBYH tSPS
BUSY (Active high)
Note
signal actually driven here; shown such indicate timing.
UART Mode (External Clock Input)
KCY12 KL12 tR12 KH12 tF12
ASCK
µPD78056F, 78058F
CONVERTER CHARACTERISTICS +85°C, AVDD AVSS
Parameter Resolution Overall error Note Conversion time Sampling time Analog input voltage Reference voltage Resistance between REF0 AVSS CONV SAMP VIAN AVREF0 RAIREF0 AVREF0 AVDD 19.1 12/f AVSS
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
AVREF0 AVDD
Note Caution
Overroll error excluding quantization error (±1/2 LSB). indicated ratio full-scale value. pins which also function port pins (see Port Pins), perform following operations during conversion. these operations performed, total error ratings cannot kept (except segment output alternate-function pin). Rewrite output latch while used port pin. Change output level used output pin, even used port pin. fXX: Main system clock frequency Main system clock oscillation frequency
Remarks
CONVERTER CHARACTERISTICS +85°C, AVSS
Parameter Resolution Overall error
Note Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Note Settling time
Note
AVREF1 AVREF1
C=30pF Output resistance Analog reference voltage AVREF1 Note
Resistance between AVREF1 AVSS RAIREF1
DACS0, DACS1
Note
Notes
load resistance load capacitance converter output pins. Value converter channel DACS0, DACS1: conversion value setting register
Remark
µPD78056F, 78058F
Data Memory STOP Mode Supply Voltage Data Retention Characteristics
Parameter Data retention power supply voltage Data retention power supply current Release signal time Oscillation stabilization wait time Symbol VDDDR Test Conditions MIN. TYP. MAX. Unit
DDDR
VDDDR Subsystem clock stop feed-back resistor disconnected Release RESET Release interrupt request
SREL WAIT
217/fx Note
Note
combination with bits (OSTS0 OSTS2) oscillation stabilization time select register, selection 212/fXX 214/fXX 217/fXX possible. Main system clock frequency fX/2) Main system clock oscillation frequency
Remark
Data Retention Timing (STOP Mode Release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release Interrupt Request Signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78056F, 78058F
Interrupt Request Input Timing
tINTL INTP0 INTP6
tINTH
RESET Input Timing
tRSL
RESET
µPD78056F, 78058F
PACKAGE DRAWINGS
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-4
Remark Dimensions materials product same those mass-production products.
µPD78056F, 78058F
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
µPD78056F, 78058F
PLASTIC TQFP (FINE PITCH)
detail lead
NOTE Each lead centerline located within 0.10 (0.004 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.145 +0.055 -0.045 0.10 1.05 0.05±0.05 5°±5° 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.009±0.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006±0.002 0.004 0.041 0.002±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-4
Remark Dimensions materials product same those mass-production products.
µPD78056F, 78058F
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under conditions recommended table below. detail recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Table 13-1. Surface Mounting Type Soldering Conditions (1/2) 80-pin plastic resin thickness 80-pin plastic resin thickness
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Three times max.
Recommended Condition Symbol IR35-00-3
Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Three times max.
VP15-00-3
Wave soldering
Solder bath temperature 260°C max., Duration sec. max., Number times: once, Preheating temperature 120°C max. (package surface temperature) temperature: 300°C max. Duration: sec. max. (per row)
WS60-00-1
Partial heating
Caution
more than soldering method should avoided (except case partial heating).
80-pin plastic resin thickness 80-pin plastic resin thickness
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Twice max.
Recommended Condition Symbol IR35-00-2
Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Twice max. Solder bath temperature 260°C max., Duration sec. max., Number times: once, Preheating temperature 120°C max. (package surface temperature) temperature: 300°C max. Duration: sec. max. (per row)
VP15-00-2
Wave soldering
WS60-00-1
Partial heating
Caution
more than soldering method should avoided (except case partial heating).
µPD78056F, 78058F
Table 13-1. Surface Mounting Type Soldering Conditions (2/2) 80-pin plastic TQFP (fine pitch)
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Duration: sec. max. 210°C above), Number times: Three times max., Time limit: days Note (thereafter hours 125°C prebaking required) Package peak temperature: 215°C, Duration: sec. max. 200°C above), Number times: Three times max., Time limit: days Note (thereafter hours 125°C prebaking required) temperature: 300°C max. Duration: sec. max. (per row)
Recommended Condition Symbol IR35-107-3
VP15-107-3
Partial heating
Note
storage period after dry-pack decompression storage conditions max. 25°C,
Caution more than soldering method should avoided (except case partial heating).
µPD78056F, 78058F
APPENDIX DEVELOPMENT TOOLS
following development tools available system development using µPD78058F Subseries. Language Processing Software
RA78K/0 Notes CC78K/0 Notes DF78054
Notes
Assembler package common 78K/0 Series compiler package common 78K/0 Series Device file common µPD78054 Subseries compiler library source file common 78K/0 Series
CC78K/0-L Notes
PROM Writing Tools
PG-1500 PA-78P054GC PG-1500 controller Notes PROM programmer Programmer adapters connected PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM
Note
In-circuit emulator common 78K/0 Series 78K/0 Series common in-circuit emulator (for integrated debugger) Break board common 78K/0 Series Emulation board common PD78064 Subseries Emulation board common PD780308 Subseries Interface adapter cable when used host machine (for IE-78000-R-A) Interface adapter when PC-9800 series (except notebook type) used host machine. Interface adapter cable when notebook type PC-9800 series used host machine. Interface adapter when PC/ATand compatibles used host machine. Emulation probe common PD78234 Subseries Emulation probe common PD78054 Subseries Socket mounted target system board manufactured 80-pin plastic (GC-3B9, GC-8BT type)
IE-780308-R-EM IE-78000-R-SV3 IE-70000-98-IF-B IE-70000-98N-IF IE-70000-PC-IF-B EP-78230GC-R EP-78054GK-R EV-9200GC-80
TGK-080SDW
Adapter mounted target system board manufactured 80-pin plastic TQFP (GK-BE9 type) Product made TOKYO ELETECH Corporation ((03) 5295-1661). Contact dealer regarding purchase this product.
SM78K0 ID78K0
Notes
System simulator common 78K/0 Series Integrated debugger IE-78000-R-A IE-78000-R screen debugger
Notes
SD78K/0 Notes DF78054
Notes
µPD78054 Subseries device file
µPD78056F, 78058F
Real-Time
RX78K/0 Notes MX78K0 Notes Real-time 78K/0 Series Real-time 78K/0 Series
Fuzzy Inference Development Support System
FE9000 Note FE9200 Note FT9080 Note FT9085 Note FI78K0 Notes FD78K0 Notes Fuzzy knowledge data creation tool Translator Fuzzy inference module Fussy inference debugger
Notes
PC-9800 series (MS-DOS) based PC/AT compatibles DOS/IBM DOS/MS-DOS) based HP9000 series 300(HP-UX based HP9000 series 700(HP-UX) based, SPARCstation (SunOS) based, EWS4800 series (EWS-UX/ based PC-9800 series (MS-DOS Windows) based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OS) based Maintenance product
Remarks third party development tools, 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF78054.
µPD78056F, 78058F
APPENDIX RELATED DOCUMENTS
Device Related Documents
Document (English) U12068E This document U11796E U12326E Document (Japanese) U12068J U11795J U11796J U12326J U10904J U10903J
Document Name
PD78058F, 78058FY Subseries User's Manual PD78056F, 78058F Data Sheet PD78P058F Data Sheet
78K/0 Series User's Manual-Instruction 78K/0 Series Instruction 78K/0 Series Instruction Table
Caution
above related documents subject change without notice. sure read latest documents before designing.
µPD78056F, 78058F
Development Tool Related Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series Compiler Operation Language CC78K0 Compiler CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) based PG-1500 Controller Series DOS) based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM IE-780308-R-EM EP-78230 EP-78054GK-R SM78K0 System Simulator, Windows based SM78K Series System Simulator Reference External parts user open interface specification ID78K0 Integrated Debugger, based ID78K0 Integrated Debugger, based ID78K0 Integrated Debugger, Windows based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) based SD78K/0 Screen Debugger PC/AT DOS) based Reference Reference Guide Introduction Reference Introduction Reference U11539E U11649E U10539E U11279E U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J Operation Language Programming know-how Document (English) EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E EEU-1280 EEU-1284 U11517E U11518E EEA-1208 EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 EEU-1443 U11362E EEU-1515 EEU-1468 U10181E U10092E Document (Japanese) EEU-809 EEU-815 U12323J U11802J U11801J U11789J EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 EEU-905 U11362J EEU-985 EEU-932 U10181J U10092J
Caution
above related documents subject change without notice. sure read latest documents before designing.
µPD78056F, 78058F
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real-time 78K/0 Series MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-1458 EEU-921 EEU-1441 EEU-858 Fundamental Installation Fundamental Document (English) U11537E U11536E U12257E EEU-1438 EEU-1444 Document (Japanese) U11537J U11536J U12257J EEU-829 EEU-862
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Microcomputer Product Series Guide Document (English) C10943X C10535E C11531E C10983E MEI-1202 C10535J C11531J C10983J MEM-539 C11893J U11416J Document (Japanese)
Caution above related documents subject change without notice. sure read latest documents before designing.
µPD78056F, 78058F
[MEMO]
µPD78056F, 78058F
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78056F, 78058F
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78056F, 78058F
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
trademark Corporation. IEBus trademark Corporation. MS-DOS Windows either registered trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 series 300, HP9000 series, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NES-OS trademarks Sony Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.

µPD78056F,78058F 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTI

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