µPD784054 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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µPD784054 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD784054
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD784054 based µPD784046 subseries with real- time output function units timers/ counters deleted standby function invalid mode provided. µPD784054 provided with many peripheral hardware functions such ROM, RAM, port, 10-bit resolution converter, timer, serial interface, interrupt functions, addition high-speed, high-performance CPU. Moreover, flash memory model, µPD78F4046, that operate same supply voltage mask model, many development tools under development. functions described detail following User's Manuals. sure read these manuals when designing your system.
µPD784054 User's Manual Hardware
U11719E
78K/IV Series User's Manual Instruction U10905E
FEATURES
78K/IV series Minimum instruction execution time port Timer converter Watchdog timer Supply voltage (with 16-MHz internal clock) lines 16-bit timer units 10-bit resolution channels channel
Serial interface UART/IOE (3-wire serial I/O) channels Standby function HALT/STOP/IDLE/standby function invalid mode
APPLICATION FIELDS
Office machines such PPCs printers systems such robots automatic machine tools
ORDERING INFORMATION
Part Number Package 80-pin plastic Internal (bytes) Internal (bytes) 1024
Remark indicates code suffix.
information this document subject change without notice. Document U11154EJ1V0DS00 (1st edition) Date Published January 1998 Printed Japan
mark
shows major revised points.
1996
µPD784054
Product Development 78K/IV Series
Under mass production Under development
Standard models
multimaster
PD784038Y µPD784038
Improved internal memory capacity, compatible with µPD784026 multimaster
PD784225Y µPD784225
pins, correction added multimaster
µPD784026
A/D, 16-bit timer, improved power management
µPD784216Y µPD784216
pins, I/O, improved internal memory capacity
µPD784218Y µPD784218
Improved internal memory capacity, correction added
µPD784054
µPD784046
Internal 10-bit ASSP models
µPD784955
converter control
µPD784908
Internal IEBuscontroller multimaster
µPD784943
CD-ROM
µPD784928Y µPD784928
Improved functions µPD784915
µPD784915
Software servo control, internal analog circuit VCR, improved timer
µPD784054
FUNCTION LIST
Item Number basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space port Total Input bits registers banks, bits registers banks (memory mapping) (with internal 16-MHz clock) bytes 1024 bytes bytes with program/data combined pins pins pins Function
Pins with Pins with pins ancillary pull-up functions Note resistors Timer Timer bits) Timer bits) Timer bits) converter Serial interface Watchdog timer Interrupt Timer register capture/compare register Timer register compare register Timer register compare register Pulse output possible Toggle output Set/reset output Pulse output possible Toggle output Set/reset output
10-bit resolution channels UART/IOE (3-wire serial I/O): channels (with baud rate generator) channel
Hardware source (internal: external: (internal/external: Software source Non-maskable Maskable instruction, BRKCS instruction, operand error Internal: external: Internal: external: (internal/external: levels programmable priorities processing formats: vectored interrupt/macro service/context switching
sizing Standby Supply voltage Package
8-bit/16-bit external data width selectable HALT/STOP/IDLE/standby function invalid mode 80-pin plastic
Note
pins with ancillary functions included pins.
µPD784054
CONTENTS
DIFFERENCES BETWEEN µPD784054 µPD784046 SUBSERIES CONFIGURATION (Top View) SYSTEM CONFIGURATION EXAMPLE (PPC) BLOCK DIAGRAM FUNCTIONS
Port Pins Pins Other Than Port Pins Circuits Pins Processing Unused Pins
ARCHITECTURE
Memory Space Registers 6.2.1 6.2.2 6.2.3 General-purpose registers Control registers Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
Ports Clock Generation Circuit Timer Converter Serial Interface 7.5.1 Asynchronous serial interface/3-wire serial (UART/IOE) Edge Detection Circuit Watchdog Timer
INTERRUPT FUNCTION.36
Interrupt Source Vectored Interrupt Context Switching Macro Service
LOCAL INTERFACE
Memory Expansion Memory Space Programmable Wait Sizing Function
µPD784054
STANDBY FUNCTION RESET FUNCTION INSTRUCTION ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD784054
DIFFERENCES BETWEEN µPD784054 µPD784046 SUBSERIES
Table shows differences between PD784054 PD784046 subseries. Table 1-1. Differences between µPD784054 µPD784046 Subseries
Part Number Item Internal Internal Port Real-time output port Timer/counter Standby function bytes (mask ROM) 1024 bytes P10-P12 None 16-bit timer units HALT/STOP/IDLE/ standby function invalid mode Provided MODE P10-P13 bits 16-bit timer/counter units 16-bit timer units HALT/STOP/IDLE mode
µPD784054 µPD784044
PD784046 Subseries PD784046
bytes (mask ROM) 2048 bytes
PD78F4046
bytes (flash memory)
MODE1 Function Interrupt hardware source
provided MODE/V
µPD784054
CONFIGURATION (Top View)
80-pin plastic
P24/INTP3/TO03 P23/INTP2/TO02
P27/INTP6
P26/INTP5
P25/INTP4
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
CLKOUT
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 AVREF AVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P22/INTP1/TO01 P21/INTP0/TO00 MODE P20/NMI MODE1 P37/ASCK2/SCK2 P36/TxD2/SO2 P35/RxD2/SI2 P34/ASCK/SCK1 P33/TxD/SO1
P30/TO10
P31/TO11
RESET
AVSS
Cautions Directly connect MODE VSS. Usually, directly connect MODE1 VSS.
P32/RxD/SI1
P52/AD10
P53/AD11
P54/AD12
P55/AD13
P56/AD14
P57/AD15
P60/A16
P61/A17
P62/A18
P63/A19
P93/ASTB
P90/RD
P92/HWR
P50/AD8
P51/AD9
P91/LWR
P94/WAIT
µPD784054
A16-A19 AD0-AD15 ANI0-ANI15 ASCK, ASCK2 ASTB CLKOUT INTP0-INTP6 MODE, MODE1 P00-P03 P10-P12 P20-P27 P30-P37 Address Address/Data Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Width Definition Clock High Address Write Strobe Interrupt from Peripherals Address Write Strobe Mode Non-maskable Interrupt Port0 Port1 Port2 Port3 P40-P47 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 RESET RxD, RxD2 SCK1,SCK2 SI1, SO1, TxD, TxD2 WAIT Port4 Port5 Port6 Port7 Port8 Port9 Read Strobe Reset Receive Data Serial Clock Serial Input Serial Output Transmit Data Power Supply Ground Wait Crystal
TO00-TO03, TO10, TO11 Timer Output
µPD784054
SYSTEM CONFIGURATION EXAMPLE (PPC)
PD784054
SCK2 Paper detection Paper feed detection Paper ejection detection Manuscript table (scanner) position detection Operation panel
Serial communication
Paper feed/transportation detection
INTP0
P10-P12
High-voltage control circuit
Drum, toner, charge transcription
Fusion unit heater temperature ANI0
Fusion unit heater control circuit
Fusion unit roller
Lamp light quantity ANI1 TO10 P00-P03 Copy density adjuster lever ANI2
Lamp regulator
Manuscript illumination lamp, lamp elimination electric charge
(DC, stepping) Main motor
Driver ANI3 Reset circuit RESET Solenoid
Manuscript table (scanner) stop clutch Manuscript table (scanner) forward clutch Resist shutter clutch
Copy density correction lever
Manual paper feed clutch
Cassette paper feed clutch
µPD784054
BLOCK DIAGRAM
INTP0-INTP6
Programmable interrupt controller
INTP0-INTP3 TO00-TO03
Timer bits) Port Timer bits)
AD0-AD15 A16-A19 LWR, ASTB WAIT P00-P03
TO10, TO11
Port
P10-P12 P21-P27 P30-P37
Port Timer bits) 78K/IV core Port
ANI0-ANI15 AVDD AVSS AVREF INTP4 converter
Port
P40-P47
Port
P50-P57
Port Watchdog timer Port
P60-P63
P70-P77
RxD/SI1 TxD/SO1 ASCK/SCK1
Port UART/IOE1 Baud-rate generator Port
P80-P87
P90-P94 CLKOUT RESET MODE MODE1
RxD2/SI2 TxD2/SO2 ASCK2/SCK2
UART/IOE2 Baud-rate generator
System control
µPD784054
FUNCTIONS Port Pins (1/2)
Name P00-P03 Shared Function Port (P0): 4-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Port (P1): 3-bit port input/output mode bit-wise. Port (P2): 8-bit port Input only input/output mode bit-wise.
P10-P12
P40-P47
Input
INTP0/TO00 INTP1/TO01 INTP2/TO02 INTP3/TO03 INTP4 INTP5 INTP6
TO10 TO11 RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
Port (P3): 8-bit port input/output mode bit-wise.
AD0-AD7
Port (P4): 8-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Port (P5): 8-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Port (P6): 4-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software.
P50-P57
AD8-AD15
P60-P63
A16-A19
µPD784054
Port Pins (2/2)
Name P70-P77 P80-P87 Input Input Shared ANI0-ANI7 ANI8-ANI15 ASTB WAIT Port (P7): 8-bit input port Port (P8): 8-bit input port Port (P9): 5-bit port input/output mode bit-wise. Pins input mode connected pull-up resistors once software. Function
µPD784054
Pins Other Than Port Pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 TO00 TO01 TO02 TO03 TO10 TO11 RxD2 TxD2 ASCK ASCK2 SCK1 SCK2 AD0-AD7 AD8-AD15 Note Output Input Input Output Input Output Input Shared P21/TO00 P22/TO01 P23/TO02 P24/TO03 P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P32/SI1 P35/SI2 P33/SO1 P36/SO2 P34/SCK1 P37/SCK2 P32/RxD P35/RxD2 P33/TxD P36/TxD2 P34/ASCK P37/ASCK2 P40-P47 P50-P57 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock input/output (3-wire serial I/O1) Serial clock input/output (3-wire serial I/O2) Lower multiplexed address/data when external memory connected When 8-bit specified Higher address when external memory connected When external 16-bit specified Higher multiplexed address/data when external memory connected Higher address when external memory connected Read strobe external memory When external 8-bit specified Write strobe external memory When external 16-bit specified Write strobe external memory located lower position Write strobe external memory located higher position when external 16-bit specified Timing signal output externally latch address information output from through AD15 pins access external memory Timer output Function Non-maskable interrupt request input External interrupt request input Capture trigger signal CC00 Capture trigger signal CC01 Capture trigger signal CC02 Capture trigger signal CC03 Conversion start trigger input converter
A16-A19 Note
Output Output Output
P60-P63
ASTB Output
Note
number pins used address pins differs depending external address space (refer LOCAL INTERFACE).
µPD784054
Pins Other Than Port Pins (2/2)
Name WAIT MODE MODE1 CLKOUT RESET ANI0-ANI7 ANI8-ANI15 Input Input Input Input Output Input Input Input Shared P70-P77 P80-P87 Reference voltage converter Positive power supply converter converter Positive power supply Chip reset Analog voltage input converter Inserts wait. Sets width. Directly connect this (this specifies test mode IC). Specifies standby function invalid mode. Usually, connect this VSS. Clock output. Outputs level during IDLE mode STOP mode. Otherwise, always outputs (oscillation frequency). Connect crystal system clock oscillation (clock also input X1). Function
µPD784054
Circuits Pins Processing Unused Pins
Table shows circuit type each recommended processing unused pins. circuit type, refer Figure 5-1. Table 5-1. Circuit Type Each Recommended Processing Unused Pins
Name P00-P03 P10-P12 P20/NMI P21/INTP0/TO00 P22/INTP1/TO01 P23/INTP2/TO02 P24/INTP3/TO03 P25/INTP4 P26/INTP5 P27/INTP6 P30/TO10 P31/TO11 P32/RxD/SI1 P33/TxD/SO1 P34/ASCK/SCK1 P35/RxD2/SI2 P36/TxD2/SO2 P37/ASCK2/SCK2 P40/AD0-P47/AD7 P50/AD8-P57/AD15 P60/A16-P63/A19 P70/ANI0-P77/ANI7 P80/ANI8-P87/ANI15 P90/RD P91/LWR P92/HWR P93/ASTB P94/WAIT MODE,MODE1 RESET CLKOUT Connect Output Leave unconnected. Connect Input Directly connect Input: Individually connect resistor. Output: Leave unconnected. Input Connect Circuit Type Input Recommended Connection Unused Pins Input: Individually connect resistor. Output: Leave unconnected. Connect Input: Individually connect resistor. Output: Leave unconnected.
Remark circuit type numbers serial series always with some models (because some models provided with particular circuits).
µPD784054
Figure 5-1. Circuits Pins
Type Type
P-ch
Pullup Enable Data
P-ch P-ch IN/OUT
N-ch
Output disable Input enable
N-ch
Type
Type
Data Output disable N-ch P-ch IN/OUT
Schmitt trigger input with hysteresis characteristics Type Type
P-ch N-ch
P-ch N-ch
Comparator
VREF (Threshold voltage)
Input enable
Type Data P-ch IN/OUT Output disable N-ch
Input enable
µPD784054
ARCHITECTURE Memory Space
1M-byte memory space accessed. mapping internal data area (special function registers internal RAM) selected using LOCATION instruction. LOCATION instruction must always executed after reset signal been deasserted, must used more than once. When LOCATION instruction executed Internal memory internal data area internal area mapped follows: Internal data area 0FB00H through 0FFFFH Internal area 00000H through 07FFFH External memory external memory accessed external memory expansion mode. When LOCATION instruction executed Internal memory internal data area internal area mapped follows: Internal data area 0FB00H through FFFFFH Internal area 00000H through 07FFFH External memory external memory accessed external memory expansion mode.
µPD784054
Figure 6-1. Memory
When LOCATION instruction executed
External memory Note (960K bytes) Main Peripheral Program/data area (512 bytes)
Note
When LOCATION instruction executed
Special function registers (SFRS) Note (256 bytes)
General-purpose registers (128 bytes)
Internal bytes) Cannot used (1280 bytes)
Special function registers (SFRs) Note (256 bytes) Internal memory bytes) Cannot used (1280 bytes)
Macro service control word area bytes) Data area (512 bytes)
External memoryNote (1013248 bytes)
Program/data area (32K bytes) CALLF entry area bytes)
Note
External memory Note (30208 bytes)
Internal (32K bytes)
CALLT table area bytes) Vector table area bytes)
Internal (32K bytes)
Notes Accessed external memory expansion mode. Base area entry area reset interrupt. internal reset.
µPD784054
Registers
6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers provided. 8-bit general-purpose registers used pairs 16-bit general-purpose register. 16-bit registers, four used with 8-bit register address expansion 24-bit address specification registers. Eight banks register sets available which selected software context switching function. general-purpose registers except registers address expansion mapped internal RAM. Figure 6-2. General-Purpose Register Format
A(R1) AX(RP0) B(R3) BC(RP1) VVP(RG4) UUP(RG5) D(R13) TDE(RG6) H(R15) WHL(RG7) HL(RP7) DE(RP6) UP(RP5) VP(RP4)
X(R0) C(R2)
E(R12)
L(R14)
banks
absolute name
Caution
RP2, used registers, respectively, setting However, this function only when using 78K/III series program.
µPD784054
6.2.2 Control registers Program counter (PC) This 20-bit program counter. contents automatically updated program executed. Figure 6-3. Program Counter (PC) Format
Program status word (PSW) This register retains status contents automatically updated program executed. Figure 6-4. Program Status Word (PSW) Format
PSWH PSWL
RBS2
RBS1
RBS0
Note
Note
This flag provided that µPD784054 maintains compatibility with 78K/III series. sure clear this flag when using 78K/III series software.
Stack pointer (SP) This 24-bit pointer that holds first address stack. sure write higher bits this pointer. Figure 6-5. Stack Pointer (SP) Format
µPD784054
6.2.3 Special function registers (SFRs) special function registers registers which special functions assigned, include mode registers control registers internal peripheral hardware. These registers mapped 256-byte space addresses 0FF00H through 0FFFFHNote. Note When LOCATION instruction executed. FFF00H through FFFFFH when LOCATION instruction executed. Caution access address this area which allocated. address which allocated accessed mistake, µPD784054 deadlocked. deadlock status cleared only inputting reset signal. Table lists special function registers. meanings symbols this table follows: Symbol Symbol indicating SFR. These symbols reserved NEC's assembler (RA78K4). With compiler (CC78K4), they used variables using #pragma directive. Indicates whether corresponding read/written. Read/write Read only Write only
units manipulation Indicates units which corresponding manipulated. SFRs that manipulated 16-bit units described operand sfrp. Specify even addresses these SFRs when specifying address. SFRs that manipulated bit-wise described manipulation instructions. reset Indicates status each register when RESET signal input.
µPD784054
Table 6-1. Special Function Register List (1/4)
Address Note Special Function Register (SFR) Name Symbol units manipulation 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF08H 0FF09H 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF1EH 0FF1FH 0FF20H 0FF21H 0FF22H 0FF23H 0FF24H 0FF25H 0FF26H 0FF29H 0FF2FH 0FF30H 0FF31H Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port mode register Port read control register Timer unit mode register Timer mode control register Note PRDC TUM0 Compare register CM11 Compare register CM10 Undefined Timer register 0000H Capture/compare register CC03 Capture/compare register CC02 Capture/compare register CC01 Capture/compare register CC00 Undefined Port Port Port Port Port Port Port Port Port Port Timer register
Note
reset
bits
bits 0000H Undefined
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. only read. Bits through read/written. fixed hardware.
µPD784054
Table 6-1. Special Function Register List (2/4)
Address Note Special Function Register (SFR) Name Symbol units manipulation 0FF32H 0FF33H 0FF37H 0FF38H 0FF3AH 0FF3BH 0FF3CH 0FF3DH 0FF3EH 0FF3FH 0FF42H 0FF43H 0FF49H 0FF4EH 0FF4FH 0FF60H 0FF61H 0FF62H 0FF63H 0FF64H 0FF65H 0FF6EH 0FF70H 0FF71H 0FF71H 0FF72H 0FF73H 0FF73H 0FF74H 0FF75H 0FF75H 0FF76H 0FF77H 0FF77H 0FF78H 0FF79H 0FF79H conversion result register ADCR4H conversion result register conversion result register ADCR3H ADCR4 conversion result register conversion result register ADCR2H ADCR3 conversion result register conversion result register ADCR1H ADCR2 conversion result register conversion result register ADCR0H ADCR1 converter mode register conversion result register ADCR0 Undefined Compare register CM41 Compare register CM40 Undefined Timer output control register Timer output control register Timer mode control register Prescaler mode register Prescaler mode register Noise protection control register External interrupt mode register External interrupt mode register Interrupt valid edge flag register Interrupt valid edge flag register Port mode control register Port mode control register Port mode control register Pull-up resistor option register Pull-up resistor option register Timer register TOC0 TOC1 TMC4 PRM4 INTM0 INTM1 IEF1 IEF2 PMC2 Note PMC3 PMC9 PUOL PUOH bits bits 0000H Undefined reset
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. Bits through PMC2 fixed hardware.
µPD784054
Table 6-1. Special Function Register List (3/4)
Address Note Special Function Register (SFR) Name Symbol units manipulation 0FF7AH 0FF7BH 0FF7BH 0FF7CH 0FF7DH 0FF7DH 0FF7EH 0FF7FH 0FF7FH 0FF84H 0FF85H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH conversion result register Clocked serial interface mode register Clocked serial interface mode register Asynchronous serial interface mode register Asynchronous serial interface mode register ADCR7H CSIM1 CSIM2 ASIM ASIM2 FFFFH Undefined conversion result register conversion result register ADCR6H ADCR7 conversion result register conversion result register ADCR5H ADCR6 conversion result register ADCR5 bits bits Undefined reset
Asynchronous serial interface status register ASIS Asynchronous serial interface status register Serial receive buffer: UART0 Serial transmit shift register: UART0 Serial shift register: IOE1 ASIS2 SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 ISPR MK0L
0FF8DH
Serial receive buffer: UART2 Serial transmit shift register: UART2 Serial shift register: IOE2
0FF90H 0FF91H 0FFA8H 0FFAAH 0FFACH 0FFACH 0FFADH 0FFADH 0FFAEH 0FFAEH 0FFAFH 0FFAFH 0FFC0H 0FFC2H 0FFC4H 0FFC7H
Baud rate generator control register Baud rate generator control register In-service priority register Interrupt mode control register Interrupt mask register Interrupt mask register
Interrupt mask register Interrupt mask register Interrupt mask register
MK0H MK1L
FFFFH
Interrupt mask register Standby control registerNote register Note
MK1H STBC PWC1
Watchdog timer mode
Memory expansion mode register Programmable wait control register
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. These registers written only using dedicated instructions STBC, #byte WDM, #byte, cannot written other instructions.
µPD784054
Table 6-1. Special Function Register List (4/4)
Address Note Special Function Register (SFR) Name Symbol units manipulation 0FFC8H 0FFC9H 0FFCAH 0FFCBH 0FFCFH 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFF0H 0FFF1H 0FFF2H 0FFF3H Oscillation stabilization time specification register OSTS External area Interrupt control register (INTOV0) Interrupt control register (INTOV1) Interrupt control register (INTOV4) Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTP6) Interrupt control register (INTCM10) Interrupt control register (INTCM11) Interrupt control register (INTCM40) Interrupt control register (INTCM41) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF4H 0FFF5H 0FFF6H Interrupt control register (INTST) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF7H 0FFF8H Interrupt control register (INTST2) Interrupt control register (INTAD) OVIC0 OVIC1 OVIC4 PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 CMIC10 CMIC11 CMIC40 CMIC41 SERIC SRIC CSIIC1 STIC SERIC2 SRIC2 CSIIC2 STIC2 ADIC Undefined width specification register Note Programmable wait control register PWC2 bits bits AAAAH reset
Notes When LOCATION instruction executed. "F0000H" this value when LOCATION instruction executed. value this register differs reset depending setting pin. 0000H 00FFH
µPD784054
PERIPHERAL HARDWARE FUNCTIONS Ports
PD784054 ports shown Figure 7-1. These ports used various control operations. function each port shown Table 7-1. Ports through connected internal pull-up resistor software when they input mode. Figure 7-1. Port Configuration
Port Port
Port
Port
Port
P70-P77 Port
Port
P80-P87 Port
Port Port
µPD784054
Table 7-1. Port Function
Port Name Port Port Port Name P00-P03 P10-P12 P20-P27 input output mode bit-wise (however, input-only). Port Port Port Port Port Port Port P30-P37 P40-P47 P50-P57 P60-P63 P70-P77 P80-P87 P90-P94 input output mode bit-wise. pins input mode Input port input output mode bit-wise. pins input mode Function input output mode bit-wise. Specification Pull-Up Resistor Software pins input mode
Clock Generation Circuit
clock generation circuit generates controls internal system clock (CLK) supplied CPU. Figure shows configuration this circuit. Figure 7-2. Block Diagram Clock Generation Circuit
Clock generation circuit
Divider fCLK Internal system clock (CLK)
Remark crystal/ceramic oscillation frequency external clock frequency fCLK internal system clock frequency
µPD784054
Figure 7-3. Example Using Oscillation Circuit Crystal/ceramic oscillation
PD784054
External clock input EXTC OSTS EXTC OSTS
PD784054
PD784054
µPD74HC04, etc.
Leave unconnected
Caution
When using clock oscillation circuit, wire portion enclosed dotted line above figure follows avoid adverse effects wiring capacitance. Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity lines through which high alternating current flows. Always keep ground point capacitor oscillation circuit same potential VSS. ground capacitor ground pattern through which high current flows. extract signals from oscillation circuit.
µPD784054
Timer
µPD784054 three 16-bit timer units. Because total interrupt requests supported, timer units used 11-channel timers. Table 7-2. Timer Function
Name Item Operation mode Function Interval timer Timer output Toggle output Set/reset output Overflow interrupt Number interrupt requests Timer Timer Timer
µPD784054
Figure 7-4. Block Diagram Timer Timer
Timer register (TM0) INTP0 INTP0 Edge detection INTP1 INTP1 Edge detection INTP2 INTP2 Edge detection INTP3 INTP3 Edge detection
CoinciCapter/compare register dence
fCLK
Prescaler
INTOV0 INTCC00 Pulse INTCC01 output control TO00
(CC00)
Coinci-
Capter/compare register dence (CC01)
Coinci-
TO01 INTCC02 TO02 Pulse INTCC03 output control TO03
Capter/compare register dence (CC02)
Coinci-
Capter/compare register dence (CC03)
Prescaler: CLK/16, /32, fCLK Timer
Clear control Timer register (TM1)
Coinci-
fCLK
Prescaler
INTOV1 INTCM10 TO10 Pulse output control TO11 INTCM11
Compare register dence (CM10)
Coinci-
Compare register dence (CM11)
Prescaler: /16, fCLK /32, CLK/64, /128 Timer
Clear control Timer register (TM4)
Coinci-
fCLK
Prescaler
INTOV4
Compare register dence (CM40)
Coinci-
INTCM40
Compare register dence (CM41)
INTCM41
Prescaler: CLK/16, /32, fCLK
µPD784054
Converter
PD784054 analog-to-digital (A/D) converter with multiplexed analog input pins (ANI0 through ANI15). This converter successive approximation type. result conversion stored retained 10-bit conversion result registers (ADCR0 through ADCR7). Therefore, high-speed, high-accuracy conversion performed (conversion time: about MHz). conversion operation started following modes: Hardware start Conversion started trigger input (INTP4). Software start Conversion started setting converter mode register (ADM). converter operates following modes: Scan mode Select mode Sequentially selects more analog input pins obtain data converted from pins. Selects only analog input obtain successive conversion values.
above modes stopping conversion specified ADM. When result conversion transferred ADCRn interrupt request INTAD generated. using this interrupt request using macro service, converted value successively transferred memory. Figure 7-5. Block Diagram Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15
Input selector Sample hold circuit
Series resistor string AVREF Voltage comparator
Input selector Successive approximation register (SAR) Conversion trigger
selector
AVSS
INTP4
Edge detection circuit
Control circuit
INTAD
Trigger enable
converter mode register (ADM)
ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 Internal
conversion result register
µPD784054
Serial Interface
µPD784054 provided with independent serial interface channels. Asynchronous serial interface (UART)/3-wire serial (IOE) using these serial interface channels, communication with external device local communication within system performed same time (refer Figure 7-6). Figure 7-6. Example Serial Interface
µPD784054 (master)
PD4711A
(UART) RS-232-C driver/ receiver Port SCK2 INTPn Port Note (3-wire serial I/O)
PD78014 (slave)
Port
Note
Handshake line
µPD784054
7.5.1 Asynchronous serial interface/3-wire serial (UART/IOE) serial interface channels from which asynchronous serial interface mode three-wire serial mode selected provided. Asynchronous serial interface mode this mode, 1-byte data following start transferred received. internal baud rate generator allows communication wide range baud rates. clock input ASCK also divided define baud rate. baud rate generator also baud rate conforming MIDI standard (31.25 kbps). Figure 7-7. Block Diagram Asynchronous Serial Interface Mode
Internal
Receive buffer
RXB, RXB2
RxD, RxD2
Receive shift register
Transmit shift register
TXS, TXS2
TxD, TxD2
Receive control Parity check
INTSR, INTSR2 INTSER, INTSER2
Transmit control Parity append
INTST, INTST2
Baud rate generator
1/2m fCLK ASCK, ASCK2
Selector
1/2n+1 1/2m
Remark fCLK: internal system clock
µPD784054
3-wire serial mode This mode start transmission when master device makes serial clock active communicate 1-byte data synchronization with this clock. interface this mode communicates with devices that have conventional clocked serial interface. Basically, communication performed using three lines: serial clock (SCK) serial data lines. connect more devices, handshake line necessary. Figure 7-8. Block Diagram 3-Wire Serial Mode
Internal
Direction control circuit
SIO1, SIO2 SI1, Shift register Output latch
SO1,
SCK1, SCK2
Serial clock counter
Interrupt generation circuit
INTCSI1, INTCSI2
Serial clock control circuit
Remark fCLK: internal system clock
Selector
1/2m
1/2n+1
fCLK
µPD784054
Edge Detection Circuit
interrupt input pins (NMI INTP0 through INTP6) input only interrupt requests also trigger signals internal hardware. Because interrupts internal hardware operate detecting specific edges input signals, function detect edges provided. addition, noise rejection function also provided prevent detection wrong edge noise.
INTP0-INTP6 Either rising falling edge Either rising falling edge, both edges Detectable Edge Noise Rejected Analog delay Clock sampling Note
Note
sampling clock selected.
Watchdog Timer
watchdog timer provided detect hang-up CPU. This watchdog timer generates non-maskable interrupt unless cleared software within specified interval time. Once watchdog timer been enable operate, operation cannot stopped software. Moreover, specified whether interrupt watchdog timer interrupt from takes precedence. Figure 7-9. Block Diagram Watchdog Timer
fCLK/29
Selector
fCLK/211 fCLK Divider fCLK/212 fCLK/213
Watchdog timer bits)
Overflow
INTWDT
µPD784054
INTERRUPT FUNCTION
three types interrupt processing shown Table selected. Table 8-1. Interrupt Request Processing
Processing Mode Vectored interrupt Context switching Processed Software Processing Branches executes processing routine (any processing contents). Automatically selects register bank, branches executes processing routine (any processing contents). Firmware Executes data transfer between memory (any processing contents). Contents Saves restores to/from stack. Saves restores to/from fixed area register bank. Retained
Macro service
Interrupt Source
interrupt sources, twenty-three sources listed Table 8-2, instruction execution, operand error available. Four priority levels interrupt processing selected, that nesting during interrupt processing levels interrupt requests that generated same time controlled. However, nesting always advances with macro service (i.e., nesting kept pending). default priority priority (fixed) processing interrupt requests that have occurred same time have same priority level (refer Table 8-2).
µPD784054
Table 8-2. Interrupt Sources
Type Default Priority Software Name instruction BRKCS instruction Operand error result exclusive operands byte byte when STBC, #byte, WDM, #byte, LOCATION instruction executed Detection input edge Overflow watchdog timer Overflow timer Overflow timer Overflow timer Detection input edge (CC00 capture trigger) Generation TM0-CC00 coincidence signal Detection input edge (CC01 capture trigger) Generation TM0-CC01 coincidence signal Detection input edge (CC02 capture trigger) Generation TM0-CC02 coincidence signal Detection input edge (CC03 capture trigger) Generation TM0-CC03 coincidence signal Detection input edge (A/D converter conversion start trigger) Detection input edge Detection input edge Generation TM1-CM10 coincidence signal Generation TM1-CM11 coincidence signal Generation TM4-CM40 coincidence signal Generation TM4-CM41 coincidence signal Occurrence UART0 reception error UART0 reception 3-wire serial I/O1 transfer UART0 transfer Occurrence UART2 reception error UART2 reception 3-wire serial I/O2 transfer UART2 transfer converter conversion (transfer ADCR) Internal External Internal External Internal External Internal External Internal External External Internal Source Trigger Execution instruction Internal/ External Macro Service
Nonmaskable Maskable
INTWDT
(highest)
INTOV0 INTOV1 INTOV4 INTP0 INTCC00
INTP1 INTCC01
INTP2 INTCC02
INTP3 INTCC03
INTP4 INTP5 INTP6 INTCM10 INTCM11 INTCM40 INTCM41 INTSER INTSR INTCSI1
INTST INTSER2 INTSR2 INTCSI2
(lowest)
INTST2 INTAD
µPD784054
Vectored Interrupt
Execution branches processing routine using memory contents vector table address corresponding interrupt source branch destination address. following operations performed that processes interrupt: branch Saves status (contents PSW) stack
returning Restores status from stack Execution returned from processing routine main routine RETI instruction. branch destination address must range FFFFH. Table 8-3. Vector Table Address
Interrupt Source instruction Operand error INTWDT INTOV0 INTOV1 INTOV4 INTP0 INTCC00 INTP1 INTCC01 INTP2 INTCC02 INTP3 INTCC03 INTP4 0014H 0012H 0010H 000EH Vector Table Address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH Interrupt Source INTP5 INTP6 INTCM10 INTCM11 INTCM40 INTCM41 INTSER INTSR INTCSI1 INTST INTSER2 INTSR2 INTCSI2 INTST2 INTAD 0034H 0036H 002EH 0030H 0032H Vector Table Address 0016H 0018H 001AH 001CH 0026H 0028H 002AH 002CH
µPD784054
Context Switching
specific register bank selected hardware when interrupt request generated when BRKCS instruction executed. Execution branches vector address stored advance selected register bank, current contents program counter (PC) program status word (PSW) stacked register bank. branch destination address must range FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Generated
Register bank 0000B Transfer Register bank PC19-16 PC15_0 Exchange Save (bits through temporary register) Save Temporary register Save RSS0 Select register bank (RBS0 RBS2n)
µPD784054
Macro Service
µPD784054 total seven types macro service. Each macro service outlined below. Counter mode: EVTCNT Operation Increments decrements 8-bit macro service counter (MSC). vectored interrupt request generated when value reaches
Application example: Event counter, measurement number times capture Block transfer mode: BLKTRS Operation Transfers block data between buffer specified pointer (SFR.PTR). transfer source destination buffer. length data transferred byte word. number times data transferred (block size) specified MSC. auto-decremented (-1) each time macro service been executed. When value reached vectored interrupt request generated.
SFR.PTR Buffer
Buffer
Internal
Application example: Data transfer/reception serial interface
µPD784054
Block transfer mode (with memory pointer): BLKTRS-P Operation This block transfer mode with memory pointer (MEM.PTR) appended. appended buffer area MEM.PTR freely memory space. Remark MEMP auto-incremented (+1: byte data transfer/+2: word data transfer) each time macro service been executed.
SFR.PTR
Buffer
MEM.PTR Buffer
Internal
Application example: Same Data differential mode: DTADIF Operation Calculates difference between contents specified pointer (SFR.PTR) (current value) contents loaded last data buffer (LDB). Stores result calculation predetermined buffer area. Stores contents current value LDB. number times data transferred (block size) specified MSC. value auto-decremented (-1) each time macro service been executed. When value reached vectored interrupt request generated. Remark differential calculation performed only 16-bit configuration.
SFR.PTR Buffer
Buffer
Differential calculation
Internal
Application example: Measurement period pulse width capture register timer
µPD784054
Data differential mode (with memory pointer): DTADIF-P Operation This data differential mode with memory pointer (MEM.PTR) appended. appended MEM.PTR buffer area which differential data stored memory space freely. Remarks differential calculation performed only 16-bit configuration. buffer specified result operation between MEM.PTR MSCNote. value MEM.PTR updated after data been transferred. Note MEM.PTR (MSC
SFR.PTR Buffer
MEM.PTR Buffer Differential calculation
Internal
Application example: Same monitoring mode0: SFLF0 Operation Checks internal operation CPU. When blocks operating normally, value given subtracting from initial value transferred specified pointer (SFR.PTR). Application example: Used self checking during normal operation. monitoring mode1: SELF1 Operation Checks internal operation CPU. When blocks operating normally, value given subtracting from initial value transferred specified pointer (SFR.PTR). Application example: Used self checking during normal operation.
µPD784054
LOCAL INTERFACE
PD784054 connected external memory (memory mapped I/O), supporting 1Mbyte memory space (refer Figure 9-1). Figure 9-1. Example Local Interface (with external 8-bit specified)
Address
PD784054
A16-A19
Decoder
SRAM PROM Character generator
AD0-AD7
Data
ASTB
Latch
Address AD8-AD15
Gate array expansion Centronics I/F, etc.
µPD784054
Memory Expansion
external program memory data memory expanded from bytes bytes seven steps. When external device connected, address/data read/write strobe signals controlled using ports through through pins. functions these ports pins memory expansion mode register (MM). Table 9-1. Setting Function
Memory Expansion Mode Register MM0-MM3 Port mode External memory expansion mode Port P40-P47 General-purpose port AD0-AD7 AD15 stepwise. Rest pins used general-purpose port pins. through stepwise. Rest pins used general-purpose port pins. ASTB Port P50-P57 Function Port P60-P63 P90-P93
Remark through AD15 used address bus. number pins ports that used address pins changed according size external memory connected (external address space), that external memory expanded stepwise. pins used address pins used general-purpose port pins (refer Table 9-2). external address space seven steps Table 9-2. Operations Ports external memory expansion mode)
Port Port bytes less Note bytes less Note AD10 AD11 AD12 AD13 AD14 AD15 bytes less Note bytes less Note bytes less 256K bytes less bytes less External address space
General-purpose port
Note
When external 16-bit specified, such that external address space this size. When external 16-bit specified, such that pins port (P50 through P57) used pins (AD8 through AD15).
Caution
µPD784054
Memory Space
1M-byte memory space divided into following eight spaces logical addresses. Each space controlled using programmable wait function sizing function. Figure 9-2. Memory Space
512K bytes
256K bytes 128K bytes bytes bytes bytes bytes bytes
Programmable Wait
wait state inserted each eight memory spaces while LWR, signals active. Even memories with different access times connected, therefore, overall efficiency system degraded. addition, address wait function that extends active period ASTB signal also available extend address decode time (this function spaces).
Sizing Function
PD784054 change external data width between bits when external device connected. Even memory space divided eight, width each memory space specified independently.
µPD784054
STANDBY FUNCTION
PD784054 following standby function modes that reduce power consumption chip. HALT mode This mode stops operating clock CPU. reduce average power consumption through intermittent operation combination normal operation this mode. IDLE mode This mode stops entire system with operation oscillation circuit continuing. Normal program operation restored from this mode with power consumption close that STOP mode time equivalent that HALT mode. STOP mode This mode stops oscillator stops internal operations chip minimize power consumption level only leakage current. Standby function invalid mode This mode makes standby function (HALT/IDLE/STOP modes) invalid asserting MODE1 high. This mode useful when standby mode must used because application. These modes programmable. Macro service started from HALT mode. Figure 10-1. Standby Status Transition
MODE1=H Standby function invalid
MODE1=L
Waits stabilization oscillation
ilization stab Oscillati expires time
Macro service request
first processing macro service Macro service
Program operation
STOP (standby)
IDLE (standby)
Interrupt request masked interrupt
HALT (standby)
Note
Only unmasked interrupt request
Remark Only external input valid. watchdog timer cannot used release standby mode (STOP/HALT/IDLE).
rvic
ttin
µPD784054
RESET FUNCTION
When level input RESET pin, internal hardware initialized (reset status). When RESET signal goes high, following data program counter (PC). Lower bits contents address 0000H Middle bits contents address 0001H Higher bits Program execution started from contents Therefore, contents assumed branch destination address, program reset started from address. contents each register program necessary. prevent malfunctioning noise, noise rejection circuit provided RESET input circuit. This noise rejection circuit sampling circuit with analog delay. Figure 11-1. Accepting Reset
Delay
Delay
Delay
initialization
Instruction execution reset start address
RESET (input)
Internal reset signal
Reset starts
Reset ends
Keep RESET signal active until oscillation stabilization time (about elapses when executing reset operation power application when releasing STOP mode reset. Figure 11-2. Reset Operation Power Application
Oscillation stabilization time
Delay
Initializes
Instruction execution reset start address
RESET (input)
Internal reset signal
Reset ends
µPD784054
INSTRUCTION
8-bit instructions combination realized describing MOV, XCH, ADD, ADDC, SUB, SUBC, AND, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 12-1. Instructions 8-Bit Addressing
Operand #byte Operand (MOV) (MOV) (MOV)Note (XCH)Note (XCH) (MOV) (XCH) ADDNote (XCH) saddr saddr' !addr16 !!addr24 [saddrp] [%saddrg] ADDNote PSWL PSWH (MOV) (XCH) (ADD)Note RORNote MULU DIVUW saddr (MOV)Note ADDNote ADDNote (ADD)Note ADDNote DBNZ PUSH CHKL CHKLA !addr16 !!addr24 [saddrp] [%saddrg] mem3 ROR4 ROL4 PSWL PSWH STBC, [TDE+] [TDE-] (MOV) (ADD)Note MOVMNote MOVBKNote DBNZ (MOV) ADDNote ADDNote ADDNote (ADD)Note ADDNote [WHL+] [WHL-] None Note
(ADD)Note (ADD)Note (ADD)Note (ADD)Note ADDNote (MOV) ADDNote ADDNote ADDNote (XCH)
(ADD)Note ADDNote
Notes ADDC, SUB, SUBC, AND, XOR, same ADD. Either second operand used, second operand operand address. ROL, RORC, ROLC, SHR, same ROR. XCHM, CMPME, CMPMNE, CMPMNC, CMPMC same MOVM. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC same MOVBK. saddr saddr2 this combination, some instructions have short code length.
µPD784054
16-bit instructions combination realized describing MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instructions 16-Bit Addressing
Operand #word Operand (MOVW) ADDW
Note
saddrp saddrp' (MOVW)Note (XCHW)Note
sfrp
!addr16 !!addr24
[saddrp] [%saddrg]
[WHL+]
byte
NoneNote
(MOVW) (XCHW)
(MOVW) (XCHW)
MOVW (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW) MULWNote INCW DECW INCW DECW
(ADDW)Note (ADDW)Note (ADDW)Note (ADDW)Note MOVW ADDW
Note
(MOVW) (XCHW)
MOVW XCHW
MOVW XCHW ADDWNote MOVW XCHW ADDWNote
MOVW XCHW ADDWNote
MOVW
SHRW SHLW
(ADDW)Note ADDWNote saddrp MOVW ADDW
Note
(MOVW)Note MOVW (ADDW)Note ADDWNote
sfrp
MOVW
MOVW
MOVW
PUSH MOVTBLW
ADDWNote (ADDW)Note ADDWNote !addr16 !!addr24 [saddrp] [%saddrg] ADDWG SUBWG post MOVW MOVW (MOVW) MOVW
PUSH
PUSH PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes SUBW CMPW same ADDW. Either second operand used, second operand operand address. saddrp saddrp2 this combination, some instructions have short code length. MULUW DIVUX same MULW.
µPD784054
24-bit instructions combination realized describing MOVG, ADDG, SUBG, INCG, DECG, PUSH, Table 12-3. Instructions 24-Bit Addressing
Operand Operand (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) #imm24 (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH saddrg !!addr24 mem1 [%saddrg] MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] NoneNote
Note
Either second operand used, second operand operand address.
µPD784054
manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BCLR, BFSET Table 12-4. Addressing Manipulation Instructions
Operand saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit Operand !!addr24.bit MOV1 AND1 XOR1 saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit MOV1 NOT1 SET1 CLR1 BTCLR BFSET /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 NOT1 SET1 CLR1 NoneNote
Note
Either second operand used, second operand operand address.
µPD784054
Call/return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, BTCLR, BFSET, DBNZ Table 12-5. Addressing Call/Return/Branch Instructions
Operand instruction address Basic instruction BCNote CALL CALL RETCS RETCSB Compound instruction BTCLR BFSET DBNZ CALL CALL CALL CALL CALL CALLF CALLT BRKCS RETI RETB $addr20 $!addr20 !addr16 !!addr20 [rp] [rg] !addr11 [addr5] None
Note
BNZ, BNE, BNC, BNL, BNV, BPO, BPE, BLT, BGE, BLE, BGT, BNH, same
Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, SWRS
µPD784054
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol Input voltage Output voltage Low-level output current output pins Total output pins High-level output current output pins Total output pins Analog input voltage Note converter reference input voltage Operating temperature Storage temperature Note Conditions Ratings -0.5 +7.0 -0.5 -0.5 +0.5 -0.5 -0.5 -100 -0.5 -0.5 -0.5 -0.5 +150 Unit
Notes Pins other than pins Note Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Recommended Operating Conditions
Oscillation Frequency
Capacitance
Parameter Input capacitance Output capacitance capacitance Symbol except measured pins Conditions MIN. TYP. MAX. Unit
µPD784054
Oscillation Circuit Characteristics
Resonator Ceramic resonator crystal resonator Recommended Circuit Item Oscillation frequency (fXX MIN. MAX. Unit
External clock
input frequency
OpenNote HCMOS inverter
input rise, fall time
input high-, low-level width
Note
When EXTC oscillation stabilization time specification register (OSTS) Input reverse phase clock when EXTC
Caution
When using system clock oscillation circuit, wire portion enclosed dotted line diagram above follows prevent adverse influence from wiring capacitance: Keep wiring length short possible. cross wiring with other signal lines. route wiring vicinity line through which high alternating current flows. Always keep ground potential capacitor oscillation circuit same potential VSS. ground capacitor ground pattern through which high current flows. extract signal from oscillation circuit.
µPD784054
Characteristics
Parameter Low-level input voltage High-level input voltage Symbol Low-level output voltage High-level output voltage Input leakage current Analog input leakage current Output leakage current supply current LIAN Data retention voltage Data retention current DDDR DDDR Note Note -400 Note Note Operating mode MHz) HALT mode (fXX MHz) IDLE mode MHz) STOP mode STOP mode VDDDR VDDDR Pull-up resistor Conditions MIN. TYP. MAX. 0.45 Unit
Notes Pins other than pins Note P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5, P27/INTP6, P34/ASCK/SCK1, P37/ASCK2/SCK2, RESET Input pins (except P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used analog inputs) Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used analog input, only during nonsampling operation)
µPD784054
Characteristics Read/write operation
Parameter System clock cycle time Address setup time (vs. ASTB) Address hold time (vs. ASTB) ASTB high-level width AddressRD delay time RDaddress float time Addressdata input time RDdata input time ASTBRD delay time Data hold time (vs. RDaddress active time low-level width AddressLWR, delay time LWR, HWRdata output time ASTBLWR, delay time Data setup time (vs. LWR, HWR) Data hold time (vs. LWR, HWR) LWR, ASTB delay time LWR, low-level width AddressWAIT input time ASTBWAIT input time ASTBWAIT hold time ASTBWAIT delay time RDWAIT input time RDWAIT hold time RDWAIT delay time LWR, HWRWAIT input time LWR, HWRWAIT hold time LWR, HWRWAIT delay time Symbol SAST HSTA WSTH DAID DRID DSTR HRID DWOD DSTW SODW HWOD DWST DAWT DSTWT HSTWT DSTWTH DRWT HRWT DRWTH DWWT HWWT DWWTH 0.5T (1.5 0.5T 1.5T (1.5 1.5T (1.5 (1.5 67.5 Note 67.5 Note 22.5 98.8 116.2 Note 22.5 15.3 68.7 17.2 78.8 57.7 53.7 0.5T (1.5 (2.5 (1.5 0.5T 15.3 17.2 63.7 47.5 (0.5 0.5T (0.5 Expression MIN. 62.5 11.2 11.2 14.2 47.5 100.2 45.7 MAX. Unit
Note
Specification when external wait inserted
Remarks tCYK 1/fCLK (fCLK internal system clock frequency) when address wait inserted, otherwise, indicates number wait cycles specifying external wait pins (WAIT) programmable wait control registers (PWC1, PWC2). tDSTWTH, tDRWTH, tDWWTH). Calculate values expression column with system clock cycle time used because these values depend system clock cycle time (tCYK values above expression column calculated based 62.5
µPD784054
Serial Operation
Parameter Serial clock cycle time Symbol CYSK Conditions SCK1, SCK2 output SCK1, SCK2 input Serial clock low-level width WSKL External clock MIN. TSFT 0.5T SFT-40 0.5T SFT-40 MAX. Unit
SCK1, SCK2 output SCK1, SCK2 input External clock
Serial clock high-level width
WSKH
SCK1, SCK2 output SCK1, SCK2 input External clock
SI1, setup time (vs. SCK1, SCK2) SI1, hold time (vs. SCK1, SCK2) SCK1, SCK2SO1, output delay time
SSSK HSSK DSBSK
Remarks TSFT value software. minimum value tCYK tCYK 1/fCLK (fCLK internal system clock frequency) Other Operations
Parameter high, low-level width INTP0-INTP6 high, low-level width RESET high, low-level width Symbol WNIH WNIL WITH, WITL WRSH WRSL Conditions MIN. MAX. Unit
CYSMP
Remarks tCYSMP sampling clock noise protection control register (NPC) software. When tCYSMP tCYK When tCYSMP tCYK tCYK 1/fCLK (fCLK internal system clock frequency) NIn: 0-6) Timing Test Point
Test point
µPD784054
Converter Characteristics AVSS AVDD VDD)
Parameter Resolution Total error Note Quantization error Conversion time CONV 62.5 Sampling time SAMP 62.5 Zero-scale error Note Full-scale error Note Nonlinearity errorNote Analog input voltage converter reference input voltage current supply current converter data retention current DDDR STOP mode DDDR DDDR -0.3 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±3.5 ±4.5 ±3.5 ±4.5 ±2.5 ±4.5 +0.3 Symbol Conditions MIN. ±0.5 ±0.7 ±1/2 TYP. MAX. Unit %FSR %FSR
Note
quantization error excluded.
Remark tCYK 1/fCLK (fCLK internal system clock frequency).
µPD784054
Read Operation bits)
tCYK (CLK)
AD8-AD15 (Output) tSAST AD0-AD7 (Input/output) Hi-Z tDAID
Higher address
Higher address
Lower address (output) tWSTH
Hi-Z
Data (input)
Hi-Z
Lower address (output)
Hi-Z
tHRID
ASTB (Output) tHSTA tFRA (Output) tDSTR tDRID tDAR tWRL tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tDRA
µPD784054
Write Operation bits)
tCYK (CLK)
AD8-AD15 (Output) tSAST AD0-AD7 (Output) Lower address (Output) tWSTH ASTB (Output) tHSTA (Output) tDSTW
Higher address
Higher address
Undefined
Data (Output) tHWOD
Lower address (Output)
tDWST
tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tHWWT tDWWTH tWWL
tSODW
tDAWT WAIT (Input)
µPD784054
Read Operation bits)
tCYK (CLK)
tSAST AD8-AD15 AD0-AD7 (Input/output) Hi-Z
tDAID Hi-Z Data (Input) Hi-Z Address (Output) Hi-Z
Address (Output) tWSTH
tHRID
ASTB (Output) tHSTA tFRA (Output) tDSTR tDRID tDAR tDSTWTH tHSTWT tDSTWT tDRWT tDAWT WAIT (Input) tHRWT tDRWTH tWRL tDRA
µPD784054
Write Operation bits)
tCYK (CLK)
AD8-AD15 AD0-AD7 (Output)
tSAST Address (Output) tWSTH Undefined Data (Output) tHWOD Address (Output)
ASTB (Output) tHSTA HWR, (Output) tDSTW tDWOD tDAW tDSTWTH tHSTWT tDSTWT tDWWT tHWWT tDWWTH tWWL tSODW tDWST
tDAWT WAIT (Input)
µPD784054
Serial Operation
tCYSK tWSKL SCK1, SCK2 tDSBSK SO1, tWSKH
SI1, tSSSK tHSSK
Interrupt Input Timing
tWNIH tWNIL
tWITH
tWITL
INTP0-INTP6
Reset Input Timing
tWRSH tWRSL
RESET
µPD784054
PACKAGE DRAWING
PLASTIC (14x14)
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 2.7±0.1 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-5
Remark package dimensions materials versions same those mass-production versions.
µPD784054
RECOMMENDED SOLDERING CONDITIONS
These products should soldered mounted under conditions recommended below. details soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, please contact your representative. Table 15-1. Surface-Mount Type Soldering Conditions
PD784054GC-XXX-3B9: 80-pin plastic
Recommended Condition Symbol IR35-00-3
Soldering Method Infrared reflow Partial heating
Soldering Conditions Package peak temperature: Time: sec. max. (210 min.), Number times: max. temperature: max., sec. max. (per side device)
µPD784054
APPENDIX DEVELOPMENT TOOLS
following development tools available developing systems using PD784054. Refer Cautions when development tools used Language processing software
RA78K4 CC78K4 DF784046 CC78K4-L 78K/IV series common assembler package 78K/IV series common compiler package Device file commonly used with PD784046 subseries 78K/IV series common compiler library source file
Flash memory writing tools
Flashpro (Model FL-PR2) FA-80GC Dedicated flash writer microcomputers incorporating flash memory Adapter flash memory writing
Debugging tools When using IE-78K4-NS in-circuit emulator
IE78K4-NS Note IE-70000-MC-PS-B IE-70000-98-IF-C Note IE-70000-CD-IF Note IE-70000-PC-IF-C Note IE-784046-NS-EM1 Note NP-80GC EV-9200GC-80 ID78K4-NS Note SM78K4 DF784046 78K/IV series common in-circuit emulator Power supply unit IE-78K4-NS Interface adapter necessary when PC-9800 series computer (except notebook-type personal computer) used host machine card interface cable necessary when PC-9800 series notebook-type personal computer used host machine Interface adapter necessary when PC/ATor compatible machine used host machine Emulation board emulating PD784054 subseries Emulation probe 80-pin plastic (GC-3B9 type) Socket mounted board target system 80-pin plastic (GC-3B9 type) Integrated debugger IE-78K4-NS 78K/IV series common system simulator Device file commonly used with PD784046 subseries
Note
Under development
µPD784054
When using IE-784000-R in-circuit emulator
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C Note IE-70000-98N-IF IE-70000-PC-IF-B IE-70000-PC-IF-C Note IE-78000-R-SV3 IE-784000-R-EM IE-784046-NS-EM1 Note IE-784046-R-EM1 IE78K4-R-EX2 Note EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784046 78K/IV series common in-circuit emulator Interface adapter necessary when PC-9800 series computer (except notebook-type personal computer) used host machine Interface adapter cable necessary when PC-9800 series notebook-type personal computer used host machine Interface adapter necessary when PC/AT compatible machine used host machine Interface adapter cable necessary when used host machine 78K/IV series common emulation board Emulation board emulating PD784054 Emulation probe conversion board necessary when IE-784046-NS-EM1 used IE-784000-R. necessary when IE-784046-R-EM1 used. Emulation probe 80-pin plastic (GC-3B9 type) Socket mounted board target system made 80-pin plastic (GC-3B9 type) Integrated debugger IE-784000-R 78K/IV series common system simulator Device file commonly used with PD784046 subseries
Real-time
RX78K/IV MX78K4 Real-time 78K/IV series 78K/IV series
µPD784054
Cautions when development tools used ID-78K4-NS, ID78K4, SM78K4 used combination with DF784046. CC78K4 RX78K/IV used combination with RA78K4 DF784046. Flashpro FA-80GC, NP-80GC product Naito Densei Machida Mfg. Co., Ltd. (TEL: (044)8223813). Contact distributor when purchasing these products. Host machines compatible with software follows:
Host Machine [OS] PC-9800 Series PC/AT compatible machines [Japanese/English Windows]
Note Note
HP9000 series [HP-UX SPARCstation [SunOS NEWS(RISC) [NEWS-OS
[Windows
Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note
Note
based software
µPD784054
APPENDIX RELATED DOCUMENTS
Device-related documents
Document Japanese Document English This manual U11447E U11719E U10905E U10095E
µPD784054 Data Sheet µPD78F4046 Preliminary Product Information µPD784054 User's Manual Hardware µPD784054 Special Function Register Table
78K/IV Series User's Manual Instruction 78K/IV Series Instruction List 78K/IV Series Instruction 78K/IV Series Application Note Software Basics
U11154J U11447J U11719J U11113J U10905J U10594J U10595J U10095J
Development tool-related documents (User's Manuals)
Document Japanese RA78K4 Assembler Package Operation Language RA78K4 Structured Assembler Preprocessor CC78K4 Compiler Operation Language CC78K Series Library Source File IE-78K4-NS IE-784000-R IE-784046-NS-EM1 IE-784046-R-EM1 EP-78230 SM78K4 System Simulator Windows Based SM78K Series System Simulator ID78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based Reference U11334J U11162J U11743J U11572J EEU-961 U12322J preparation U12903J Planned U11677J EEU-985 U10093J Planned EEU-1534 Planned U11677E EEU-1515 U10093E U10092E U12796E U10440E U11960E Document English U11334E U11162E U11743E U11572E U11571E
External Part User Open U10092J Interface Specifications Reference Reference Reference U12796J U10440J U11960J
Caution
contents above related documents subject change without notice. sure latest edition document when designing your system.
µPD784054
Embedded software-related documents (User's Manuals)
Document Japanese 78K/IV Series Real-Time Fundamental Installation Debugger 78K/IV Series MX78K4 Fundamental U10603J U10604J U10364J U11779J Document English U10603E U10604E
Other documents
Document Japanese Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability Quality Control Guide Prevent Damages Semiconductor Devices Electrostatic Discharge (ESD) Semiconductor Quality/Reliability Handbook Microcontroller-Related Product Guide Third Parties C10943X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E Document English
Caution
contents above related documents subject change without notice. sure latest edition document when designing your system.
µPD784054
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD784054
IEBus trademark Corporation. Windows either registered trademark trademark Microsoft Corporation United States and/or other countries. PC/AT trademark Corporation. HP9000 Series HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
Some related document preliminary, marked such. Please keep this mind refer this information export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
96.5

µPD784054 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION

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