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VR4300TM, VR4305TM, VR431064-bit Microprocessor µPD30200 µPD30210


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User's Manual
VR4300TM, VR4305TM, VR431064-bit Microprocessor
µPD30200 µPD30210
Document U10504EJ6V0UM00 (6th edition) Date Published June 1999 CP(K) Printed Japan 1996, 1998 1994
[MEMO]
User's Manual U10504EJ6V0UM00
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Series, VR4300 Series, VR3000, VR4000, VR4100, VR4200, VR4300, VR4305, VR4310, VR4400, VR4400PC trademarks Corp. UNIX registered trademark licensed X/Open Company Limited other countries. MC68000 trademark Motorola Inc. IBM370 trademark Corp. iAPX trademark Intel Corp. trademark Digital Equipment Corp. MIPS trademark MIPS Technologies Inc.
User's Manual U10504EJ6V0UM00
Exporting this product equipment that includes this product require governmental license from U.S.A. some countries because this product utilizes technologies limited export control regulations U.S.A.
information this document subject change without notice. Before using this document, please confirm that this latest version. devices/types available every country. Please check with local representative availability additional information. part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. Descriptions circuits, software, other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software, information design customer's equipment shall done under full responsibility customer. Corporation assumes responsibility losses incurred customer third parties arising from these circuits, software, information. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance.
User's Manual U10504EJ6V0UM00
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
User's Manual U10504EJ6V0UM00
MAJOR REVISIONS THIS EDITION
Page Throughout Throughout Throughout 252, µPD30210 been developed. Deletion description µPD30210 model Deletion multiplication rate µPD30210 Change description DivMode Table Clock/Control Interface Signals Addition description 6.3.8 WatchLo (18) WatchHi (19) Registers Change Figure Power-ON Reset Change Figures Cold Reset Soft Reset Change description 14.2 External Normal Interrupts Change description 14.4 Timer Interrupts Change description DMTC0 instruction mark shows major revised points. Contents
User's Manual U10504EJ6V0UM00
PREFACE
Readers This manual targets users intends understand functions VR4300, VR4305 (µPD30200, VR4310 (µPD30210) design application systems using this micropro-cessor. This manual introduces architecture functions VR4300, VR4305, VR4310 users, following organization described below. This manual consists following contents: Introduction Pipeline operation Memory management system cache Exception processing Floating-point operation Hardware Instruction details assumued that readers this manual general knowledge electric engineering, logic circuits, microcomputers. Unless otherwise specified, VR4300 described representative product this manual. When using this manual that VR4305 VR4310, read follows. VR4300 VR4305 VR4300 VR4310 VR4400in this manual represents VR4000TM. VR4000 series this manual represents VR4100TM, VR4200TM, VR4300, VR4305, VR4310, VR4400. learn about detailed function specific instruction, Refer Chapter Instruction Summary, Chapter Floating-Point Operations, Chapter Instruction Details.
Purpose
Organization
read this manual
User's Manual U10504EJ6V0UM00
learn about overall functions VR4300, Read this manual sequential order. learn about electrical specifications VR4300, Refer data sheet which separately available. Conventions Data significance High order left order right Active (top over signal names) Description item with text Caution Important information Remark Supplement Numeric representation binary decimal hexadecimal Prefixes indicating power (address space, memory capacity): (kilo) 1024 (mega) 10242 (giga) 10243 (tela) 10244 (peta) 10245 (exa) 10246 also following documents. related documents indicated this publication include preliminary versions. However, preliminary versions marked such. Document Name VR4300, VR4305, VR4310 User's Manual Document Number This manual U10116E U10710E U11788J (Japanese only)
Related documents
µPD30200, 30210 Data Sheet
Series Application Note Programming Guide VR4000 Series Application Note Simulation Guide
User's Manual U10504EJ6V0UM00
CONTENTS
Chapter
1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.5.1 1.5.2
General.31
Characteristics.32 Ordering Information 64-Bit Architecture.33 VR4300 Processor Internal Block Configuration Registers Instruction Overview.39 Data Formats Addressing System Control Coprocessor (CP0) Floating-Point Unit (FPU), CP1.47 Internal Cache Memory Management System (MMU) Translation Lookaside Buffer (TLB) Operating Modes Instruction Pipeline
Chapter
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5
Functions
Configuration (Top View).52 Functions System Interface Signals Clock/Control Interface Signals Interrupt Interface Signals.57 Joint Test Action Group (JTAG) Interface Signals.58 Initialization Interface Signals
Chapter
3.2.1 3.2.2
Instruction Summary
Instruction Formats Instruction Classes Load/Store Instructions Computational Instructions
User's Manual U10504EJ6V0UM00
3.2.3 3.2.4 3.2.5 3.2.6
Jump/Branch Instructions.77 Special Instructions Coprocessor Instructions System Control Coprocessor (CP0) Instructions.86
Chapter
4.1.1 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.6.7 4.6.8 4.6.9 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9
Pipeline
General Pipeline Operations Branch Delay.94 Load Delay Pipeline Operation.95 Interlock Exception Handling.103 Pipeline Interlocks Exceptions.106 Pipeline Interlocks .106 Instruction Miss (ITM) .107 Instruction Cache Busy (ICB) .108 Multicycle Instruction Interlock (MCI).109 Load Interlock (LDI) .110 Data Cache Miss (DCM) .111 Data Cache Busy (DCB) .111 CACHE Operation (COp) .112 Coprocessor Bypass Interlock (CP0I) .113 Pipeline Exceptions.114 Instruction-Independent Exceptions (Reset, NMI, Interrupt) .114 Instruction-Dependent Exceptions .115 Interactions between Interlocks Exceptions .115 Exception Interlock Priorities .116 WB-Stage Interlock Exception Priorities .117 DC-Stage Interlock Exception Priorities .117 EX-Stage Interlock Exception Priorities .118 RF-Stage Interlock Exception Priorities.118 Bypassing .119 Code Compatibility .119 Write Buffer .120
User's Manual U10504EJ6V0UM00
Chapter
5.2.1 5.2.2 5.2.3 5.2.4 5.3.1 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.4.10 5.4.11
Memory Management System .121 CONTENTS
Translation Lookaside Buffer (TLB).122 Memory Management System Architecture .122 Operating Modes .127 Virtual Addressing User Mode.127 Virtual Addressing Supervisor Mode.129 Kernel Mode Operations .133 System Control Coprocessor .142 Format Entry .143 Registers .146 Index Register .146 Random Register (1).147 EntryHi (10), EntryLo0 (2), EntryLo1 (3), PageMask Registers.148 Wired Register .150 Processor Revision Identifier (PRId) Register (15).151 Config Register (16) .151 Load Linked Address (LLAddr) Register (17).154 Cache Registers [TagLo (28) TagHi (29)] .154 Virtual-to-Physical Address Translation Process.155 Misses .158 Instructions.158
Chapter
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8
Exception Processing .159
Exception Processing Operation .160 Precision Exceptions .161 Exception Processing Registers .161 Context Register .163 BadVAddr Register (8).164 Count Register .164 Compare Register (11) .165 Status Register (12) .165 Cause Register (13) .171 Exception Program Counter (EPC) Register (14) .174 WatchLo (18) WatchHi (19) Registers.175
User's Manual U10504EJ6V0UM00
6.3.9 6.3.10 6.3.11 6.3.12 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 6.4.15 6.4.16 6.4.17 6.4.18
XContext Register (20).176 Parity Error (PErr) Register (26) .178 Cache Error (CacheErr) Register (27).178 Error Exception Program Counter (Error EPC) Register (30) .179 Exception Details .180 Exception Types .180 Exception Vector Locations .180 Priority Exceptions.182 Cold Reset Exception .183 Soft Reset Exception .184 Non-maskable Interrupt (NMI) Exception .185 Address Error Exception .186 Exceptions.187 Error Exception .190 System Call Exception .191 Breakpoint Exception .192 Coprocessor Unusable Exception.193 Reserved Instruction Exception.194 Trap Exception .195 Integer Overflow Exception .196 Floating-Point Exception.197 Watch Exception .198 Interrupt Exception.199 Exception Handling Servicing Flowcharts .200
Chapter
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5
Floating-Point Operations.207
Overview.208 Programming Model .208 Floating-Point General Purpose Register (FGR).208 Floating-Point Registers (FPR) .210 Floating-Point Control Registers (FCRs) .211 Control/Status Register (FCR31) .211 Implementation/Revision Register (FCR0).216 Floating-Point Formats .217
User's Manual U10504EJ6V0UM00
7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6
Fixed-Point Format .220
CONTENTS
Overview.221 Floating-Point Load/Store/Transfer Instructions.221 Convert Instructions .224 Computational Instructions .226 Compare Instructions.227 Branch Instructions .229 Instruction Execution Time.230 Pipeline Synchronization.233
Chapter
8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7
Floating-Point Exceptions .235
Types Exceptions.236 Exception Processing.237 Flags .238 Inexact Exception .240 Invalid Operation Exception .240 Divide-by-Zero Exception (Z).241 Overflow Exception .242 Underflow Exception .242 Unimplemented Operation Exception .243 Saving Returning State.244 Handling IEEE754 Exceptions.244
Chapter
9.2.1 9.2.2 9.2.3 9.3.1 9.3.2 9.3.3 9.3.4
Initialization Interface .247
Functional Overview .248 Reset Signal Description .249 Power-ON Reset.249 Cold Reset .250 Soft Reset.251 VR4300 Processor Modes.254 Power Modes .254 Privilege Modes.255 Floating-Point Registers .255 Reverse Endianess .256
User's Manual U10504EJ6V0UM00
9.3.5 9.3.6 9.3.7
Instruction Trace Support .256 Bootstrap Exception Vector (BEV).256 Interrupt Enable (IE).256
Chapter
10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.4 10.5 10.6 10.6.1 10.6.2
Clock Interface .257
Signal Terminology .258 Basic System Clocks .259 System Timing Parameters.263 Synchronization with SClock .263 Synchronization with MasterClock .263 Phase-Locked Loop (PLL) .263 Power Mode Operation .264 Connecting Clocks Phase-Locked System .265 Connecting Clocks System without Phase Locking .266 Connecting Gate-Array Device .266 Connecting CMOS Discrete Device.269
Chapter
11.1 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.4 11.5 11.5.1 11.5.2 11.6
Cache Memory .273
Memory Organization.274 Cache Organization.275 Organization Instruction Cache (I-Cache) .276 Organization Data Cache (D-Cache).277 Accessing Caches .278 Cache Operations .279 Cache Write Policy.280 Data Cache Line Replacement .280 Instruction Cache Line Replacement.282 Cache States .283 Cache State Transition Diagrams .283 Data Cache State Transition .284 Instruction Cache State Transition .285 Manipulation Caches External Agent .285
User's Manual U10504EJ6V0UM00
Chapter
12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.5 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 12.6.6 12.6.7 12.6.8 12.7
System Interface .287 CONTENTS
Terminology .288 System Interface Description.289 Physical Addresses .289 Interface Buses .291 Address Data Cycles.292 Issue Cycles .293 Handshake Signals.295 System Interface Protocols .296 Master Slave States.296 Moving from Master Slave State.297 External Arbitration.297 Uncompelled Change Slave State .298 Processor External Requests.298 Processor Requests .300 Processor Read Request .301 Processor Write Request.301 External Requests .302 External Write Request.303 Read Response.303 Handling Requests.304 Fetch Miss .304 Load Miss .304 Store Miss.304 Loads Stores Uncached Area .305 CACHE Instructions.305 Processor Request External Request Protocols.306 Processor Request Protocols.306 Processor Read Request Protocol.306 Processor Write Request Protocol .309 Flow Control Processor Request .311 External Request Protocols.312 External Arbitration Protocol .313 External Write Request Protocol .316 External Read Response Protocol .317 Successive Processing Request .321
User's Manual U10504EJ6V0UM00
12.7.1 12.7.2 12.7.3 12.7.4 12.8 12.8.1 12.8.2 12.8.3 12.8.4 12.9 12.9.1 12.9.2 12.10 12.11 12.11.1 12.11.2 12.11.3 12.11.4 12.11.5 12.11.6 12.12
Successive Processor Write Requests .321 Processor Write Request Followed Processor Read Request .322 Processor Read Request Followed Processor Write Request .323 Processor Write Request Followed External Write Request .324 Discarding Re-Executing Commands .325 Re-Execution Processor Commands .325 Discarding Re-Executing Write Command .325 Discarding Re-Executing Read Command.327 Executing Discarding Command.328 Data Flow Control .330 Independent Transfer SysAD(31:0) .331 System Endianness .331 System Interface Cycle Time.332 System Interface Commands Data Identifiers .333 Command Data Identifier Syntax .333 System Interface Command Syntax .334 Read Requests .334 Write Requests.336 System Interface Data Identifier Syntax.337 Data Identifier Definitions.337 System Interface Addresses .339
12.10.1 Release Latency Time .332
12.12.1 Addressing Conventions.339 12.12.2 Sequential Subblock Ordering.339
Chapter
13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4
JTAG Interface.341
Principles Boundary Scanning.342 Signal Summary.343 JTAG Controller Registers .344 Instruction Register .344 Bypass Register .345 Boundary-Scan Register.346 Test Access Port (TAP) .347
User's Manual U10504EJ6V0UM00
13.3.5 13.3.6 13.3.7 13.4
Controller .348 CONTENTS Controller Reset.348 Controller States .348 Notes Implementation .350
Chapter
14.1 14.2 14.3 14.4 14.5 14.5.1 14.5.2
Interrupts .351
Non-maskable Interrupt .352 External Normal Interrupts .353 Software Interrupts .354 Timer Interrupt .354 Generation Interrupt Request Signal.354 Detection Hardware Interrupts.356 Masking Interrupt Request Signals .357
Chapter
15.1 15.1.1 15.1.2 15.1.3
Power Management .359
Features .360 Normal Power Mode .360 Power Mode .360 Power Mode .361
Chapter
16.1 16.2 16.3 16.4 16.5 16.6 16.7
Instruction Details .363
Instruction Notation Conventions.364 Load Store Instructions .367 Jump Branch Instructions.369 Coprocessor Instructions .369 System Control Coprocessor (CP0) Instructions.370 Instructions .370 Instruction Opcode Encoding .544
Chapter
17.1
Instruction Details .547
Instruction Formats.548
User's Manual U10504EJ6V0UM00
17.2 17.3 17.4 17.5 17.6
Instruction Notation Conventions.552 Load Store Instructions .553 Floating-point Computational Instructions .555 Instructions.558 Instruction Opcode Encoding.611
Chapter Chapter
Passive Elements .613 Coprocessor Hazards.617
Appendix Differences between VR4300, VR4305, VR4310.625 Appendix Differences from VR4400 .627
B.1.1 B.1.2 B.1.3 B.1.4 B.1.5 B.1.6 B.1.7 B.2.1 B.2.2 B.3.1 B.3.2 B.3.3 B.3.4 B.3.5 B.3.6 B.3.7
Differences Software .628 CACHE Instruction .628 Cache Parity.628 Status Register .628 Config Register.629 Status FCR31 Occurrence Unimplemented Operation Exception.629 Integer Zero Division .629 Cache Parity Error Exception.629 Differences System Design.631 Initialization Processor.631 System Interface .631 Other Differences.634 Cache Size .634 TLB.634 Floating-Point Unit.635 Pipeline .635 Interrupt .636 Kernel Physical Address Segment Configuration .636 JTAG .636
User's Manual U10504EJ6V0UM00
Appendix Differences from VR4200 .639 CONTENTS
C.1.1 C.1.2 C.1.3 C.1.4 C.2.1 C.2.2 C.2.3 C.3.1 C.3.2 C.3.3 C.3.4 Differences Software .640 Cache Parity.640 Status Register .640 Config Register.640 Cache Parity Error Exception.641 Differences System Design.642 System Interface .642 Clock.642 Package.643 Other Differences.643 Physical Address .643 Write Buffer.644 Reset .644 Status(3:0) Pins.644
Appendix Index.645
User's Manual U10504EJ6V0UM00
LIST FIGURES (1/6)
Fig. Title Page
4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17
Internal Block Diagram Registers Instruction Formats Big-Endian Byte Ordering Little-Endian Byte Ordering Big-Endian Data Doubleword Little-Endian Data Doubleword Misaligned Word Addressing Registers Instruction Formats Byte Access within Doubleword Pipeline Stages Instruction Execution Pipeline Pipeline Operations Branch Delay Instruction Pipeline Operations Jump Link Register Instruction Pipeline Operations Branch Equal Instruction Pipeline Operations Trap Less Than Instruction Pipeline Operations Load Word Instruction Pipeline Operations Store Word Instruction Pipeline Operations Interlocks, Exceptions, Faults Correspondence Pipeline Stage Interlock Exception Condition Instruction Miss Interlock Example Instruction Cache Busy Interlock Example Multicycle Instruction Interlock Example Load Interlock Example Data Cache Miss Followed Load Interlock
User's Manual U10504EJ6V0UM00
LIST FIGURES (2/6)
Fig. 4-18 4-19 4-20 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 Title Page
Example Coprocessor Bypass Interlock (CP0I) Execution Interlock Priorities Write Buffer Format Overview Virtual-to-Physical Address Translation 32-bit Mode Virtual Address Translation 64-bit Mode Virtual Address Translation User Mode Virtual Address Space Supervisor Mode Address Space Kernel Mode Address Space Details xkphys Field Registers Entry Format Entry Registers Index Register Random Register Wired Register Boundary Wired Register Processor Revision Identifier Register Config Register LLAddr Register TagLo TagHi Register Address Translation Context Register BadVAddr Register Count Register Compare Register Status Register Self-Diagnostic Status Field Cause Register Register
User's Manual U10504EJ6V0UM00
LIST FIGURES (3/6)
Fig. 6-10 6-11 6-12 6-13 6-14 6-15 6-16 10-1 10-2 10-3 10-4 10-5 Title Page
WatchLo WatchHi Register XContext Register PErr Register CacheErr Register ErrorEPC Register General Purpose Exception Handler TLB/XTLB Miss Exception Handler Cold Reset, Soft Reset Exception Handler Registers Control/Status Register Assignments Control/Status Register (FCR31) Cause, Enable, Flag Fields Implementation/Revision Register Single-Precision Floating-Point Format Double-Precision Floating-Point Format Fixed-Point Format Fixed-Point Format DC-to-EX Hardware Interlock Bypass FCR31 Cause/Enable/Flag Bits Power-ON Reset Cold Reset Soft Reset. Signal Transitions Clock-to-Q Delay When Frequency Ratio MasterClock PClock 1:1.5 When Frequency Ratio MasterClock PClock Phase-Locked System
User's Manual U10504EJ6V0UM00
LIST FIGURES (4/6)
Fig. 10-6 10-7 Title Page
Gate-Array System without Phase Lock, Using VR4300 Processor Gate-Array CMOS System without Phase Lock, Using VR4300 Processor Logical Hierarchy Memory VR4300 Cache Support VR4300 8-Word I-Cache Line Format VR4300 4-Word Data Cache Line Format Cache Data Organization Data Cache State Diagram Instruction Cache State Diagram Data Sequence Instruction Cache Read Request Data Sequence Data Cache Read Request System Interface Buses Signal Status Processor Request Address Cycle Extended Signal System Interface Register-to-Register Operation Requests System Events Processor Request Flow External Request Flow Read Response Unforcible Transition Processor Read Request Delayed Processor Read Request Processor Block Write Request (Write Data Pattern: Processor Block Write Request (Write Data Pattern: Dxx) Delayed Processor Read Request Delayed Second Processor Write Request Arbitration External Request Arbitration Processor External Write Request Protocol
User's Manual U10504EJ6V0UM00
11-1 11-2 11-3 11-4 11-5 11-6 11-7 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19
LIST FIGURES (5/6)
Fig. 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 12-29 12-30 12-31 12-32 12-33 12-34 12-35 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2
Title
Page
Read Request/Read Response Protocol Block Read Response Slave Status External Write Request Following Read Response When External Write Request Takes Precedence While Processor Read Request Pending Successive Block Write Requests (Write Data Pattern: Successive Single Write Requests (Write Data Pattern: Dxx) Processor Write Request Followed Processor Read Request (Write Data Pattern: Processor Single Read Request Followed Block Write Request (Write Data Pattern: Successive Processor Write Requests Followed External Write Request (Write Data Pattern: Discarding Re-executing Processor Single Write Request Discarding Re-executing Processor Single Read Request Discarding Mastership External Agent Processor Request System Interface Command Syntax Definition Read Request SysCmd(4:0) Definition Write Request SysCmd(4:0) Definition Data Identifier SysCmd(4:0) Definition JTAG Boundary-Scan Cells JTAG Interface Signals Registers Instruction Register Bypass Register Operation Output Enable Boundary-Scan Register JTAG Test Access Port Signal Interrupt Register Bits Enables Bits
User's Manual U10504EJ6V0UM00
LIST FIGURES (6/6)
Fig. 14-3 14-4 16-1 17-1 17-2 17-3 18-1 18-2 Title Page
Hardware Interrupt Request Signals Masking Interrupt Requests VR4300 Opcode Encoding Load Store Instruction Format Computational Instruction Format Encoding Instructions Connection Example Passive Elements Layout Example Capacitor
User's Manual U10504EJ6V0UM00
LIST TABLES (1/4)
Table 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 Title Page
Frequency ratio between PClock MasterClock System Control Coprocessor (CP0) Register Definitions System Interface Signals Clock/Control Interface Signals Interrupt Interface Signals JTAG Interface Signals Initialization Interface Signals Number Cycles Load Store Instruction Delay Slot Load/Store Instructions Load/Store Instructions (Extended ISA) Immediate Instructions Immediate Instruction (Extended ISA) Three-Operand Type Instruction Three-Operand Type Instructions (Extended ISA) Shift Instructions Shift Instructions (Extended ISA) Multiply/Divide Instructions Multiply/Divide Instructions (Extended ISA) Number Cycles Stalled Multiply/ Divide Instruction Number Delay Slot Cycles Jump/ Branch Instruction Jump Instructions Branch Instructions Branch Instructions (Extended ISA) Special Instructions Special Instructions (Extended ISA) Coprocessor Instructions Coprocessor Instructions (Extended ISA) System Control Coprocessor (CP0) Instruction
User's Manual U10504EJ6V0UM00
LIST TABLES (2/4)
Table 7-10 7-11 7-12 Title Page
Description Pipeline Showing Stage Which Operations Commence Description Pipeline Exceptions Description Pipeline Interlocks 32-bit 64-bit User Mode Segments 32-bit 64-bit Supervisor Mode Segments 32-bit Kernel Mode Segments 64-bit Kernel Mode Segments Cache xkphys Address Space Cache Algorithm Mask Field Values Page Sizes Exception Processing Registers Cause Register ExcCode Field 64-Bit Mode Exception Vector Base Addresses 32-Bit Mode Exception Vector Base Addresses Exception Priority Order Floating-Point Control Register Assignments Flush Values Denormalized Number Results Rounding Mode Control Bits Equations Calculating Values Single-and Double-Precision Floating-Point Format Floating-Point Format Parameter Values Minimum Maximum Floating-Point Values Load/Store/Transfer Instructions Convert Instruction Computational Instructions Compare Instruction Mnemonics Definitions Compare Instruction Conditions Branch Instructions
User's Manual U10504EJ6V0UM00
LIST TABLES (3/4)
Table 7-13 7-14 10-1 11-1 11-2 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 13-1 13-2 16-1 16-2 16-3 17-1 17-2 Title Page
Number Load/Store/Transfer Instruction Execution Cycles Number Instruction Delay Cycles Default IEEE754 Exception Values Internal Results Flag Status Frequency Ratio between PClock MasterClock Stall Cycle Count Data Cache Miss Stall Cycle Count Instruction Cache Miss System Interface Requests Release Latency Time External Requests Encoding SysCmd3 System Interface Commands Encoding SysCmd2 Read Requests Encoding SysCmd(1:0) Block Read Requests Encoding SysCmd(1:0) Single Read Requests Encoding SysCmd2 Write Requests Encoding SysCmd(1:0) Block Write Requests Encoding SysCmd(1:0) Single Write Requests Processor Data Identifier Encoding SysCmd(3:0) External Data Identifier Encoding SysCmd(3:0) JTAG Instruction Register Encoding JTAG Scan Order Instruction Operation Notations Load Store Instruction Common Functions Access Type Specifications Load/Store Instructions Valid Instruction Formats Logical Reverse Predicates Condition True/False
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Table 17-3 17-4 17-5 19-1 19-2 Title Page
Load Store Instructions Common Functions Format Field Decoding Floating-Point Computational Instructions Operations Coprocessor Hazards Example Calculating Number Hazards Number Instructions Inserted Differences between VR4300, VR4305, VR4310 Differences Software Differences System Design Other Differences Differences Software Differences System Design Other Differences
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This chapter outlines RISC 64-bit microprocessor VR4300, VR4305 (µPD30200), VR4310 (µPD30210).
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Characteristics
VR4300 VR4305, VR4310 members SeriesRISC (Reduced Instruction Computer) microprocessors high-performance 64-bit microprocessor employing RISC architecture developed MIPSTM. instructions upward-compatible with instructions VR3000Series completely compatible with those VR4400 VR4200. Therefore, existing applications used with VR4300, VR4305, VR4310. VR4300, VR4305, VR4310 have following features: Internal operating frequency: max. (µPD30200-80), max. (µPD30200-100), max. (µPD30200-133, 30210-133), max. (µPD30210-167) 64-bit architecture supporting 64-bit data processing Optimized, 5-stage pipeline processing High-speed translation lookaside buffer (TLB) supporting virtual addresses double entries) Address space Physical: bits Virtual: bits (64-bit mode) bits (32-bit mode) Supports single-precision double-precision floating-point operations On-chip cache memories Instruction: bytes Data: bytes Employs write back cache system store operation system decreased 32-bit external interface facilitating system development Multiplies external operating frequency (input clock interface) create internal operating frequency. Multiple selected power application (µPD30200-80: (µPD30200-100: (µPD30200-133: (µPD30210-133: (µPD30210-167:
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Write buffer power mode Reduces internal system clocks normal level. Also reduces power consumption Software-compatible with VR4400 VR4200 upwardcompatible with VR3000 Series Supply voltage: (µPD30200-80, µPD30200-100), (µPD30200-133,
Ordering Information
Part Number Package 120-pin plastic 120-pin plastic 120-pin plastic 120-pin plastic 120-pin plastic Maximum Operating Frequency (MHz)
µPD30200GD-80-LBB µPD30200GD-100-MBB µPD30200GD-133-MBB µPD30210GD-133-MBB µPD30210GD-167-MBB
64-Bit Architecture
VR4300 64-bit high-performance microprocessor. also execute 32bit applications even when operates 64-bit microprocessor.
VR4300 Processor
Figure shows internal block diagram VR4300. VR4300 equipped with full-associative high-speed translation lookaside buffer (TLB) that entries with pages corresponding each entry; data cache instruction cache; FPU, addition high-performance integer operation unit.
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Data/Address
Control
MasterClock
System Interface
Clock Generator
Instruction Cache
Data Cache
Instruction Address
Execution Unit
Pipeline Control
Figure
Internal Block Diagram
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1.4.1 Internal Block Configuration
System Interface allows processor access external resources such memories. contains 32-bit multiplexed address/data bus, with per-byte parity, clock signals, interrupt request signals, various control signals. compatible with System interface used VR4400 VR4200. Clock Generator generates pipeline clock (PClock) based externally input clock (MasterClock). frequency PClock selected setting frequency ratio between MasterClock PClock. This ratio using DivMode pins power application. (For setting DivMode pins, refer Table Clock/Control Interface Signals.) Table indicates selectable frequency ratio. System interface clock (SClock) usually same frequency MasterClock. Table Product Name VR4300 VR4305 VR4310 Frequency ratio between PClock MasterClock Selectable Frequency Ratio (MasterClock PClock) 1.5*1, 2.5*3,
DivMode DivMode DivMode DivMode
Selectable with model only (With model, this setting reserved.) Selectable with model only (With model, this setting reserved.) Selectable with model only (With model, this setting reserved.) Status register during operation, frequencies PClock SClock reduced normal frequency. Because (Phase-Locked Loop) technique employed, skew (phase difference) between external clock internal operation clock minimized. Instruction Cache direct-mapped, virtually-indexed, physically-tagged. capacity Kbytes. Execution Unit hardware resources execute integer floating-point instructions. 64-bit register file, 64-bit integer/mantissa datapath, 12bit exponent datapath. provided with dedicated multiplexer order process multiply instruction high speed. Coprocessor (CP0) memory management unit (MMU) handles exception processing. handles address translation checks memory accesses that occur between different memory segments (user, supervisor, kernel). translation lookaside buffer (TLB) used translate virtual physical addresses.
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Data Cache direct-mapped, virtually-indexed physically-tagged writeback cache. capacity Kbytes. Instruction Address calculates effective address next instruction fetched. contains incrementer Program Counter (PC), target address adder, conditional branch address selector. Pipeline Control ensures instruction pipeline operates properly (should following conditions occur: pipeline stall exception).
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1.4.2 Registers
processor provides following registers: 64-bit general purpose registers, GPRs 64-bit floating-point operation registers, FPRs
addition, processor provides following special registers: 64-bit Program Counter, register 64-bit register, containing integer multiply divide highorder doubleword result 64-bit register, containing integer multiply divide loworder doubleword result 1-bit Load/Link LLBit register 32-bit floating-point Implementation/Revision register, FCR0 32-bit floating-point Control/Status register, FCR31
General Purpose registers have assigned functions: hardwired value zero, used target register instruction whose result discarded. also used source when zero value needed. link register used JALR instructions. used other instructions. Make sure that other data used calculations does overlap with register used JAL/JALR instruction.
Furthermore, processor contains registers system control processor (CP0) which perform exception processing address management. registers operate either 32-bit 64-bit registers, depending VR4300 processor mode operation. Figure shows registers.
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General Purpose Registers Multiply Divide Registers
Link address
Program Counter
Load/Link Register Floating-Point Registers
LLbit
Floating-Point Control Registers Implementation/Revision Control/Status
Figure
Registers
VR4300 processor Program Status Word (PSW) register such; this covered Status Cause registers incorporated within System Control Coprocessor (CP0). registers, refer 1.4.5 System Control Coprocessor (CP0).
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1.4.3 Instruction Overview
Each instruction bits long. shown Figure 1-3, there three instruction formats: immediate (I-type) jump (J-type) register (R-type)
I-Type (Immediate) J-Type (Jump) R-Type (Register)
target
immediate
funct
Figure
Instruction Formats
instruction further divided into following groupings: Load Store instructions move data between memory general purpose registers. They immediate (I-type) instructions, since only addressing mode supported base register plus 16-bit, signed immediate offset. Computational instructions perform arithmetic, logical, shift, multiply, divide operations values registers. They include register (R-type, which both operands result stored registers) immediate (I-type, which operand 16-bit signed immediate value) formats. Jump Branch instructions change control flow program. Jumps always made address formed combining 26-bit target address with high-order bits Program Counter (J-type format) register address (R-type format). Branch instructions performed 16-bit offset address relative program counter (I-type). Jump Link instructions save their return address register
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Coprocessor instructions (CPz) perform operations coprocessors. Coprocessor load store instructions I-type. opposed instructions, instructions specific coprocessor. (Refer Chapter Floating-Point Operations.) Coprocessor (system coprocessor, CP0) instructions perform operations registers control memory-management exception-handling facilities processor. Special instructions perform system call exception breakpoint exception operations, cause branch general exceptionhandling vector based upon result comparison. These instructions occur both R-type (both operands result registers) I-type (one operand 16-bit immediate value) formats.
each instruction, refer Chapter Instruction Summary Chapter Instruction Details.
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1.4.4 Data Formats Addressing
VR4300 processor uses four data formats: 64-bit doubleword, 32-bit word, 16-bit halfword, 8-bit byte. Byte ordering within larger data formats-halfword, word, doubleword-can configured either big-endian little-endian. When VR4300 processor configured big-endian system, byte most-significant (leftmost) byte, thereby providing compatibility with 68000 conventions. Figure shows this configuration.
Higher Address
Word Address
Lower Address
Figure
Big-Endian Byte Ordering
Remarks most-significant byte lowest address. word addressed address most-significant byte. When configured little-endian system, byte always least-significant (rightmost) byte, which compatible with iAPX conventions. Figure shows this configuration. Unless otherwise specified, little endian used throughout this manual.
Higher Address
Word Address
Lower Address
Figure
Little-Endian Byte Ordering
Remarks least-significant byte lowest address. word addressed address least-significant byte.
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Higher Doubleword Address Address Lower Address
Word
Halfword
Byte
Figure
Big-Endian Data Doubleword
Remarks most-significant byte lowest address. word addressed address most-significant byte.
Higher Doubleword Address Address Lower Address
Word
Halfword
Byte
Figure
Little-Endian Data Doubleword
Remarks least-significant byte lowest address. word addressed address least-significant byte.
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uses byte addressing halfword, word, doubleword accesses with following alignment constraints: Halfword accesses must aligned even byte boundary 4.). Word accesses must aligned byte boundary divisible four 8.). Doubleword accesses must aligned byte boundary divisible eight 16.).
following special instructions load store words that aligned 4byte (word) 8-word (doubleword) boundaries:
These instructions always used pairs access data aligned boundary. access data aligned boundary, additional cycle necessary compared when accessing data aligned boundary. Figure illustrates word misaligned having byte address accessed little endian.
Higher Address Lower Address Big-Endian
Higher Address Lower Address Little-Endian
Figure
Misaligned Word Addressing
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1.4.5 System Control Coprocessor (CP0)
MIPS defines four types coprocessors (CP0 through CP3). internal system control coprocessor supports virtual memory system exception processing. internal floating-point unit. reserved future definition. also reserved expansion. instruction executed, reserved instruction exception occurs. converts virtual addresses into physical addresses, selects operating mode (Kernel, supervisor, user mode), control exceptions. also controls cache subsystem analyze causes return execution from error processing. register VR4300 same that VR4200. Because VR4300 does have parity check function, however, parity error register (26) cache error register (27) practically operate. These registers defined maintain compatibility with VR4200. Figure shows register. Table briefly explains each register. details registers related virtual memory system, refer Chapter Memory Management System, details registers used exception processing, refer Chapter Exception Processing.
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Register Name Index Random EntryLo0 EntryLo1 Context PageMask Wired
Reg.
Register Name Config LLAddr WatchLo WatchHi XContext
Reg.
BadVAddr Count EntryHi Compare Status Cause PRId Memory Management
Exception Processing Parity Error Cache Error TagLo TagHi ErrorEPC
Future
Figure
Registers
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Table Number 21-25 Register Index Random EntryLo0 EntryLo1 Context PageMask Wired BadVAddr Count EntryHi Compare Status Cause PRId Config LLAddr WatchLo WatchHi XContext Parity Error Cache TagLo TagHi ErrorEPC
System Control Coprocessor (CP0) Register Definitions Description Programmable pointer into array Pseudorandom pointer into array (read only) half entry even virtual address (VPN) half entry virtual address (VPN) Pointer kernel virtual page table entry (PTE) 32-bit mode Page size specification Number wired entries Reserved future Display virtual address that occurred error last Timer Count High half entry (including ASID) Timer Compare Value Operation status setting Display cause last exception Exception Program Counter Processor Revision Identifier Memory system mode setting Load Linked instruction address display Memory reference trap address bits Memory reference trap address high bits Pointer Kernel virtual table 64-bit mode Reserved future Cache parity bits Cache Error Status register Cache register Cache register high Error Exception Program Counter Reserved future
Error*
These registers defined maintain compatibility with VR4200, used with hardware VR4300.
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1.4.6 Floating-Point Unit (FPU),
floating-point unit (FPU) operates coprocessor performs arithmetic operations floating-point values. FPU, with associated system software, fully conforms requirements ANSI/IEEE Standard 754-1985, IEEE Standard Binary Floating-Point Arithmetic. includes: Full 64-bit Operation. contain either 64-bit registers hold single-precision double-precision values. Another sixteen floating-point registers used setting Status register Moreover, 32-bit Control/Status register provided, conforming IEEE exception processing standard. Load Store Instruction Set. Like CPU, uses load- store-based instruction set. Floating-point operations started single cycle, however execution floating-point allowed overlap other operations. Sharing Hardware. There separate VR4300; floating-point operations processed same hardware used integer instructions.
1.4.7 Internal Cache
VR4300 instruction cache data cache enhance efficiency pipelining. Each cache data width bits accessed clock. instruction cache data cache accessed parallel. instruction cache capacity bytes, while data cache capacity bytes. details cache, refer Chapter Cache Memory.
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Memory Management System (MMU)
VR4300 processor 32-bit physical addressing range Gbytes. However, since rare systems implement physical memory space this large, provides logical expansion memory space programmer translating addresses into large virtual address space. VR4300 processor supports following addressing modes: 32-bit mode, which virtual address space divided into Gbytes user process Gbytes kernel. 64-bit mode, which virtual address expanded Tbyte (240 bytes) user virtual address space.
detailed description these address spaces given Chapter Memory Management System.
1.5.1 Translation Lookaside Buffer (TLB)
Virtual memory mapping assisted translation lookaside buffer, which holds virtual-to-physical address translations. This fully-associative, on-chip contains entries, each which maps pair variable-sized pages either Kbytes Mbytes. Joint (JTLB) hold both instruction data addresses, thus also referred joint (JTLB). address translation value tagged with high-order bits virtual address (the number these bits depends upon size page) perprocess identifier. there matching entry TLB, exception occurs software writes entry contents on-chip from page table memory. JTLB entry rewritten selected value either Random Index register.
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Instruction Micro-TLB (ITLB) VR4300 processor two-entry instruction micro-TLB (ITLB) which assists instruction address translation. ITLB operated directly software. Instructions access this while data accesses Joint TLB; miss micro-TLB stalls pipeline until micro-TLB refilled from joint TLB. micro-TLB fully associative, uses least-recentlyused (LRU) replacement algorithm. Each micro-TLB entry maps Kbytes virtual space physical space. This ensures each ITLB entry subset single JTLB entry.
1.5.2 Operating Modes
VR4300 processor three operating modes: User mode Supervisor mode Kernel mode
manner which memory addresses translated mapped depends operating mode CPU; this described Chapter Memory Management System.
Instruction Pipeline
VR4300 5-stage instruction pipeline. This pipeline used floatingpoint operations well integer operations. normal environment, pipeline executes instruction cycle. pipeline VR4300 operates frequency determined depending setting DivMode(1:0)* pins. details, refer Chapter Pipeline.
VR4300 VR4305. VR4310, DivMode(2:0).
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Configuration (Top View)
120-pin plastic mm). µPD30200GD-80-LBB µPD30200GD-100-MBB µPD30200GD-133-MBB µPD30210GD-133-MBB µPD30210GD-167-MBB
Int3 SysAD23 DivMode0 SysAD24 DivMode1 SysCmd4 ColdReset SysCmd3 SysCmd2 EValid Reset SysCmd1 SysCmd0 EReq SysAD25 PMaster SysAD26 SysAD22 SysAD21 SysAD20 VDDP GNDP PLLCap0 PLLCap1 VDDP GNDP (Div Mode2) MasterClcok TClock SyncOut SysAD19 SyncIn SysAD18 SysAD17 Int4
Int2 SysAD27 SysAD28 SysAD29 SysAD30 PValid SysAD31 PReq SysAD0 SysAD1 SysAD2 SysAD3 JTDO SysAD4 JTDI
Remark name µPD30210-xxx
SysAD16 SysAD15 SysAD14 SysAD13 SysAD12 SysAD11 SysAD10 Int0 SysAD9 SysAD8 SysAD7 JTMS SysAD6 SysAD5 JTCK Int1
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NAME ColdReset DivMode (1:0)* EReq EValid (4:0) JTCK JTDI JTDO JTMS MasterClock PLLCap (1:0) PMaster PReq PValid Reset Syncln SyncOut SysAD (31:0) SysCmd (4:0) TClock VDDP GNDP Cold Reset Divide Mode External External Request External Valid Interrupt Request JTAG Clock Input JTAG Data JTAG Data JTAG Command Signal Master Clock Non-maskable Interrupt Request Phase Locked Loop Capacitance Processor Master Processor Request Processor Valid Reset Synchronization Clock Input Synchronization Clock Output System Address/Data System Command Data Transmit Clock Power Supply Ground
DivMode (2:0)
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Functions
2.2.1 System Interface Signals
system interface signals used when VR4300 connected with external device system. Table indicates functions these signals. Table Signal Name SysAD(31:0) Definition System address/data System command/data External request System Interface Signals Function 32-bit address/data bus. Used transmit receive data address between processor external agent. 5-bit bus. Used transfer commands data identifiers between processor external agent. Asserted active when external agent requests processor system interface. Asserted active when processor requests external agent system interface. protocol error detected system interface, this signal oscillated synchronization with MasterClock cycle which multiple SClock. Asserted active when external agent drives valid address valid data onto SysAD bus, valid command/data identifier SysCmd bus. Asserted active when processor drives valid address data onto SysAD bus, valid command/data identifier SysCmd bus. Asserted active when processor master system interface bus. Asserted active when external agent ready accept processor request.
SysCmd(4:0)
EReq
Input
PReq
Processor request
Output
EValid
External agent valid
Input
PValid
Processor valid
Output
PMaster
Processor master External ready
Output Input
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2.2.2 Clock/Control Interface Signals
These interface signals used supply control clocks. Table shows functions signals. Table Signal Name MasterClock Definition Master clock Clock/Control Interface Signals (1/3) Input Function Inputs MasterClock from this pin. internal operating speed determined frequency this signal contents DivMode signals. Outputs transmit/receive clock same frequency MasterClock. Outputs synchronization clock. Connect this SyncIn. Model mutual connection between TClock external agent. Inputs synchronization clock. This pins static internal circuit. This static internal circuit. This connects capacitor adjusting internal circuit processor.
Indicates ratio which internal PClock generated from MasterClock. Normally, frequency TClock same that MasterClock. change value these pins after setting value power application. Otherwise, operation will guaranteed. following indicates relationship between DivMode values frequency ratio each product. Remark maximum value PClock same maximum internal operating frequencies each product regardless frequency ratio. (Refer Ordering Information.) VR4300 µPD30200-100 MasterClock PClock TClock DivMode Frequency ratio Example [MHz] 2:3:2 66.7 66.7 1:2:1 1:3:1 33.3 33.3
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Transmit/receive Output clock Synchronization Output clock output Synchronization clock input Static Static Adjusting Internal operating frequency mode Input Input
SyncIn VDDP GNDP PLLCap(1:0) DivMode
Chapter
Table Signal Name DivMode Definition
Clock/Control Interface Signals (2/3) Input
VR4300 µPD30200-133 DivMode MasterClock PClock TClock
Function
Internal operating frequency mode
Frequency ratio
1:4:1 1:2:1 1:3:1
Example [MHz]
33.3 33.3 66.7 66.7 44.3 44.3
VR4305 µPD30200-80 DivMode MasterClock PClock TClock
Frequency ratio
1:1:1 1:2:1 1:3:1
Example [MHz]
66.7 66.7 66.7
VR4310 µPD30210-133 DivMode MasterClock PClock TClock
Frequency ratio
1:5:1 1:6:1 1:3:1 1:4:1 1:2:1 1:3:1
Example [MHz]
26.7 26.7 22.2 22.2 33.3 33.3 33.3 33.3 33.3 33.3
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Table Signal Name DivMode Definition
Clock/Control Interface Signals (3/3) Input
VR4310 µPD30210-167 DivMode MasterClock PClock TClock
Function
Internal operating frequency mode
Frequency ratio
1:5:1 1:6:1 2:5:2 1:3:1 1:4:1 1:2:1 1:3:1
Example [MHz]
33.3 33.3 27.8 27.8 66.7 66.7 33.3 33.3 33.3 33.3 33.3 33.3
2.2.3 Interrupt Interface Signals
These signals used external device issue interrupt requests VR4300. Table shows functions these signals. Table Signal Name Int(4:0) Definition Interrupt request acknowledge Non-maskable interrupt Interrupt Interface Signals Input Function General purpose interrupt request pins. These pins ORed with bits through internal interrupt register. This accepts non-maskable interrupt signal. ORed with internal interrupt register.
Input
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2.2.4 Joint Test Action Group (JTAG) Interface Signals
These signals interfacing boundary scan JTAG. Table shows functions these signals. Table Signal Name JTDI JTCK Definition JTAG data input JTAG clock input JTAG Interface Signals Input Input Function Inputs data scanned serially. Inputs serial clock. JTDI JTMS read simultaneously rising edge this signal. this signal level when JTAG interface used. Outputs serially scanned data. Inputs high level this serial data input next command JTAG.
JTDO JTMS
JTAG data output JTAG command
Output Input
2.2.5 Initialization Interface Signals
These signals used when external device initializes operation parameters processor. Table shows functions these signals. Table Signal Name ColdReset Definition Cold reset Initialization Interface Signals Input Function Asserted active cold reset. SClock TClock start cycle rising edge this signal. This signal needs asserted active deasserted inactive synchronization with MasterClock signal. Make this active inactive synchronization with MasterClock, keep inactive cold reset. Make this active inactive synchronization with MasterClock soft reset.
Reset
Reset
Input
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Instruction Summary
This chapter overview central processing unit (CPU) instruction set; refer Chapter Instruction Details detailed descriptions individual instructions. Because instruction dependent upon structure coprocessor, refer Chapter Floating-Point Operations Chapter Instruction Details.
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Instruction Formats
Each instruction consists single 32-bit word, aligned word boundary. There three instruction formats-immediate (I-type), jump (Jtype), register (R-type)-as shown Figure 3-1. simplifying instruction format three ways, decoding instructions simplified. Complicated less frequently used operations addressing modes implemented combining more instructions using compiler.
I-Type (Immediate)
J-Type (Jump)
immediate
R-Type (Register)
target
immediate target funct
funct
6-bit operation code 5-bit source register number 5-bit target (source/destination) register number branch condition 16-bit immediate value, branch displacement address displacement 26-bit unconditional branch target address 5-bit destination register number 5-bit shift amount 6-bit function field Figure Instruction Formats
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Support MIPS
Even though VR4300 processor does support multiprocessor operating environment, synchronization support instructions defined MIPS MIPS ISA-the Load Linked Store Conditional instructions-are processed correctly, order maintain compatibility with VR4400 VR4200. load link (LLbit) instruction, cleared ERET, tested instruction. only operation LLbit that implemented reset cache invalidation. Caution Note that load/store instructions this processor executed program order since SYNC instruction handled NOP.
Instruction Classes
instructions classified into classes.
3.2.1 Load/Store Instructions
Load store immediate (I-type) instructions that move data between memory general purpose registers. Only mode that adds 16-bit signed immediate offset base register available addressing mode load/store instructions.
Scheduling Load Delay Slot
load instruction whose loading result cannot used instruction immediately following called delayed load instruction. instruction slot immediately after delayed load instruction called load delay slot. With VR4000 Series, instruction including load destination register described immediately after load instruction. this case, however, interlock count generated equal number necessary cycles. Therefore, although instruction described, recommended schedule load delay slot improve performances VR4300 maintain compatibility with VR3000 Series (for details, refer Chapter Pipeline).
Store Delay Slot
VR4300 processor, store instruction writing data cache keeps data cache busy during both stages. instruction immediately following needs access data cache stage (e.g. load instruction), hardware interlocks. Consequently, scheduling store delay slots desirable performance.
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Table
Number Cycles Load Store Instruction Delay Slot Instruction Load Store PCycles Required
Defining Access Types
Access type size data loaded/stored processor. code load/store instruction determines access type. Figure shows access type data loaded/stored. address used load/store instruction least significant byte address (most significant byte endian address indicating least significant byte little endian), regardless access type byte ordering (endianness). byte ordering doubleword data accessed determined access type low-order bits address, shown Figure 3-2. Combinations access type low-order bits address other than those shown Figure prohibited. combination other than those shown figure used, address error exception occurs. Table lists load/store instructions defined ISA, Table lists instructions extended ISA.
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Access-Type Mnemonic (Value) Doubleword Septibyte Sextibyte Quintibyte Word
Low-Order Address Bits
Bytes Accessed endian Little endian
Byte Access within Doubleword
Triplebyte
Halfword
Byte
Figure
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Table Instruction Load Byte
Load/Store Instructions (1/2)
base offset
Format Description
offset (base) Generates address adding sign-extended offset contents register base. Sign-extends contents byte specified address loads result register offset (base) Generates address adding sign-extended offset contents register base. Zero-extends contents byte specified address loads result register offset (base) Generates address adding sign-extended offset contents register base. Sign-extends contents halfword specified address loads result register offset (base) Generates address adding sign-extended offset contents register base Zero-extends contents halfword specified address loads result register offset (base) Generates address adding sign-extended offset contents register base. Sign-extends contents word specified address 64-bit mode) loads result register offset (base) Generates address adding sign-extended offset contents register base. Shifts word specified address left, that byte specified address leftmost position word. Sign-extends 64bit mode), merges result shift contents register loads result register offset (base) Generates address adding sign-extended offset contents register base. Shifts word specified address right, that byte specified address rightmost position word. Sign-extends 64bit mode), merges result shift contents register loads result register
Load Byte Unsigned
Load Halfword
Load Halfword Unsigned
Load Word
Load Word Left
Load Word Right
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Table Instruction Store Byte
Load/Store Instructions (2/2)
base offset
Format Description
offset (base) Generates address adding sign-extended offset contents register base. Stores contents low-order byte register memory specified address. offset (base) Generates address adding sign-extended offset contents register base. Stores contents low-order halfword register memory specified address. offset (base) Generates address adding sign-extended offset contents register base. Stores contents low-order word register memory specified address. offset (base) Generates address adding sign-extended offset contents register base. Shifts contents register right that leftmost byte word position byte specified address. Stores result shift lower portion word memory. offset (base) Generates address adding sign-extended offset contents register base. Shifts contents register left that rightmost byte word position byte specified address. Stores result shift higher portion word memory.
Store Halfword
Store Word
Store Word Left
Store Word Right
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Table Instruction
Load/Store Instructions (Extended ISA) (1/2)
base offset
Format Description
Load Doubleword offset (base) Generates address adding sign-extended offset contents register base. Loads contents doubleword specified address register Load Doubleword offset (base) Left Generates address adding sign-extended offset contents register base. Shifts doubleword specified address left that byte specified address leftmost position doubleword. Merges result shift contents register loads result register Load Doubleword offset (base) Right Generates address adding sign-extended offset contents register base. Shifts doubleword specified address right that byte specified address rightmost position doubleword. Merges result shift contents register loads result register Load Linked offset (base) Generates address adding sign-extended offset contents register base. Loads contents word specified address register sets offset (base) Generates address adding sign-extended offset contents register base. Loads contents doubleword specified address register sets offset (base) Generates address adding sign-extended offset contents register base. Zero-extends contents word specified address, loads result register
Load Linked Doubleword
Load Word Unsigned
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Table Instruction Store Conditional
Load/Store Instructions (Extended ISA) (2/2)
base offset
Format Description
offset (base) Generates address adding sign-extended offset contents register base. stores contents low-order word register memory specified address, sets register does store contents word, clears register offset (base) Generates address adding sign-extended offset contents register base. stores contents register memory specified address, sets register does store contents register, clears register
Store Conditional Doubleword
Store Doubleword offset (base) Generates address adding sign-extended offset contents register base. Stores contents register memory specified address. Store Doubleword offset (base) Left Generates address adding sign-extended offset contents register base. Shifts contents register right that leftmost byte doubleword position byte specified address. Stores result shift lower portion doubleword memory. Store Doubleword Right offset (base) Generates address adding sign-extended offset contents register base. Shifts contents register left that rightmost byte doubleword position byte specified address. Stores result shift higher portion doubleword memory.
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3.2.2 Computational Instructions
Computational instructions executes arithmetic operations, multiply/divide, logical operations, shift operations values registers. These instructions classified into types: R-type I-type. R-type instructions uses registers both source, I-type instructions uses immediate value sources. operation instructions divided into following four types classification operation. immediate instructions (Refer Tables 3-5.) 3-operand type instructions (Refer Tables 3-7.) Shift instructions (Refer Tables 3-9.) Multiply/Divide instructions (Refer Tables 3-10 3-11.) compatibility data necessary 64-bit 32-bit modes, 32-bit operands must correctly sign-extended. Otherwise, 32-bit value result operation will meaningless.
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Instruction Summary
Table Instruction Immediate
Immediate Instructions
immediate
Format Description
ADDI immediate Sign-extends 16-bit immediate adds register Stores 32-bit result register (sign-extends result 64-bit mode). Generates exception complement integer overflow occurs. ADDIU immediate Sign-extends 16-bit immediate adds register Stores 32-bit result register (sign-extends result 64-bit mode). Does generate exception even integer overflow occurs. SLTI immediate Sign-extends 16-bit immediate compares with register signed integer. less than immediate, stores register otherwise, stores register SLTIU immediate Sign-extends 16-bit immediate compares with register unsigned integer. less than immediate, stores register otherwise, stores register ANDI immediate Zero-extends 16-bit immediate, ANDs with register stores result register immediate Zero-extends 16-bit immediate, with register stores result register XORI immediate Zero-extends 16-bit immediate, exclusive-ORs with register stores result register immediate Shifts 16-bit immediate bits left, clears low-order bits word Stores result register sign-extending result 64-bit mode).
Immediate Unsigned
Less Than Immediate
Less Than Immediate Unsigned Immediate
Immediate
Exclusive Immediate Load Upper Immediate
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Table Instruction Doubleword Immediate
Immediate Instruction (Extended ISA)
immediate
Format Description
DADDI immediate Sign-extends 16-bit immediate bits, adds register Stores 64-bit result register Generates exception integer overflow occurs. DADDIU immediate Sign-extends 16-bit immediate bits, adds register Stores 64-bit result register Does generate exception even integer overflow occurs.
Doubleword Immediate Unsigned
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Table Instruction
Three-Operand Type Instruction
funct
Format Description
Adds contents register stores (sign-extends 64-bit mode) 32-bit result register Generates exception integer overflow occurs. ADDU Adds contents register stores (sign-extends 64-bit mode) 32-bit result register Does generate exception even integer overflow occurs. Subtracts contents register from register stores (sign-extends 64-bit mode) result register Generates exception integer overflow occurs. SUBU Subtracts contents register from register stores (sign-extends 64-bit mode) 32-bit result register Does generate exception even integer overflow occurs. Compares contents registers signed integers. contents register less than those stores register otherwise, stores SLTU Compares contents registers unsigned integers. contents register less than those stores register otherwise, stores ANDs contents registers units, stores result register contents registers units, stores result register Exclusive-ORs contents registers units, stores result register NORs contents registers units, stores result register
Unsigned
Subtract
Subtract Unsigned
Less Than
Less Than Unsigned
Exclusive
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Table Instruction Doubleword
Three-Operand Type Instructions (Extended ISA)
funct
Format Description
DADD Adds contents registers stores 64-bit result register Generates exception integer overflow occurs. DADDU Adds contents registers stores 64-bit result register Does generate exception even integer overflow occurs. DSUB Subtracts contents register from register stores 64-bit result register Generates exception integer overflow occurs.
Doubleword Unsigned
Doubleword Subtract
Doubleword DSUBU Subtract Unsigned Subtracts contents register from register stores 64-bit result register Does generate exception even integer overflow occurs.
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Instruction Summary
Table Instruction Shift Left Logical
Shift Instructions
funct
Format Description
Shifts contents register bits left, inserts loworder bits. Sign-extends 64-bit mode) 32-bit result stores register Shifts contents register bits right, inserts highorder bits. Sign-extends 64-bit mode) 32-bit result stores register Shifts contents register bits right, sign-extends highorder bits. Sign-extends 64-bit mode) 32-bit result stores register SLLV Shifts contents register left inserts low-order bits. number bits which register contents shifted specified low-order bits register Sign-extends 64-bit mode) result stores register SRLV Shifts contents register right, inserts high-order bits. number bits which register contents shifted specified low-order bits register Sign-extends 64-bit mode) 32-bit result stores register SRAV Shifts contents register right sign-extends high-order bits. number bits bylow-order register contents shifted specified low-order bits register Sign-extends 64-bit mode) 32-bit result stores register
Shift Right Logical
Shift Right Arithmetic
Shift Left Logical Variable
Shift Right Logical Variable
Shift Right Arithmetic Variable
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Table Instruction Doubleword Shift Left Logical
Shift Instructions (Extended ISA) (1/2)
funct
Format Description
DSLL Shifts contents register bits left, inserts loworder bits. Stores 64-bit result register DSRL Shifts contents register bits right, inserts highorder bits. Stores 64-bit result register DSRA Shifts contents register bits right, sign-extends highorder bits. Stores 64-bit result register DSLLV Shifts contents register left, inserts low-order bits. number bits which register contents shifted specified low-order bits register Stores 64-bit result stores register DSRLV Shifts contents register right, inserts higher bits. number bits which register contents shifted specified low-order bits register Sign-extends 64-bit result stores register DSRAV Shifts contents register right, sign-extends high-order bits. number bits which register contents shifted specified low-order bits register Sign-extends 64-bit result stores register DSLL32 Shifts contents register 32+sa bits left, inserts loworder bits. Stores 64-bit result register DSRL32 Shifts contents register 32+sa bits right, inserts high-order bits. Stores 64-bit result register
Doubleword Shift Right Logical
Doubleword Shift Right Arithmetic
Doubleword Shift Left Logical Variable
Doubleword Shift Right Logical Variable
Doubleword Shift Right Arithmetic Variable
Doubleword Shift Left Logical
Doubleword shift Right Logical
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Table Instruction Doubleword Shift Right Arithmetic
Shift Instructions (Extended ISA) (2/2)
funct
Format Description
DSRA32 Shifts contents register 32+sa bits right, sign-extends high-order bits. Stores 64-bit result register Table 3-10 Multiply/Divide Instructions
funct
Instruction Multiply
Format Description
MULT Multiplies contents register contents register 32-bit signed integer. Sign-extends 64-bit mode) stores 64-bit result special registers MULTU Multiplies contents register contents register 32-bit unsigned integer. Sign-extends 64-bit mode) stores 64-bit result special registers Divides contents register contents register operand treated 32-bit signed integer. Sign-extends 64-bit mode) stores 32-bit quotient special register 32-bit remainder special register DIVU Divides contents register contents register operand treated 32-bit unsigned integer. Sign-extends 64-bit mode) stores 32-bit quotient special register 32-bit remainder special register MFHI Transfers contents special register register MFLO Transfers contents special register register MTHI Transfers contents register special register MTLO Transfers contents register special register
Multiply Unsigned
Divide
Divide Unsigned
Move From Move From Move Move
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Table 3-11 Instruction Doubleword Multiply
Multiply/Divide Instructions (Extended ISA)
funct
Format Description
DMULT Multiplies contents register contents register signed integer. Stores 128-bit result special registers DMULTU Multiplies contents register contents register unsigned integer. Stores 128-bit result special registers DDIV Divides contents register contents register operand treated signed integer. Stores 64-bit quotient special register 64-bit remainder special register DDIVU Divides contents register contents register operand treated unsigned integer. Stores 64-bit quotient special register 64-bit remainder special register
Doubleword Multiply Unsigned Doubleword Divide
Doubleword Divide Unsigned
When integer multiply divide instruction executed, VR4300 stalls entire pipeline. number processor cycles (PCycles) stalled this time shown below. Table 3-12
Instruction Number required cycles MULT
Number Cycles Stalled Multiply/Divide Instruction
DIVU DMULT DMULTU DDIV DDIVU
MULTU
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3.2.3 Jump/Branch Instructions
jump branch instructions change flow program. jump branch instructions generate delay slot. instruction immediately following jump branch instruction (i.e., instruction delay slot) executed while first instruction destination fetched from memory. Instructions involving link, such BLTZAL, store return address register r31. Table 3-13 Number Delay Slot Cycles Jump/Branch Instruction Instruction Branch Jump Number Required Cycles
Outline Jump Instruction
Subroutine call described high-level language usually uses instruction. instructions J-type instructions. instruction this type shifts 26-bit target address bits left combines with high-order bits current program counter generate 64-bit absolute address. return, dispatch, jump between pages, JALR instruction usually used. Both these instructions R-type references 64-bit byte address general purpose register. details, refer Chapter Instruction Details.
Outline Branch Instruction
branch instruction signed 16-bit offset relative program counter. Instructions involving link, such BLTZAL, store return address register r31. Table 3-14 lists jump instructions, Table 3-15 shows branch instructions. Table 3-16 lists branch instructions extended ISA.
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Table 3-14 Instruction Jump
Jump Instructions
target
Format Description
target Shifts 26-bit target address bits left, jumps address coupled with high-order bits delayed instruction. target Shifts 26-bit target address bits left, jumps address coupled with high-order bits delayed instruction. Stores address instruction following delay slot (link register). Format Description
Jump Link
Instruction Jump Register Jump Link Register
funct
Jumps address register delayed instruction. JALR Jumps address register delayed instruction. Stores address instruction following delay slot register following common limits applied Tables 3-15 3-16.
Branch Address
branch addresses branch instructions calculated adding 16bit offset (signed bits shifted bits left) address instruction delay slot. branch instructions generate delay slot.
Operation during Branch (Table 3-16)
branch condition branch likely instruction satisfied, instruction delay slot invalidated. instruction delay slot unconditionally executed other branch instructions. Remark instruction branch destination fetched stage branch instruction. Comparison branch calculation target address executed phase stage phase stage branch instruction. cycle branch delay slot defined architecture necessary. cycle delay slot also necessary jump instruction. branch condition branch likely instruction satisfied, instruction branch slot invalidated.
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following symbols instruction format Table 3-15 through Table 3-21 special. REGIMM cofun code operation code operation identifier operation code branch condition identifier coprocessor function area operation code Branch Instructions
offset funct
Table 3-15 Instruction Branch Equal Branch Equal Branch Less Than Equal Zero Branch Greater Than Zero Instruction Branch Less Than Zero Branch Greater Than Equal Zero Branch Less Than Zero Link Branch Greater Than Equal Zero Link
Format Description
offset Branches branch address register equals offset Branches branch address register equal BLEZ offset Branches branch address register less than BGTZ offset Branches branch address register greater than
Format Description
REGIMM
offset
funct
BLTZ offset Branches branch address register less than BGEZ offset Branches branch address register greater than BLTZAL offset Stores address instruction following delay slot register (link register), branches branch address register less than BGEZAL offset Stores address instruction following delay slot register (link register) branches branch address register greater than
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Table 3-16 Instruction Branch Equal Likely Branch Equal Likely
Branch Instructions (Extended ISA)
offset funct
Format Description
BEQL offset Branches branch address registers equal. branch condition satisfied, instruction branch delay slot discarded. BNEL offset Branches branch address registers equal. branch condition satisfied, instruction branch delay slot discarded. BLEZL offset Branches branch address register less than branch condition satisfied, instruction branch delay slot discarded. BGTZL offset Branches branch address register greater than branch condition satisfied, instruction branch delay slot discarded. Format Description
Branch Less Than Equal Zero Likely Branch Greater Than Zero Likely Instruction Branch Less Than Zero Likely Branch Greater Than Equal Zero Likely Branch Less Than Zero Link Likely
REGIMM
offset
funct
BLTZL offset Branches branch address register less than branch condition satisfied, instruction branch delay slot discarded. BGEZL offset Branches branch address register greater than branch condition satisfied, instruction branch delay slot discarded. BLTZALL offset Stores address instruction following delay slot register (link register). Branches branch address register less than branch condition satisfied, instruction branch delay slot discarded. BGEZALL offset Stores address instruction following delay slot register (link register). Branches branch address register greater than branch condition satisfied, instruction branch delay slot discarded.
Branch Greater Than Equal Zero Link Likely
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3.2.4 Special Instructions
special instructions generate exception software. instruction type R-type (Syscall, Break). trap instructions invalid with VR3000 Series. other instructions valid with Series. Table 3-17 Instruction Synchronize Special Instructions
SPECIAL
Format Description
funct
SYNC Completes load/store instruction currently pipeline before load/store instruction executed. SYSCALL Generates system call exception transfers control exception processing program. BREAK Generates breakpoint exception transfers control exception processing program. Table 3-18 Special Instructions (Extended ISA) (1/2)
SPECIAL
System Call
Breakpoint
Instruction Trap Greater Than Equal Trap Greater Than Equal Unsigned Trap Less Than
Format Description
funct
Compares registers signed integers. register greater than generates exception. TGEU Compares registers unsigned integers. register greater than generates exception. Compares registers signed integers. register less than generates exception. TLTU Compares registers unsigned integers. register less than generates exception. Generates exception registers equal. Generates exception registers equal.
Trap Less Than Unsigned Trap Equal Trap Equal
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Table 3-18 Instruction Trap Greater Than Equal Immediate Trap Greater Than Equal Immediate Unsigned Trap Less Than Immediate
Special Instructions (Extended ISA) (2/2)
REGIMM
Format Description
immediate funct
TGEI immediate Compares contents register with 16-bit sign-extended immediate signed integer. contents greater than immediate, generates exception. TGEIU immediate Compares contents register with 16-bit zero-extended immediate unsigned integer. contents greater than immediate, generates exception. TLTI immediate Compares contents register with 16-bit sign-extended immediate signed integer. contents less than immediate, generates exception. TLTIU immediate Compares contents register with 16-bit zero-extended immediate unsigned integer. contents less than immediate, generates exception. TEQI immediate Generates exception contents register equal immediate. TNEI immediate Generates exception contents register equal immediate.
Trap Less Than Immediate Unsigned Trap Equal Immediate Trap Equal Immediate
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3.2.5 Coprocessor Instructions
coprocessor instructions used operate each coprocessor. coprocessor load store instructions I-type. format operation instruction each coprocessor differs. Table 3-19 shows coprocessor instructions valid Series. Table 3-20 lists coprocessor instructions valid only with VR4000 which defined extended ISA. Table 3-19 Instruction Load Word Coprocessor Coprocessor Instructions (1/2)
base offset funct
Format Description
LWCz offset (base) Sign-extends adds offset register base generate address. Loads contents word specified address general purpose register coprocessor SWCz offset (base) Sign-extends adds offset register base generate address. Stores contents general purpose register coprocessor memory position specified address. Format Description COPz
Store Word From Coprocessor
Instruction Move Coprocessor Move From Coprocessor Move Control Coprocessor Move Control From Coprocessor
funct
MTCz Transfers contents register general purpose register coprocessor MFCz Transfers contents general purpose register coprocessor register CTCz Transfers contents register coprocessor control register coprocessor CFCz Transfers contents coprocessor control register coprocessor register Format Description COPz
Instruction Coprocessor Operation
cofun
COPz cofun Coprocessor executes operation defined each coprocessor. status changed operation coprocessor.
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Table 3-19 Instruction Branch Coprocessor True
Coprocessor Instructions (2/2)
offset funct
Format Description COPz
BCzT offset Shifts 16-bit offset bits left sign-extends bits. Adds result address instruction delay slot calculate branch address. condition signal coprocessor true, branches branch address, delayed instruction. BCzF offset Shifts 16-bit offset bits left sign-extends bits. Adds result address instruction delay slot calculate branch address. condition signal coprocessor false, branches branch address, delayed instruction. Table 3-20 Coprocessor Instructions (Extended ISA) (1/2)
Branch Coprocessor False
Instruction Doubleword Move Coprocessor Doubleword Move From Coprocessor Instruction Load Doubleword Coprocessor Store Doubleword From Coprocessor
Format Description COPz
DMTCz Transfers contents general purpose register general purpose register coprocessor DMFCz Transfers contents general purpose register coprocessor general purpose register CPU. Format Description
base
offset
LDCz offset (base) Sign-extends adds offset register base generate address. Loads contents doubleword specified address general purpose register rt+1 coprocessor SDCz offset (base) Sign-extends adds offset register base generate address. Stores contents doubleword general purpose register rt+1 coprocessor memory position specified address.
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Table 3-20 Instruction Branch Coprocessor True Likely
Coprocessor Instructions (Extended ISA) (2/2)
offset funct
Format Description COPz
BCzTL offset Shifts 16-bit offset bits left sign-extends Adds result address instruction delay slot calculate branch address. condition signal coprocessor true, branches branch address, delayed instruction. branch condition satisfied, instruction branch delay slot discarded. BCzFL offset Shifts 16-bit offset bits left sign-extends Adds result address instruction delay slot calculate branch address. condition signal coprocessor false, branches branch address, delayed instruction. branch condition satisfied, instruction branch delay slot discarded.
Branch Coprocessor False Likely
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3.2.6 System Control Coprocessor (CP0) Instructions
system control coprocessor (CP0) instructions execute operations register control memory processor perform exception processing. Table 3-21 Instruction Move System Control Coprocessor Move From System Control Coprocessor Doubleword Move System Control Coprocessor Doubleword Move From System Control Coprocessor Instruction Read Indexed Entry Write Indexed Entry Write Random Entry Probe Matching Entry Return From Exception System Control Coprocessor (CP0) Instruction (1/2)
funct
Format Description COP0
MTC0 Loads contents word general purpose register general purpose register CP0. MFC0 Loads contents word general purpose register general purpose register CPU. DMTC0 Loads contents doubleword general purpose register general purpose register CP0. DMFC0 Loads contents doubleword general purpose register general purpose register CPU.
Format Description COP0
funct
TLBR Loads entry indicated index register entry entry Lo0, entry Lo1, page mask registers. TLBWI Loads contents entry entry Lo0, entry Lo1, page mask registers entry indicated index register. TLBWR Loads contents entry entry Lo0, entry Lo1, page mask registers entry indicated random register. TLBP Loads address entry coinciding with contents entry register index register. ERET Returns from exception, interrupt, error trap.
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Table 3-21 Instruction Cache Operation
System Control Coprocessor (CP0) Instructions (2/2)
CACHE
Format Description
base
offset
funct
Cache offset (base) Sign-extends 16-bit offset bits adds register base generate virtual address. virtual address converted into physical address using TLB, cache operation indicated 5-bit code executed that address.
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[MEMO]
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Pipeline
This chapter describes operation VR4300 processor pipeline.
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General
VR4300 uses 5-stage pipeline. pipeline usually controlled pipeline clock that determined value DivMode(1:0)* pins. This pipeline clock called PClock cycle called PCycle. Each stage pipeline executed PCycle. PCycle stages, shown Figure 4-1. Therefore, least PCycles required execute instruction. necessary data cache must fetched from main memory, more cycles necessary. When pipeline flows smoothly, five instructions executed simultaneously. VR4300 VR4305. VR4310, DivMode(2:0).
MasterClock Cycle
PClock Phase Cycle
PCycle
Figure five pipeline stages are:
Pipeline Stages
Instruction Cache Fetch Register Fetch Execution Data Cache Fetch Write Back
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Pipeline
Figure outlines pipeline. horizontal rows this figure indicate execution processes instructions, vertical columns indicate five processes executed same time. (5-Deep)
PCycle
Current Cycle
Figure
Instruction Execution Pipeline
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4.1.1 Pipeline Operations
Figure shows operations that occur during each pipeline stage; Table describes these pipeline activities. PCycle
PClock Phase Cycle
Instr Fetch
ITLB IDEC BCMP
Computational
Load/Store
DTLB
Branch
Figure
Pipeline Operations
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Table Cycle
Description Pipeline Showing Stage Which Operations Commence Mnemonic ITLB IDEC BCMP Instruction Cache Fetch Instruction micro-TLB read Instruction cache Check Register File Read Instruction DECode Instruction Virtual Address calculation Branch Compare Arithmetic Logic operation Data Virtual Address calculation Data Cache Read Data joint-TLB read Load data Alignment Data cache Check Data Cache Write Register File Write Descriptions
Begins During this Phase
DTLB
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Branch Delay
pipeline VR4300 generates branch delay cycle following cases: When target address calculated with jump instruction When branch condition branch instruction satisfied target address calculated
instruction address generated stage jump/branch instruction cannot used until stage instruction executed after next instruction. Figure illustrates branch delay location branch delay slot.
Branch
Single branch delay instruction
(Branch Delay Slot)
Target Branch Delay
Figure
Branch Delay
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Pipeline
Load Delay
load instruction that does allow result used instruction immediately following called delayed load instruction. instruction slot immediately following this delayed load instruction referred load delay slot. VR4300 processor, instruction immediately following load instruction contents loaded register, however such cases hardware interlocks insert additional delay cycles. Consequently, scheduling load delay slots desirable, both performance VR-Series processor compatibility.
Pipeline Operation
operation pipeline illustrated following examples that describe typical instructions executed. instructions described are: ADD, JALR, BEQ, TLT, Each instruction taken through pipeline operations that occur each relevant stage described. Floating-point instructions executed pipeline same manner multicycle integer instructions.
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Instruction rd,rs,rt
stage
phase stage, fourteen low-order bits virtual address used address instruction cache. high-order bits this virtual address select four instruction cache banks, remaining bits address selected bank. ITLB selects page. phase stage, cache index compared with page frame number from ITLB cache data read out. cache hit/miss signal valid late phase stage, virtual incremented that next instruction fetched. During phase fields 2-port register file accessed register data valid register file output. same time, bypass multiplexers select inputs from either DC-stage output addition register file output, depending need operand bypass.
stage
stage
controls operation. operands flow into inputs, operation started. result operation latched into output latch during phase This stage this instruction. data from output stage (the ALU) moved into output latch During phase latch feeds data inputs register file, which addressed field. file write strobe enabled. phase data written into register file.
stage
stage
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Pipeline
PClock Phase Cycle
ITLB
IDEC
Figure
Instruction Pipeline Operations
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Jump Link Register Instruction JALR rd,rs
stage stage stage
Same stage instruction. During phase stage, register addressed field read file. During phase stage, value register clocked into virtual latch. This value used phase fetch next instruction. value virtual incremented during stage incremented again produce link address PC+8 where address JALR instruction. resulting value which program will eventually return from jump destination. This value placed Link output latch Instruction Address unit.
stage stage
PC+8 value moved from Link output latch output latch pipeline stage. Refer instruction. Note that value explicitly provided then register used default. explicitly specified, cannot same register addressed result executing such instruction undefined.
PClock Phase Cycle
ITLB
IDEC
Figure
Jump Link Register Instruction Pipeline Operations
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Branch Equal Instruction rs,rt,offset
stage stage
Same stage instruction. During phase register file addressed with fields contents these registers placed register file output latch. During phase check performed determine each corresponding position these operands equal values. they equal, PC+target, where target sign-extended offset field. they equal, PC+4. next resulting from branch comparison valid beginning phase instruction fetch.
stage
stage stage
This stage this instruction. This stage this instruction.
PClock Phase Cycle
ITLB
IDEC BCMP
Figure
Branch Equal Instruction Pipeline Operations
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Trap Less Than Instruction rs,rt
stage stage stage
Same stage instruction. Same stage instruction. During phase bypass multiplexers select inputs from RF-, DC-stage output latch, depending need operand bypass. controls operation. operands flow into inputs, operation started. result operation latched into output latch during phase
stage
sign bits operands output latch checked determine less than condition true. this condition true, Trap Exception occurs. This, with pipeline exceptions, implies 2-cycle stall. register loaded with value exception vector instructions following previous pipeline stages killed. exception code ExCode field cause register less than condition stage. value this instruction stored register updated appropriately according contents Status register. less than condition stage, activity occurs stage.
stage
PClock Phase Cycle
ITLB
IDEC
Figure
Trap Less Than Instruction Pipeline Operations
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Load Word Instruction rt,offset(base)
stage stage stage
Same stage instruction. Same stage instruction. Note that base field same position field. Refer stage instruction. inputs come from GPR[base] through bypass multiplexer from sign-extended offset field. result operation that latched into output latch phase represents effective virtual address operand (DVA). data cache accessed parallel with TLB, cache field compared with Page Frame Number (PFN) field entry. After passing through load aligner, aligned data placed output latch during phase During phase cache read data written into file addressed field.
stage
stage
PClock Phase Cycle
DTLB
ITLB
IDEC
Figure
Load Word Instruction Pipeline Operations
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Store Word Instruction rt,offset(base)
stage stage stage
Same stage instruction. Same stage instruction. Refer instruction calculation effective address. From output latch GPR[rt] sent through bypass multiplexer into main shifter, where shifter performs byte-alignment operation operand. results shift operations latched output latches during phase Refer instruction description cache access. Additionally, merged data from load aligner moved into store data output latch during phase there cache hit, content store data output latch written into data cache appropriate word location. Note that store instructions data cache consecutive PCycles. following instruction requires data cache, pipeline stalled PCycle complete writing aligned store data.
stage
stage
PClock Phase Cycle
DTLB
ITLB
IDEC
Figure 4-10
Store Word Instruction Pipeline Operations
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Interlock Exception Handling
Smooth pipeline flow interrupted when cache misses exceptions occur, when data dependencies detected. Interruptions handled using hardware, such cache misses, referred interlocks, while those that handled using software called exceptions. shown Figure 4-11, interlock exception conditions collectively referred faults.
Faults
Software
Hardware
Exceptions
Interlocks
Abort
Stalls
Figure 4-11
Interlocks, Exceptions, Faults
each cycle, exception interlock conditions checked active instructions. Because each exception interlock condition corresponds particular pipeline stage, condition traced back particular instruction exception/ interlock stage, shown Figure 4-12. instance, Interlock raised execution (EX) stage. Tables describe pipeline interlocks exceptions listed Figure 4-12.
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Clock PCycle
State
Pipeline Stage
IICB IADE ITLB
SYSC BRPT RSVD
OVFL TRAP DADE DTLB INTR
CP0I
Interlock
Exceptions
Remark Figure 4-12
conditions exceptions shown starting from exception with highest priority.
Correspondence Pipeline Stage Interlock Exception Condition
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Table Exception IADE ITLB SYSC BRPT RSVD OVFL TRAP DADE DTLB INTR
Description Pipeline Exceptions Description
Instruction Address Error Exception Instruction Exception Instruction Error Exception SYSCALL Instruction Exception Breakpoint Instruction Exception Coprocessor Unusable Exception Reserved Instruction Exception External Reset Exception External Exception Integer Overflow Exception TRAP Instruction Exception Floating-point Exception Data Address Error Exception Data Exception Reference Watch Address Exception Interrupt Exception Data Error Exception Table Description Pipeline Interlocks Description Instruction Miss Instruction Cache Busy Load Interlock Multi-cycle Interlock Data Cache Miss Data Cache Busy Cache Bypass Interlock
Interlock IICB CP0I
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Pipeline Interlocks Exceptions
When interlock exception condition arises, pipeline flow interrupted. Depending upon whether condition interlock exception, following occurs: interlock condition arises, pipeline remains stalled until interlock corrected hardware. exception occurs, exception-causing instruction pipelines that follow aborted, exception resolved software, pipeline restarted reloaded.
Pipeline interlocks pipeline exceptions described following section. exceptions themselves described Chapter Exception Processing. Bypassing, which allows data conditions produced stages pipeline made available stage next cycle, also described this section.
4.6.1 Pipeline Interlocks
When interlock condition occurs, pipeline stalls remains stalled until interlock corrected. Should pipeline stall requests from different stages arise simultaneously, Pipeline Control Unit prioritizes stall requests. instance, stall request from stage always allowed resolved before simultaneous RF-stage stall request, since both require same resource (TLB, memory) resolved. stage allowed stall order complete multicycle instruction long there load dependency between itself (the stage) stage. Interlock conditions each pipeline stage shown Figure 4-12 described Table 4-3. remainder this section describes detail following pipeline interlocks: Instruction Miss (ITM) Instruction Cache Busy (ICB) Load Interlock (LDI) Multicycle Instruction Interlock (MCI) Data Cache Miss (DCM) Data Cache Busy (DCB) Cache Operation (COp) Bypass Interlock (CP0I)
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4.6.2 Instruction Miss (ITM)
pipeline stall Instruction Miss occurs when virtual address next instruction fetched found instruction micro-TLB (ITLB). pipeline stalls when micro-TLB miss detected stage, whereupon pipeline controller notifies micro-TLB proceed servicing stall. pipeline starts running again when micro-TLB been updated from JTLB. miss penalty PCycles incurred when micro-TLB updated from JTLB. virtual address also misses JTLB, exception taken which overrides stall allow handler update JTLB. Once update completed, instruction fetch re-executed. This initiates repeat Istall until micro-TLB updated from JTLB, which just updated exception handler.
Stall I
Stall
Stall
I
ITLB Access JTLB ITLB Update Miss
Figure 4-13
Instruction Miss Interlock
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4.6.3 Instruction Cache Busy (ICB)
pipeline stall Instruction Cache Busy interlock occurs when next instruction found instruction cache, cache cannot service Instruction Fetch. pipeline stalls when instruction cache miss detected stage. After detecting stall, pipeline controller notifies instruction cache proceed servicing stall. pipeline begins running again after entire cache line been written into instruction cache. When instruction cache busy with CACHE instruction Instruction Fetch cannot serviced, Cache Operation (COp) interlock taken, ICB.
Stall
Stall
I-cache Miss
Refill I-cache
I-cache Update
Figure 4-14
Example Instruction Cache Busy Interlock
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Pipeline
4.6.4 Multicycle Instruction Interlock (MCI)
pipeline stall Multicycle Interlock occurs when instruction with execution latency more than pipeline clock enters stage. pipeline begins running again during multicycle instruction's last clock operation stage.
Stall Mult
Stall
Read MultHi
Read MultLo
Multiple Cycle Instruction Stall
Figure 4-15
Example Multicycle Instruction Interlock
User's Manual U10504EJ6V0UM00
Chapter
4.6.5 Load Interlock (LDI)
pipeline stall Load Interlock occurs when data fetched load instruction required next immediate instruction. pipeline stalls when load-use instruction (the instruction using load data), enters stage. pipeline begins running again when clock after target load read from data cache stage "Load instruction Figure 416). Load Interlock normally only active PClock cycle when load instruction stage load-use instruction stage. data returned from data cache stage input into stage, using bypass multiplexers. data cache misses, Data Cache Busy interlock extends stall until data cache been updated with missing data. still active during this time extends stall clock beyond Data Cache Interlock while data bypassed from data cache into stage. This case illustrated Figure 4-17.
Stall
Load
I-cache
Load
I-cache
Bypass
detected
I-cache
I-cache
I-cache
Figure 4-16
Example Load Interlock
User's Manual U10504EJ6V0UM00
Pipeline
4.6.6 Data Cache Miss (DCM)
data cache miss occurs stage, pipeline stalls PCycle which miss detected. pipeline stalls regardless whether load store instruction executed. data cache busy (explained next) continues stalling until cache line read. When requested word data been read from cache, pipeline begins running again. Figure 4-17 illustrates DCM.
4.6.7 Data Cache Busy (DCB)
pipeline stall data cache being busy occur following situations: instruction immediately after store instruction requires data cache then pipeline stalled stage while store writes data cache during stage. cache store pipeline only stalls PClock while data written data cache. cache store miss pipeline stalls with store stage until cache line been updated. Once line been updated, pipeline restarts moves store instruction into stage. instruction following "store" (i.e. instruction currently stage) also requires access data cache, pipeline will then stall PCycle while store data being written cache. When miss occurs load, data cache signals busy while fetches missed data word from external memory. Refer Figure 4-17.
pipeline begins running again load when missed data word available from data cache.
User's Manual U10504EJ6V0UM00
Chapter
Stall
Stall
Stall
Load
I-cache
Bypass
detected
I-cache
Load
Bypass
D-cache Miss detected
D-cache Miss
Update D-cache
Figure 4-17
Example Data Cache Miss Followed Load Interlock
4.6.8 CACHE Operation (COp)
pipeline stall CACHE operation occur following situations: When instruction cache operation instruction enters stage, instruction cache operation continues serviced while pipeline stalls. pipeline begins running again when instruction cache operation complete, allowing next instruction fetch proceed. When data cache operation instruction requiring operation PCycles data cache entered stage.
User's Manual U10504EJ6V0UM00
Pipeline
4.6.9 Coprocessor Bypass Interlock (CP0I)
pipeline stall Bypass Interlock occurs when instruction which caused exception reaches stage subsequent instruction stage requests read register. This interlock causes pipeline stall PCycle allow register written stage before allowing register read stage.
Stall
Instruction which causes exception
stage completes first phase stage
CP01 CP01
Load
Figure 4-18
Example Coprocessor Bypass Interlock (CP0I)
User's Manual U10504EJ6V0UM00
Chapter
Pipeline Exceptions
When pipeline exception condition occurs, pipeline stalls PCycles instruction causing exception well those that follow pipeline aborted. Accordingly, stall conditions later exception conditions from aborted instruction inhibited; there benefit servicing stalls aborted instruction. After aborting instructions, execution starts predefined exception vector. System Control Coprocessor (CP0) registers loaded with information that identifies type exception well auxiliary information such virtual address which translation exceptions occur. Exception conditions each pipeline stage shown Figure 4-12 described Table 4-2. Exceptions split into groups: those that occur independently instruction execution (Reset, NMI, interrupt exceptions) those exceptions that result from execution particular instruction instruction-dependent exception). This category includes other exceptions.
Exceptions logically precise.
4.7.1 Instruction-Independent Exceptions (Reset, NMI, Interrupt)
Reset, interrupt exceptions identified processed follows: Reset exception highest priority possible exceptions; when Reset exception asserted, instructions pipeline stages except aborted regardless interlocks other exceptions that active. interrupt exception requests accepted only previous PCycle cycle. When interrupt exception occurs, pipeline stages except aborted.
User's Manual U10504EJ6V0UM00
Pipeline
4.7.2 Instruction-Dependent Exceptions
Prioritizing between instruction-dependent exceptions interlocks made according these rules: exception re

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