III. FAILURE MECHANISMS SEMICONDUCTOR DEVICES INTRODUCTION FAILUR
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FAILURE MECHANISMS SEMICONDUCTOR DEVICES
III. FAILURE MECHANISMS SEMICONDUCTOR DEVICES
INTRODUCTION FAILURE MECHANISMS SCREENING FAILURE MECHANISMS ATTRIBUTED WAFER FABRICATION PROCESS
CARRIER
3.3.1.1 INTRODUCTION 3.3.1.2 CARRIER MECHANISM 3.3.1.3 SHIFT MOSFET 3.3.1.3 SHIFT MOSFET
OXIDE FILM DESTRUCTION
3.3.2.1 INTRODUCTION 3.3.2.2 TEST DATA (OXIDE FILM DESTRUCTION TEG) 3.3.2.3 SCREENING OXIDE FILM DESTRUCTION FAILURE RATE
ELECTRO/STRESS MIGRATION
3.3.3.1 ELECTROMIGRATION 3.3.3.3.1.1 INTRODUCTION 3.3.3.3.1.2 THEORY 3.3.3.3.1.3 TEST DATA 3.3.3.2 STRESS MIGRATION 3.3.3.3.2.1 INTRODUCTION 3.3.3.3.2.2 THEORY 3.3.3.3.2.3 TEMPERATURE DEPENDENCE INFLUENCE DEVICE STRUCTURE 3.3.3.3 SUMMARY
SOFT ERROR
3.3.4.1 INTRODUCTION 3.3.4.2 PHYSICAL MECHANISM 3.3.4.3 TEST DATA 3.3.4.4 OTHER SOFT ERROR EVALUATION METHOD 3.3.4.5 SUMMARY MECHANISMS FAILURES ORIGINATING ASSEMBLY PROCESS
RELIABILITY WIRE BONDING (RELIABILITY Au-Al JOINT)
3.4.1.1 INTRODUCTION 3.4.1.2 THEORY 3.4.1.3 TEST DATA 3.4.1.4 SUMMARY
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.4.2 RELIABILITY EXTERNAL PLATING MIGRATION PHENOMENON)
4.2.1 INTRODUCTION
.4.2.2 PHENOMENON 4.2.3 GENERATION MECHANISM .4.2.4 ACCELERATION FACTORS COUNTERMEASURES 3.5.4.2.5 SUMMARY 5.4.3 SLIDING PHENOMENON 3.5.4.3.1 INTRODUCTION 3.5.4.3.2 PHENOMENON 3.5.4.3.3 SUMMARY 5.4.4 MECHANISM FAILURES TRIGGERED FILLER 3.5.4.4.1 INTRODUCTION 3.5.4.4.2 PHENOMENON 3.5.4.4.3 SUMMARY MECHANISMS FAILURES ARISING FROM MOUNTING PROCESSES OCCURRING ACTUAL 5.5.1 RELIABILITY SURFACE MOUNTED DEVICES (SMD) 3.5.5.1.1 CHANGES FORM SURFACE MOUNTING 3.5.5.1.2 SURFACE MOUNTING METHOD 3.5.5.1.3 FAILURE MODES ENCOUNTERED MOUNTING PROCESS 3.5.5.1.3.1 CRACKS DEVELOPED RESIN PACKAGE 5.1.3.2 DEGRADATION MOISTURE RESISTANCE 3.5.5.1.3.3 MEASURES IMPROVEMENT MOUNTING 3.5.5.1.3.4 SUMMARY 3.5.1.4 FAILURE MODES APPEARING DURING ACTUAL (MOISTURE RESISTANCE
PLASTIC MOLD SEMICONDUCTOR DEVICES)
3.5.5.1.4.1 INTRODUCTION 3.5.5.1.4.2 MECHANISMS FAILURES 3.5.5.1.4.3 EFFECTS BIAS APPLICATION 3.5.5.1.4.4 ACCELERATION 3.5.5.1.4.5 METHODS EVALUATING MOISTURE RESISTANCE 3.5.5.1.4.6 SUMMARY 5.5.2 FAILURE MECHANISM SOLDER DEGRADATION LIFE ESTIMATION 3.5.5.2.1 INTRODUCTION 3.5.5.2.2 DEGRADATION SOLDER 3.5.5.2.3 RESULTS TEMPERATURE CYCLE TEST 3.5.5.2.4 LIFE ESTIMATION 3.5.5.2.5 SUMMARY
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
RELIABILITY BONDING WIRES (FATIGUE RUPTURE RESONANCE PRODUCED ULTRASONIC CLEANING)
3.5.5.3.1 INTRODUCTION 3.5.5.3.2 NUMERICAL ANALYSIS 3.5.5.3.3 EXPERIMENT 3.5.5.3.4 APPROXIMATE SOLUTION ESTIMATION RESONANCE RUPTURE
INCIDENCE
.5.3.5 RELIABILITY ANALYSIS .5.3.6 SUMMARY
ELECTROSTATIC DESTRUCTION
3.5.5.4.1 INTRODUCTION 3.5.5.4.2 STATIC ELECTRICITY 3.5.5.4.3 TESTING METHODS ELECTROSTATIC DESTRUCTION 3.5.5.4.4 FAILURE MODES ORIGINATING ELECTROSTATIC BREAKDOWN 5.5.5 CMOS LATCH-UP PHENOMENON 3.5.5.5.1 INTRODUCTION 3.5.5.5.2 PHYSICAL MECHANISM 3.5.5.5.3 ANALYSIS LATCH-UP PHENOMENON 3.5.5.5.4 LATCH-UP PHENOMENON ACTUAL 3.5.5.5.5 METHODS MEASURING LATCH-UP WITHSTAND CAPACITY 3.5.5.5.6 SUMMARY FAILURE MECHANISMS LD'S (LASER DIODES)
(CATASTROPHIC OPTICAL DAMAGE) REFERENCES
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
III. FAILURE MECHANISMS SEMICONDUCTOR DEVICES
INTRODUCTION
Reliability test designed reproduce failures product which occur actual use. Understanding failure mechanisms from results reliability test extermely important know product reliable actual use. effect stresses (temperaure, humidity, voltage, current etc.) occurrence failures identified understanding failure mechanisms, product reliability actual predicted from results reliability test, which conducted under accelerated conditions. Reliability-affecting problems product also identified clarifying failure mechanisms. Such information useful improving product design manufacturing processes enhance product reliability quality, well determining precautions which must made clear customers. Reliability test also provides useful information manufacturer screen products using optimal method selected according identified failure mechanisms. Furthermore, event failure reported market, understanding failure mechanisms enables manufacturer take prompt proper measures correcting design and/or manufacturing processes, that recurrence failure prevented. This chapter introduces typical failure mechanisms semiconductor devices that encountered actual screening methods semiconductor devices, analyzes major failure mechanisms.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
FAILURE MECHANISMS SCREENING
vast number sophisticated manufacturing processes required complete semiconductor device. failure mechanism therefore variable, each failure having various causes. Table III-1 gives manufacturing processes related major failures semiconductor device, well cause, mode detection method each failure. causes failures classified into design factor, manufacturing factor, operating environmental factor. many cases, these factors influence each other cause failure. should noted, therefore, that some failures caused single factor, some combination multiple factors. Fig. III-1 shows causes failures semiconductor device each manufacturing process. Fig. III-2 shows relation between failure rate curve (called bathtub curve) failure mechanisms. Generally, initial random failures caused either defects introduced during production stage operating environmental factor, such electrostatic breakdown. Initial failure rate lowered screening eliminating products with initial failures. Initial failures attributed design factors, materials, manufacturing techniques. When screening products, necessary note that objective screening eliminate products that deviate from range distribution through quality variation, eliminate those edges distribution. Care must taken that screening does cause excessive stress damage conforming products. With these mind, necessary select effective screening methods most suitable failure mech-anisms, while considering required quality reliability levels well economy. Table III-2 compares various screen-ing methods terms defects that eliminated, effectiveness, cost. recommended that these methods used independently combination.
FAILURE RATE
INITIAL FAILURE RANDOM FAILURE WEAR-OUT PERIOD FAILURE PERIOD PERIOD
FAILURE MECHANISM
ESD, LATCH-UP OXIDE FILM DESTRUCTION
FOREIGN SUBSTANCE, DEFECTIVE MASK
MANUCUSTOMFACTURER
MARKET (END USER)
SOFTWARE ERROR DEFECTIVE MOISTURE RESISTANCE ELECTROMIGRATION ELECTRONS STRESS STRAIN RESIN
Fig. III-2 Failure Rate Curve (Bathtub Curve) Failure Mechanisms
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
TABLE III-1 FAILURE MECHANISMS DETECTION METHODS SEMICONDUCTOR
Reliability-affecting process Causes failure Dislocation stacking fault Non-uniform resistivity Wafer fabrication Surface abnormalities Cracks, chips, scratches etc. (usually caused handling) Contamination Failure modes Detection methods
Initial electrical characteris-tics test Degradation junction characteristics (hereinafter referred electrical test) Operation life test Unpredictable characteristic values Inadequate electrical charac-teristics, short, open Open, short Electrical test Electrical test Operation life test
Cracks, pinholes Passivation Non-uniform film thickness Scratches, cracks, scars photo mask Misalignment Abnormal photo resist pattern (abnormal line width intervals, pinholes) Improper etching oxide film Undercut Etching Spotting (stain), non-uniform etching Contamination (residues photo resist chemical substance) Diffusion Improper doping profile control Scratches soil metallized layer (caused handling) Thin metallized layer insufficient deposition insufficient oxide film formation (stepped portions) Contaminated oxide film, material mismatch Metallization Corrosion (residue chemical substance)
Electrical test Visual inspection (before sealing) Temperature cycling test Visual inspection (before sealing) Degradation junction characteristics Temperature cycling Hightemperature storage HTRB tests High-temperature storage Temperature cycling High-voltage Electrical breakdown, short Operation life tests Visual inspection (before sealing) breakdown voltage Ditto increased leakage current oxide film Visual inspection (before sealing) Open, short Electrical test Open, short Degradation characteristics parameter drift, open, short Open, short, intermittent failure Short/open metallized layer Ditto Ditto Visual inspection (before sealing) Electrical Operation life test Visual inspection (before sealing) Electrical test Visual inspection (before sealing) Temperature cycling Hightemperature storage Operation life tests Ditto, HTRB test High-temperature storage Temperature cycling Operation life Electrical tests Visual inspection (before sealing) Temperature cycling Operation life tests Electrical Operation life Temperature cycling tests High-temperature storage Temperature cycling Operation life tests Visual inspection (before sealing) High-temperature storage Temperature cycling Operation life tests Visual inspection (before sealing) Electrical High-temperature storage Temperature cycling Operation life tests Electrical Temperature cycling Operation life tests Visual inspection (before sealing) Temperature cycling Vibration Mechanical shock Thermal shock tests
Masking
Latent short breakdown voltage, increased leakage current Degradation caused unstable defective active Passive elements Open, virtually open, short, virtually short Open, high-impedance internal connection Peeling metallized layer insufficient adhesion
Peeling metallized layer
Displacement, contaminated contact Improper metallization temperature time Dicing Cracked chipped caused improper dicing
High contact resistance, open Peeling metallized layer, poor bonding, short Open, latent open
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
TABLE III-1 FAILURE MECHANISMS DETECTION METHODS SEMICONDUCTOR (Continued)
Reliability-affecting process Causes failure Void between header Failure modes Degradation caused overheating Detection methods
bonding
Wire bonding
Radiography Operation life Constant acceleration Mechanical shock Vibration tests Visual inspection (before sealing) Radiography Vibration(monitored) Excessive spreading solder Short, intermittent short Shock (monitored) tests Visual inspection (before sealing) Poor bonding header Cracks peeling Constant acceleration Shock Vibration tests Temperature cycling HighMaterial mismatch Cracks peeling temperature storage Constant acceleration tests Broken wire, intermittent open, Constant acceleration Shock Excessive poor bonding strength peeling bonded wire, open Vibration tests Temperature cycling HighMaterial mismatch, contaminated Peeling bonded lead temperature storage Constant bonding acceleration Shock Vibration tests High-temperature storage Intermetallic plaque formation Open bonding Temperature cycling Constant acceleration Shock Vibration tests Operation life Constant acceleration Insufficient bonding area intervals Open, bonding short Shock Vibration tests Visual inspection (before sealing) Visual inspection (before sealing) Electrical Constant acceleration Improper bonding method control Open, short, intermittent operation Shock Vibration tests Visual inspection (before sealing) Improper bonding arrangement Open, short Electrical test Visual inspection (before sealing) High-temperature storage Cracked nicked Open Temperature cycling Constant acceleration Shock Vibration tests Visual inspection (before sealing) Excessively looped lead, excessive Short-circuit with case, substrate Radiography Constant acceleration insufficient drooping length lead other leads Shock Vibration tests Visual inspection (before sealing) Wire disconnection leading open Cuts, notches scratches lead Constant acceleration Shock short Vibration tests Ditto Radiography Tail wire remaining unremoved Short, intermittent short Incomplete hermetic seal Degradation characteristics, short chemical corrosion humidity, open Degradation characteristics attributed inversion layer channeling Open Short metallized layer leakage, open Seal test Operation life HTRB Hightemperature storage Temperature cycling tests Visual inspection/lead fatigue test Seal Electrical High-temperature storage Temperature cycling Highvoltage tests Low-voltage test Constant acceleration Vibration (monitored) Radiography Shock (monitored) tests Electrical characteristic test
Improper atmosphere package Broken bent external lead Sealing Cracks voids seal glass
Migration seal glass between outer Intermittent short lead metal case Dielectric particles floating package Intermittent short Inadequate marking Malfunction
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
TABLE III-2 COMPARISON SCREENING METHODS
Defects Lead shape Metallized layer Foreign particles oxide film Internal visual bond Wire bond inspection Contamination corrosion substrate bond Lead shape Foreign particles Manufacturing defect Radiography (major) Seal Package Contamination Electrical stability Metallized High-temperature layer Silicon substrate storage test Corrosion Package Seal bond Wire Temperature cycling bond Cracked substrate test Thermal mismatching Package Seal bond Wire Thermal shock test bond Cracked substrate Thermal mismatching Constant acceleration Lead shape bond Wire test bond Cracked substrate Foreign particles Vibration noise test Radioisotope fine leak Package Seal test Screening method Helium fine leak test Gross leak test Intermittent operation life test Package Seal Package Seal Effectiveness Cost Remarks
Good
Cost depends extent visual inspection
Good
Moderate
Assembled state checked after sealing
Good
Inexpensive
Preferable screening method
Good
Inexpensive
effective screening methods
Good Good Good Good Good Good
Inexpensive Moderate Expensive Moderate Moderate Inexpensive
Similar temperature cycling test
Effective detecting leakage range from 10-8 10-12 Effective detecting leakage range from 10-8 10-12 Applicable detecting leakage above 10-3
Dynamic operation life test operation life test
Metallized layer Bulk silicon Oxide film Inversion layer Good channeling Design Parameter drift Contamination Metallized layer Bulk silicon Oxide film Inversion layer Very good channeling Design Parameter drift Contamination Basically same Good intermittent operation life test Extremely good
Expensive
Expensive
Expensive Expensive
Less effective than dynamic operation life test most effective screening method
High-temperature Same dynamic operation life dynamic operation life test test
SILICON SUBSTRATE PHOTOLITHOGRAPHY JUNCTION FORMATION METALLIZATION
DIFFUSION DEPTH VOID THERMAL STRESS HILLOCK ELECTROMIGRATION INTERFACE STATE BULK DESTRUCTION CORROSION DISLOCATION STACKING FAULT IMPLANTED DOSE STEP COVERAGE MISALIGNMENT METALLIC IMPURITIES EXPOSURE/ DEVELOPMENT ADHESION IMPLANTATION ANNEALING THICKNESS CONTAMINATION DEFECT SCRATCH PHOTO RESIST ADHESION RESIDUE PINHOLE CRACK FOREIGN PARTICLES
OXIDE FILM FORMATION
DEFECT MISALIGNMENT PINHOLE MASK
CRACK
STRAIN
DEFORMATION SCRATCH DUST FILM THICKNESS
RESISTIVITY INTERFACE STATE
PROCESSINDUCED DEFECT
WARP
SCRATCH
CONTAMINATION
ALKALINE INSUFFICIENCY UNDERCUT EXCESS/ INSUFFI-CIENCY ETCHING FILM QUALITY CONCENTRATION PRECIPITATED IMPURITIES TEMPERATURE CHEMICAL RESIDUE EXCESS/ INSUFFICIENCY
NONUNIFORMITY
DISLOCATION
CONTAMINATION
CRYSTAL DEFECT
SURFACE CONTAMINATION
ADHESION
STACKING FAULT
HEAVY METALS
SHAPE
CARBON/ OXYGEN
STEPPED OXIDE FILM
DEFECTIVE CONTACT SOIL PENETRATION SURGE
SURFACE CONTAMINATION VOID SURFACE CONTAMINATION HUMIDITY FOREIGN PARTICLES BEND INTERNAL IMPURITIES EXTERNAL LEAD BREAKAGE ADHESION FRAME MISALIGNMENT CHIP STRAIN CRACK RESIN STRAIN CRACKED CHIP WIRE DRIFT VOID SEAL ABNORMAL LOOP INADEQUATE MARKING ABNORMAL ALLOYING
TEMPERATURE
ALPHA PARTICLES
OPEN SHORT DEGRADATION
INADEQUATE STRENGTH
CRACKED CHIP
TEMPERATURE SCRATCH WIRE CONDITION
THERMAL STRAIN INADEQUATE TAIL PROCESSING SOLDER
INADEQUATE STRENGTH
NOISE VOLTAGE/ CURRENT STATIC OXIDATION ELECTRICITY WHISKER RESIDUE RUST ATMOSPHERIC PRESSURE ATMOSPHERE CRACK ASSEMBLY PLATING SOLDERING HEAT
GENERATION
FLOATING FOREIGN PARTICLES CRACK SOLDER PRESOVERFLOW SURE
CONTAMINATION
INSUFFICIENT STRENGTH
ULTRASONIC HUMIDITY CLEANING TEMPERATURE CONTAMIDIE SEPANATION RATION VIBRATION MECHANICAL STRESS RADIATION SHOCK COSMIC
WIRE SCRAP
MATERIAL MISMATCH
POOR SOLDERABILITY THERMAL STRESS WIRE BREAKAGE VOID STRESS WIRE
RADIOGRAPHY
BONDING
WIRE BONDING SEALING
OTHER PROCESSES
OPERATING ENVIRONMENT
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
Fig. III-1 Characteristic Diagram Semiconductor Device Failures
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
Burn-in considered most effective screening methods semiconductor devices. burn-in method, semiconductor devices subject short-term, accelerated high-temperature operation life test. Normally, this accelerating condition attained raising supply voltage since many initial failures attributed oxide film defects, which cause high electric field acceleration. Meanwhile, intermetallic compound generation Au-Al junction reportedly causes high temperature acceleration. temperature stress dependence reaction speed discovered Arrhenius, been utilized form Arrhenius model. Among parameters this model activation energy temperature. higher activation energy, temperature stress dependence becomes greater. Since activation energy specific each failure mechanism, failure mechanism estimated determining activation energy value. Table III-3 gives typical failure modes mechanisms semiconductor devices, together with their activation energy values.
TABLE III-3 FAILURE MECHANISMS SEMICONDUCTOR DEVICES ACTIVATION ENERGY
Failure mode Mechanism Intermetallic compound generation au-al junction electromigration corrosion (Water intrusion) Oxide film destruction junction destruction (Al-Si solid phase reaction) junction destruction (Al-Si solid phase reaction) electromigration External lead breakage Drop current amplification factor Increase leakage current Change memory characteristics Shift threshold voltage KOVAR (Salty environment) migration accelerated moisture Generation inversion layer Leakage oxide film Polarization glass drift oxide film Slow trapping Si-Si oxide film interface (Plastic) (Memory) Diode electrode) Transistor (Microwave) (KOVAR frame) Transistor (Plastic) device (EPROM) device device device Subject device Activation energy 1.0eV[2], 0.6eV[4] 0.55eV[5] 0.3~0.35eV[6], 3.5eV[8] 1.5eV[9] 0.6eV[10] 0.65eV[11] 0.8eV[12] 0.8~1.0eV[13], [14] 0.8~1.15eV[15], [16] 1.0eV[17] 1.2~1.4eV[18] 1.0eV[19]
Open
Short
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
FAILURE MECHANISMS ATTRIBUTED WAFER FABRICATION PROCESS
CARRIER 3.1.1 INTRODUCTION
high-density integration LSIs been achieved mainly miniaturization. Dennard have proposed proportional reduction rule method proceeding with miniaturization devices [20]. This rule, which generally called scaling rule, follows: referring field effect transistor (FET) shown Fig. III-3, channel length decreased original value, punch-through phenomenon should occur. This prevented increasing substrate density factor prevent resultant increase threshold voltage (VTH) corresponding increase dependence substrate bias, gate oxide film thickness decreased original value. this time, there would problems supply voltage could also reduced original value. However, reduction supply voltage would cause internal signal level drop, desirable. Supply voltage therefore scaled down general practices. result, MOSFET internal electric field increases, accelerating impact ionization. Some stateof-the-art devices recently available market have lower internal operating voltage. carrier phenomenon problems that must considered enhance reliability.
SOURCE GATE DRAIN SOURCE (VS) GATE(VG) DRAIN(VD)
GATE OXIDE FILM
GATE ELECTRODE
LOCOS
SOURCE DIFFUSION LAYER
DRAIN DIFFUSION LAYER
LOCOS
LOCOS
DEPLETION REGION
LOCOS
DEPTH DIFFUSION (XJ)
EFFECTIVE CHANNEL LENGTH (LEFF)
CHANNEL REGION
ISUB
SUBSTRATE P-TYPE SUBSTRATE
Fig. III-3 Basic Structure MOSFET 3.1.2 CARRIER MECHANISM
Fig. III-4 Carrier Phenomenon n-MOSFET
MOSFET operation, electric field along channel from drain source uniform, being largest drain side end. saturation region operation particular, depletion region (pinch-off region) formed drain side since channel does reach drain diffusion layer. This narrow region supports most source-drain voltage, provides extremely high electric field. When electric field exceeds V/cm, impact ionization observed. impact ionization phenomenon explained below using n-channel MOSFET (n-MOSFET) shown Fig. III-4. Electrons injected channel region accelerated electric field channel region high electric field pinch-off region near drain, they receive energy high enough (1.6 more) cause impact ionization thereby generating electron-hole pairs. Most electrons thus generated absorbed drain become drain current However, small quantities electrons (having high energy) enter gate oxide film become gate current (IG). Almost holes generated absorbed silicon substrate become substrate current (ISUB). Thus, MOSFET operated saturation region, carriers generated impact ionization, causing various reliability-affecting problems. example, part electrons injected gate oxide film caught trap, changing mutual conductance (gm) MOSFET[21],
[22],
various electrical characteristics LSI[23]-[25].
floating gate memories (such FAMOS
EPROM), which gate electrode connected exterior, electrons injected gate oxide film accumulate gate electrode, causing soft-write failure[26]. also been reported that only part holes injected into gate oxide film cause various types degradation[27], [28].
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
When holes absorbed substrate become substrate curnt (ISUB), problems induced. first problem, ISUB flowing through substrate effect raising substrate electric potential (VSUB). Specifically, holes injected into silicon substrate cause substrate's surface electric potential rise locally. ISUB increases, junction between source substrate forwardbiased, effecting electron injection from source into substrate. Most injected electrons drift toward drain, forming electronhole carrier pairs result impact ionization occurring they approach high electric field region near drain. other words, this phenomenon involves regeneration, resulting complete breakdown between source drain. actual LSI, this pheFREQUENCY nomenon restricts allowable upper limit supply voltage (VCC) operation. voltage exceeding upper limit applied, excess current will flow, causing aluminum wire melt junction destroy-the phenomenon called breakdown. Fig.III-5 shows example breakdown voltage distribution 64M-bit dynamic RAM. breakdown voltage this dynamic problem, with sufficient margin relation absolute maximum rating 4.6V. Second problem secondary impact ionization which occurs holes accelerated depletion layer. Part electrons generated here diffused substrate. These diffused electrons lead malfunction operated small amount accumulated arges. been reported that diffused electrons cause soft error dynamic RAM[29]. Fig. III-6 summarizes reliability problems caused these carrier phenomena.
BREAKDOWN VOLTAGE
Fig. III-5 Breakdown Voltage Distribution 64M-bit DRAM
CARRIER PHENOMENA
ELECTRON INJECTION INTO GATE OXIDE FILM
HOLE CURRENT GENERATED PRIMARY IMPACT ISOLATION
ELECTRON CURRENT GENERATED SECONDARY IMPACT ISOLATION
SOFT WRITE FAMOS
SHIFT MOSFET
SOURCE-DRAIN BREAKDOWN
MALFUNCTION CAUSED INCREASED SUBSTRATE'S SURFACE ELECTRIC POTENTIAL
SOFT ERROR
Fig. III-6 Failures Caused Carrier Phenomenon
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.1.3 SHIFT MOSFET
mentioned Section 3.1.2, impact ionization remarkable high electric field region near drain. electron trapping phenomenon therefore most active oxide film near drain. This trend clear from Fig. III-7, which shows relation between source current (IS) drain voltage (VD) (=gate voltage (VG)) before after stress application. increases (negative charges accumulate gate oxide film) result stress application. chart, curve (Normal) indicates that relation between after stress application same during characteristic measurement, curve (Reverse) indicates that this relation after stress application reverse that during characteristic measurement. relation given shows large shift. This because, under biased condition VD=VG during measurement, pinch-off region created drain side, that silicon substrate surface condition this region gives little influence MOSFET characteristics. drain voltage reduced close linear region, pinch-off region will formed, narrowing between curves Fig. III-8 shows example shift n-MOSFET subjected long-time stress application. increases over time. increasing trend more conspicuous greater. increase every causes about 10-fold higher rate change VTH. This increase number electrons injected oxide film. Mutual conductance (gm) also degrades shifts. shift dominant while channel width n-MOSFET relatively small, degradation dominant when larger. indicated Fig. III-8, carrier phenomenon occurring form shift exhibits negative temperature dependence, which explained temperature dependence impact ionization coefficient, mean free path carriers, effective trap density oxide film[22],[30]. been reported, however, that drain current saturation region degrades substantially high temperatures. future, this degradation have serious inverse influence reliability deep sub-micron devices operated high temperatures[31].
(µA)
INITIAL
SHIFT (ARBITARY UNIT)
AFTER STRESS APPLICATION
VD=8V VD=7V 0.01
0.001 10-2
10-1
(=VG)
STRESS TIME
Fig. III-7 Shift Phenomenon n-MOSFET
Fig. III-8 Dependence Shift
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.1.4 ELECTRICAL CHARACTERISTIC SHIFT DEVICE
described previous section, shifts degrades MOSFET operated saturation region. These parameters also change under accelerated condition with high voltage. accelerated test with single MOSFET, tend change greater amounts than allowed design. This tendency more conspicuous finer structure. This because bias state actual circuit cannot simulated accurately accelerated test with single transistor. However, design highreliability must take into account bias state actual well results accelerated test with single transistor. this regard, simulation methods guidelines necessary parameters have been reported[32]-[34]. Generally, very rare that MOSFETs constituting responsible characteristic degradation. most cases, only part MOSFETs critical path degrade severe operating conditions[35] follows:
High drain voltage applied. Gate tends provide intermediate electric potential. Drain current value high. ON/OFF repeated high frequency.
MOSFETs operated under these conditions identified circuit simulation design stage, eliminated improving design (e.g. increasing channel length, restricting operating condition etc.), attain highly reliable LSIs. example, following paragraph describes lower limit shift dynamic which caused carrier phenomenon[25]. Figs. III-9 III-10 show voltage dependence temperature dependence, respectively, lower limit shift caused long-term aging. lower limit shift greater applied higher temperature lower. This shift caused shift n-MOSFET equalizing n-MOSFET shown Fig. III-11, assumed from simulation result internal potential waveform, which shows that above-mentioned transistors present severe electric potential state intermediate potential) which carrier phenomenon readily occur. Table III-4 specifies shift risk indices MOSFETs, determined simulation. Clearly, particular MOSFETs have severe operating condition requirements avoid carrier phenomenon.
Ta=20°C VCC=8.5V VCC=7.0V VCC=8.0V
VCC=8.0V
SHIFT
SHIFT
Ta=0°C Ta=20°C
VCC=6.0V
AGING TIME
AGING TIME
Fig. III-9 Voltage Dependence Lower Limit Shift
Fig. III-10 Temperature Dependence Lower Limit Shift
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
n-MOSFET 1/2VCC
nMOS
Table III-4 Shift Risk Index MOSFET
n-MOSFET pMOS nMOS EQUALIZING n-MOSFET Shift Risk Index
pMOS EQUALIZING n-MOSFET
Fig. III-11 Equivalent Circuit DRAM Memory Cell
Efforts have also been made last decade seek wafer process that eliminate carrier phenomena. Some state-of-theart LSIs have adopted MOSFETs lightly doped drain (LDD) structure shown Fig. III-12. This structure reduces field strength pinch-off region. Fig. III-13 shows effect structure shift. transistor structure[36], process damage[37]-[39] etc. have also been identified factors that influence carrier life.
structure Conventional structure VDS=7.0V VGS=3.5V Ta=20C
FIELD STRENGTH
SHIFT
10-1
CONVENTIONAL MOSFET
10-2 MOSFET 10-3 10-2
10-1
STRESS APPLICATION TIME
Fig. III-12 Comparison Field Strength between Conventional MOSFET Structures OXIDE FILM DESTRUCTION 3.2.1 INTRODUCTION
Fig. III-13 Effect Structure
Oxide film destruction dielectric breakdown accounts extremely high percentage failures field use. keep with increasing integration density LSIs, indispensable improve oxide film quality technique evaluating film quality. many years, many researchers have conducted studies concerning dielectric breakdown oxide film. old, most commonly used technique evaluating oxide film quality against dielectric breakdown voltage-ramping method[40],
[41].
This method
evaluates oxide film quality electric field which dielectric breakdown occurs film. determine such electric field, voltage applied oxide film increased gradually until dielectric breakdown occurs. found during 1970s, however, that dielectric breakdown takes place oxide film exposed long time electric field much lower than dielectric breakdown field. Many cases such time-dependent dielectric breakdown (TDDB) oxide film have been reported recently[42]-[46]. Since TDDB oxide film directly leads field failures, TDDB prediction effective estimating reliability. This section describes some methods evaluating oxide film quality with respect TDDB[7].
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.2.2 EXPERIMENTAL DATA (OXIDE FILM BREAKDOWN TEG)
Fig. III-14 shows typical result TDDB test using TEG. TDDB failure distribution divided into three regions distribution region initial failures attributable manufacturing defects etc. Manufacturing defects causing these initial failures eliminated manufacturer's screening before shipment. TDDB failures distributed region closely related with field failures actual products. distribution region true TDDB failures, that product life TDDB, which normally sufficiently long compared with actual life. 99.9 99.0 90.0 CUMULATIVE FAILURE 70.0 50.0 30.0 20.0 10.0 REGION REGION REGION
10-6
10-5
10-4
10-3
10-2
10-1 TEST TIME
Fig. III-14 TDDB Characteristic Capacitor
99.9 (1/(1-F(t))) 7.5M TIME FAILURE TOX=70A Ta=125°C ELECTRIC FIELD (MV/cm)
-2.09E
CUMULATIVE FAILURE
10-1 AGING TIME (SEC)
Fig. III-15 Distribution Oxide Film Life Dielectric Breakdown
Fig. III-16 Stress Bias Dependence Oxide Film Life
Fig. III-15 shows distribution oxide film life dielectric breakdown flat capacitor TEG. this chart indicates, oxide film life TDDB drops sharply stress (electric field) increases. Since oxide film used actual LSIs also very thin, electric field film, well TDDB characteristic region Fig. III-14, direct influence film quality. Fig. III-16 shows stress bias dependence oxide film life, assuming time cumulative failure rate oxide film life. acceleration oxide film destruction expressed follows: where Electric field oxide film (MV/cm) [E0: Electric field actual operation Electric field accelerated test] Absolute temperature [T0: Absolute temperature actual operation; Absolute temperature accelerated test] Activation energy temperature (Ea=0.30eV) Electric field acceleration factor Boltzmann's constant 8.62 10-5 eV/K) (III-1)
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
thinner film thickness, greater acceleration factor voltage becomes. However, considering that electric field actual operation high that thinner oxide film more likely susceptible manufacturing defects, extremely important manufacture oxide film high quality screen manufacturing defects completely. Various attempts have been made produce high-quality oxide film. Among these oxidation oxidation high voltage. Equation III-1 indicates, oxide film life depends largely electric field. Application high voltage oxide film therefore effective screening initial failures. Based this notion, screening been conducted following methods:
Operating wafer high supply voltage wafer test Conducting high-temperature high-bias burn-in final test
also necessary design LSIs that electric field possible applied oxide film during actual use.
3.2.3 SCREENING OXIDE FILM BREAKDOWN PREDICTION FAILURE RATE
Since uses thin gate oxide film MOSFET, oxide film destruction gives rise serious reliability-affecting problem. This problem more serious dynamic DRAM which uses thinner oxide film memory cell. high-temperature high-bias burn-in (B.I.) effective screening method that ensure high product reliability. instantaneous failure rates B.I. B.I. condition that product exhibit best possible efficiency design performance ratings. Specifically, voltage temperature highest permissible values. DRAM like products that contain dynamic circuits, necessary conduct dynamic B.I. which multiple-phase pattern applied ensure uniform bias application constituent elements. Fig. III-17 shows example flow B.I. experiment. Here, important analyze failure detected test conducted after each B.I., determine relation between B.I. condition B.I. time. intermediate test also conducted necessary determine time dependence B.I. effect. allow statistical dispersion failures, large number (some 5,000 10,000) test pieces must subject experiment. This section discusses relation between cumulative
TEST Pass B.I. (1st)
CUMULATIVE FAILURE RATE
Fail
F(t)=1-exp(-t0.2/240)
Fail TEST Pass B.I. (1st) Fail
TEST Pass
FAILURE ANALYSIS
TEST TIME
Fig. III-17 Flow B.I. Experiment
Fig. III-18 Result Model B.I. Experiment
Fig. III-18 shows result model B.I. experiment conducted based assumption that failures Weibull distribution, that B.I. conducted under condition Ta=125°C VCC=7.0 that acceleration coefficient (Ac) 1,130 times that actual operation. Based data Fig. III-18, time dependence cumulative failure rate F(t) B.I. expressed follows F(t)=1-exp(-t0.2/240) 125°C/7V (III-2)
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
form parameter Weibull distribution 0.2, that failure rate shows decreasing trend (m<1). other words, B.I. assumed have screening effect, causing failure rate decrease. When converted time under actual operating condition (Ta=55°C, VCC=5.0V), this relation expressed follows: F(t)=1-exp(-t0.2/980) 55°C/5V instantaneous failure rate calculated following equation: (t)=0.2 t0.2/980 (III-4) (III-3)
relation between B.I. time field instantaneous failure rate determined based Equations III-3 III-4. Fig. III-19 shows result. longer B.I. time, lower failure rate. time increases, however, reduction failure rate tends saturate, resulting lower efficiency. B.I. time should therefore according target quality level each product. product used this model experiment, B.I. time hours, which appropriate since instantaneous failure rate drops below target quality level this B.I. time. relation shown Fig. III-19 average result large number lots. Naturally, relation between B.I. time field instantaneous failure rate differs individual lots. necessary, therefore, confirm that each satisfies target quality level. Since this B.I. experiment assumes oxide film destruction failure mechanism, form parameter Weibull distribution considered constant. Fig. III-20 shows analytical photograph oxide film destruction observed B.I. experiment. Equations III-3 III-4 indicate, instantaneous failure rate (t)) lower cumulative failure rate (F(t)) after B.I. higher than Even when cumulative failure rate after 20-hour B.I. exceeds however, rate after additional hours B.I., that after 40-hour B.I. higher than product considered satisfy instantaneous failure rate goal FIT.
INSTANTANEOUS FAILURE RATE (FIT)
B.I. TIME
Fig. III-19 Relation between B.I. Time Instantaneous Failure Rate
Fig. III-20 Analyzed Oxide Film Breakdown
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
ELECTRO/STRESS MIGRATION
Electro/stress migration problem affecting reliability thin film metallizations LSIs. Electro/stress migration phenomenon which metal atoms move result overcurrent stress. Electromigration caused overcurrent, stress migration, stress. Whereas electromigration well-known phenomenon identified many years ago, stress migration discovered 1980s been understood well. Open short failure actual thin film metallizations LSIs often caused combination electromigration stress migration, difficult distinguish between these phenomena. following sections discuss electromigration stress migration separately.
3.3.1 ELECTROMIGRATION 3.3.1.1 INTRODUCTION
Electromigration phenomenon metal atoms moving under stress electric current. Specifically, when large current flows within metallization, metal atoms collide with electrons move direction current flow, metal atoms adjacent electron holes metal moving through holes[47]. this time, uniform mass movement occurs entire metallization region, problem arises. Non-uniform mass movement leads serious reliability problem. Where electrons flow from area large mass flux area small mass flux, mass boundary region increases, forming whisker hillock, causing short circuit between metal wires. Where electrons flow from area small mass flux area large mass flux, other hand, mass boundary region decreases, causing open failure.
3.3.1.2 THEORY
electromigration study approaches: approach considers moving electrons wave, other particles. Huntington have established following relational expression mass flux metal atoms, using former approach[48] J/(k exp[-/(k (III-5)
where metal resistivity metal diffusion coefficient eZ*, effective charge metal metal density sectional area metallization current density metal activation energy diffusion absolute temperature Boltzmann's constant. Black established following relational expression, considering electrons particles[49],[50] U=B0 exp[-/(k where constant which depends material. Equations III-5 III-6 indicate, metal mass flux decreased following measures
(III-6)
Decreasing current density Lowering temperature Decreasing value using metal with small value Increasing using metal with large value
When metal used fixed, item
depends defect density. Since aluminum (Al) used thin film metallization polycrystalline,
most significant crystal defects exist crystal grain boundary. Therefore, defect density reduced increasing grain size. Furthermore, number electron holes crystal grain boundary thin film metallization decreased adding copper (Cu) silicon (Si) activation energy diffusion varies depending diffusion mechanism[49]. energy intergranular diffusion through electron holes single crystal, diffusion through holes grain boundary, diffusion metallization surface. thin film used mass-production LSIs (grain size approx. film thickness less), activation energy generally regardless whether surface coating provided not.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
subsequent paragraphs discuss life thin film metallization relation open failure. Non-uniform temperature, non-uniform cross sectional area thin film metallization, non-uniform crystal grain size, contact with foreign matter possible causes nonuniform mass movement. approximate life thin film metallization terms time failure (TTF) calculated using Equation III-5[50]. Specifically, when temperature current density gradient exists anywhere thin film metallization, loss mass that section unit time determined from Equation III-5. When open failure caused temperature gradient, following expression holds TTF, which time when cross sectional area thin film metallization becomes initial value (TTF)TT3 exp[-/(k (III-7)
Similarly, when open failure caused current density gradient, non-uniform grain size contact with foreign matter (non uniformity Equation III-5), following expression holds (TTF)TT exp[-/(k (III-8)
Since open failure thin film metallization result complex, continuous reduction involving regeneration, Equations III-7 III8 should considered just guide prediction. From Equation III-6, following expressions derived temperature current density gradients, respectively. (TTF)TT2 exp[-/(k (TTF)T1 exp[-/(k (III-9) (III-10)
Thus, mass movement expressed Equation III-5, combined with various process factors, makes electromigration phenomenon more complicated. following expression, derived from Black's Equation III-6, generally been used predict TTF. (TTF)T1 exp[-/(k where coefficient (=1.5 2.5) representing current density dependence. (III-11)
3.3.1.3 EXPERIMENTAL DATA
Fig. III-21 shows scanning electron microscope (SEM) image thin film metallization which opened electromigration. Fig. III-22 shows time open failure, namely, life various thin film metallization structures, related temperature current density[4],[51].
Fig. III-21 Image Open Metallization Caused Electromigration
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
300°C 250°C
200°C
150°C
TIME FAILURE
TIME FAILURE
Samples thin film metallization evaporation-deposited flat SiO2 surface thin film metallization crossing approx. 1,000 stepped portions SiO2 film (III) thin film metallization connected series with junction (IV) thin film metallization connected series with polysilicon.
A/cm2
T=200°C
10-1
TEMPERATURE Temperature Dependence Life
CURRENT DENSITY (A/cm2) Current Density Dependence Life
Fig. III-22 Temperature Current Density Dependence Life
shown Fig. III-22(a), thin film metallization structures, temperature dependence life same, with activation energy diffusion 0.7eV. This result wonder because aluminum grain size almost same structures. following stated view current density dependence life shown Fig. III-22(b) Samples (II) TTFJ-1.6 when current density higher than A/cm2, TTFJ-3.9 when current density lower than this. assumed therefore that, high current density region, major cause open failure current density gradient, current density region, major cause temperature gradient Joule heating. Sample (III) TTFJ-2.5 met. temperature gradient assumed major cause open failure. Sample (IV) TTFJ-4.0 met. temperature gradient assumed major cause open failure. Based Fig. III-22 data, lives samples (II), (III) (IV) were predicted actual operating conditions. results shown Figs. III-23, III-24 III-25, respectively.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
TIME FAILURE
TEMPERATURE 25°C 50°C 75°C
100°C 125°C
CURRENT DENSITY (A/cm2)
Fig. III-23 Predicted Life Curves Sample (II)
TEMPERATURE 25°C 50°C TIME FAILURE TIME FAILURE 75°C 100°C 125°C
TEMPERATURE
25°C 50°C 75°C 100°C
125°C
CURRENT DENSITY (A/cm2)
CURRENT DENSITY (A/cm2)
Fig. III-24 Predicted Life Curves Sample (III) 3.3.2 STRESS MIGRATION 3.3.2.1 INTRODUCTION
Fig. Fig. III-25 Predicted Life Curves Sample (IV)
Stress migration phenomenon which metal atoms migrate presence thermal stress alone, with electric current applied[52],[53]. When thermal stress applied semiconductor device, stress occurs device difference thermal expansion coefficient between different materials. relieve this stress, metal atoms pulled migrate. Thin film metallization generally contains tensile stress, which concentrates crystal grain boundary metal. Therefore, metal atoms move diffusion, voids formed along grain boundary, ending break metallization. passivation film, which high compressive stress, increases tensile stress thin film metallization, thereby promoting stress migration.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.3.2.2 THEORY
stress thin film metallization expressed thermal stress intrinsic stress film, follows[54] (III-12) thermal stress occurs function temperature, object made more different materials, difference thermal expansion coefficient between different materials, expressed follows /(1-) 2)dt
(III-13)
where Young's modulus, Poisson ratio, thermal expansion coefficients, temperatures. intrinsic stress occurs crystal lattice distorted factor other than temperature. This stress depends largely materials process. Stress migration phenomenon plastic deformation caused metal atom electron hole movements attributed these stresses temperature. Fig. III-26 shows temperature dependence stress applied aluminum thin film metallization[55], along with deformation diagram aluminum[56].
TEMPERATURE (°C) NORMALIZED TENSILE STRESS 10-1 10-2 10-3 10-4
-200 -100 ALUMINUM THEORETICAL SHEAR STRESS DISLOCATION GLIDE
DISLOCATION CREEP
TENSILE STRESS (MN/m2)
10-5 10-6 10-7 10-8
ELASTICITY REGION
DIFFUSIONAL FLOW 10-1
10-2 10-3
Creep rate 10-8/sec Aluminum melting point 660°C Dislocation glide Dislocation creep Lattice diffusion (Nabarro-Herring) creep Grain boundary diffusion (Coble) creep
HOMOLOGOUS TEMPERATURE T/
Fig. III-26 Deformation Mechanism Aluminum
said that plastic deformation stress migration caused grain boundary diffusion creep dislocation creep[56],[57]. grain boundary diffusion creep rate dislocation creep rate expressed follows 1=A1 [-B/(k 1=A2 [-V/(k (III-14) (III-15)
which represents grain boundary diffusion constant; bulk internal lattice diffusion constant activation energies absolute temperature stress Boltzmann's constant; constants. These equations consistent with complicated behavior thin film metallization whose deterioration rate failure rate stress migration have peaks certain temperature.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.3.2.3 TEMPERATURE DEPENDENCE INFLUENCE DEVICE STRUCTURE
major factors influencing stress migration follows.
Temperature Dependence Regarding temperature dependence stress migration failures, researchers have reported variously some report that failure
rate peak certain temperature, some report that increases with temperature, others argue that independent temperature. Thus, temperature dependence stress migration failures clear presumably, various factors combined complicated manner cause stress migration.
Influence Device Structure Table III-5 summarizes main device structures that influence stress migration. Fig. III-27 shows image thin film
metallization that opened stress migration.
Table III-5 Influence Device Structure
Metallization film thickness Metallization width Metallization length Passivation film Base structure Additives thinner metallization, greater relative defect density therefore shorter life[58]. narrower metallization, larger influence defects therefore shorter life[58]. longer metallization, greater probability containing defects therefore shorter life[59]. compressive strength passivation film causes tensile stress increase metallization, resulting shorter life[60]. Steps base film surface raise probability non-uniform metallization thickness defects, resulting shorter life. Addition causes brittle metallization, resulting shorter life. addition relieves stress metallization, resulting longer life.
Fig. III-27 Image Open Metallization Caused Stress Migration
3.3.3 SUMMARY
mechanism electromigration been clarified almost completely. Studies have been underway based data shown Figs. III-23, III-24 III-25, determine electric current density each metallization that ensures sufficiently long life, well optimal pattern layout that does cause temperature gradient chip. been reported recently that pulse operation lengthen time electromigration failure[61]. these efforts aimed improving life prediction accuracy. Concerning stress migration, there many points remaining cleared. Addition metallization, adoption barrier metal structure low-stress passivation film under consideration, measures preventing stress migration failures.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
SOFT ERROR 3.4.1 INTRODUCTION
Conventionally, higher integration density LSIs, which dynamic typical, been achieved decreasing memory cell area. However, this leads reduction amount charge stored memory cell. Excessive reduction amount stored charge causes decay radioactive substances contained package internal metallization materials. result, particles emitted from these substances penetrate silicon substrate, generating noise, which destroys memory data [62]. Since this malfunction permanent corrected rewriting, called "soft error."
3.4.2 PHYSICAL MECHANISM
Fig. III-28 shows process which electron-hole pairs generated particles. When high-energy particle enters silicon substrate, electron-hole pairs generated along path particle, ionization effect particle's energy. n-channel FET, electron-hole pairs generated near diffusion depletion layers split electrons holes electric field, electrons drifting into n-type diffusion layer, holes p-type substrate. electrons collected n-type diffusion layer cause soft errors. dynamic RAM, there modes soft errors: cell mode line mode. cell mode error occurs when particles enter capacitor memory cell. this mode, error memory cell cannot occur, errors being 'L.' line mode error occurs when particles enter sense amplifier line. this mode, incidence errors each. typical DRAM, line mode soft errors dominant under operating condition shorter cycle time. These errors become remarkable particularly when particles enters sense amplifier neighboring region memory cell. Nearly soft errors attributed particles entering these areas.
ALPHA PARTICLE GATE SUBSTRATE ELECTRON-HOLE PAIRS
Fig. III-28 Process Electron-hole Pair Generation Particle Injection 3.4.3 EXPERIMENTAL DATA
following three methods have been used evaluate soft errors. flux from package internal metallization materials measured film track counting technique gridded ionization chamber (GIC) technique. particle immunity semiconductor chip evaluated using intense radiation source. device mounted actual system evaluated comprehensively. particle sources uranium thorium (Th) contained package internal metallization materials. Table III-6 gives contents each package material, flux measurements[64]. Although plastic itself plastic package emits virtually particles, alumina silica added filler plastic contains maximum Cerdip ceramic package contains several alumina binder clay, less than metal KOVAR 42-alloy. Zircon (ZnSiO4) added maximum filler seal glass contains high 1,000
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
TABLE III-6 PARTICLE SOURCES PACKAGE MATERIALS
Package Component Constituent (ppm) (ppm) Alpha flux (cm-2 hr-1) 0.1~0.6 130~300
Plastic
Filler
Al2O3, SiO2
0.2~0.6
0.2~1.0
Plastic
polymers
Cerdip
base Seal glass
90~95% Al2O3 Oxide (Solder glass)
0.2~0.6 100~1000
0.2~0.24
Ceramic
Package Metal
90~95% Al2O3 Gold-plated kovar
0.2~24
0.3~8
0.1~3 0.01~0.5
Ceramic
90~95% Al2O3
0.2~3.1
Braze seal
AuSn
Fig. III-29 shows acceleration test result soft error rate DRAM. test used intense particle radiation source acceleration. result shows DRAM's typical soft error trend, that combination line mode errors which inversely proportional cycle time (tCYCLE) cell mode errors which independent cycle time. Under normal operating condition (tCYCLE<1µs), line mode errors constitute more DRAM soft errors. Fig. III-30 shows supply voltage (VCC) dependence soft error rate DRAM. supply voltage decreases, soft error rate increases, reduction amount charge stored memory cell.
SOFT ERROR RATE (bit/min) SOFT ERROR RATE (bit/min) 2nd-generation DRAM 1st-generation DRAM particle source 241Am Ta=25°C VCC=3.0V Cell checker pattern
2nd-generation DRAM 1st-generation DRAM particle source 241Am Ta=25°C Cycle time :1.0µsec Cell checker pattern
10-1
10-1
10-2
10-2
10-3
10-3
10-4
10-4
10-5 10-1
10-5
CYCLE TIME (µsec)
ext.
Fig. III-29 Cycle Time Dependence Soft Error Rate DRAM
Fig. III-30 Supply Voltage Dependence Soft Error Rate DRAM
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
obtain accurate soft error rate device under actual operating conditions, long-term system evaluation must made with large number sample devices. Through error processing sequence shown Fig. III-31, soft errors (due particles) distinguished from other errors, such read errors noise during reading operation, hard errors which device operation becomes abnormal. separate errors electrical noise, necessary distinguish between single-bit errors multi-bit errors, know exact time occurrence each error check errors occur simultaneously multiple devices). Fig. III-32 shows correlation between system evaluation result acceleration test result soft error rate. From this correlation chart, estimate that present high-density DRAM's soft error rate higher than several FIT.
INITIALIZE (WRITE) READ DATA CORRECT? REREAD HARD ERROR DEVICE DEGRADATION READ ERROR DATA CORRECT? REWRITE REREAD SOFT ERROR ERROR PARTICLES READ ERROR SYSTEM NOISE NOISE ERROR SYSTEM NOISE
NOISE ERROR (MULTI-BIT ERROR)
DATA CORRECT? HARD ERROR MASK ERROR DEVICE
SOFT ERROR (SINGLE-BIT ERROR)
Fig. III-31 System Evaluation Sequence Soft Error
SOFT ERROR RATE (FIT)
64MD (Estimation)
256kD
16MD 16MD 300mil
10-4
10-3
10-2
10-1
SOFT ERROR RATE PARTICLE ACCELERATION TEST (1/min)
Fig. III-32 Correlation between System Soft Error Rate Accelerated Soft Error Rate
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
3.4.4 OTHER SOFT ERROR EVALUATION METHOD
Other than method described Section 3.4.3, soft error evaluation test method been proposed[65], which chip surface irradiated with ions measure soft error rate. Fig. III-33 shows measuring apparatus. This apparatus monitors soft errors occurring chip irradiating designated part chip with ions emitted from microprobe. Since chip locally irradiated with ions, chip portions susceptible soft errors located. irradiation intensity angle adjusted easily.
Multiplier Goniometer Scintillator Scanning Plate Microprobe
Memory
Output
Word Generator
State Mapping
Secondary Electron Image
Fig. III-33 Soft Error Measuring Apparatus with Microprobe
3.4.5 SUMMARY
Increase integration density semiconductor devices decreases their noise tolerance, making devices more susceptible malfunction caused cosmic rays particles emitted from trace amounts radioactive substances package materials. This malfunction permanent, corrected rewriting. prevent soft errors, essential
increase amount stored charge,
lower correction efficiency,
decrease flux.
Each these goals attained following measures.
increase amount stored charge Decrease thickness capacitor insulator layer, adopt high dielectric material layer. Adopt device structure, such three-dimensional cell. Adopt voltage-raising circuit device.
lower collection efficiency Reduce diffusion area. Increase concentration impurities substrate. Adopt structure, such well Hi-C structure.
decrease flux higher-purity materials components. Cover chip surface with high-purity protective film that does contain radioactive substances.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
MECHANISMS FAILURES ORIGINATING ASSEMBLY PROCESS
RELIABILITY WIRE BONDING (RELIABILITY Au-Al JOINT) 4.1.1 INTRODUCTION
assemble semiconductor device, semiconductor chip first bonded package, then surface electrode pad) semiconductor chip inner lead plated) package bonded connected with each other using fine metal wire Al). past, most semiconductor failures were attributed wire bonding process; however, recent technological progress wire bonding remarkable, with improvement accuracy manufacturing equipment automation manufacturing processes dramatically increasing reliability wire bonding.[66], [67] Automated wire bonding removes dispersion quality worker, reducing initial joint failures during manufacturing significantly. known, however, that joint made Au-Al binary system, formation intermetallic compound causes structurally unavoidable long-term life degradation phenomenon occur; intermetallic compound generally known purple plague. This section explains reliability wire bonding relation with progress diffusion Au-Al alloy.
4.1.2 THEORY
wire bonding methods available: wire thermosonic ball-bonding method wire ultrasonic wedge bonding. Both methods allow dissimilllar metals Au-Al alloy system form bonding joint. With wire method, joint between electrode semiconductor chip wire forms Au-Al joint; with wire method, joint between plated surface inner lead wire forms Au-Al joint. known that with such Au-Al joint, long-term storage semiconductor device high temperature causes contact resistance joint increase thereby joint have breaks ultimately; many instances such failures have been reported because they cause fatal failures equipment where they installed.[31], [68]-[75]. known that Au-Al alloy joint, several intermetallic compounds formed shown Fig. III-34.[76] Table III-7 shows characteristics intermetallic compounds, TEMPERATURE (°C) 1200 1100 1000 AuAl2
1060
AuAl
PERCENTAGE INTERMETALLIC COMPOUNDS (WEIGHT
Fig. III-34 Phase Diagram Au-Al systems [78]
TABLE III-7 PROPERTIES INTERMETALLIC COMPOUNDS CONSISTING AL[72], [73]
Chemical compound AuAl2 AuAl Au2Al Au5Al2 Au4Al Crystal structure f.c.c. CaF2 structure structure Unknown -brass structure structure f.c.c. Expansion coefficient Hardness (Hv) 20~50 Purple Gray 60~90 Yellowish golden Ditto Ditto Color
02.3
1.20
10-5 10-5
0.94 10-5 1.26 10-5 1.40 10-5 1.20 10-5 1.42 10-5
Au2Al Au5Al2? Au4Al
1063
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
following considered causes that lead degradation Au-Al alloy joints Several intermetallic compounds produced diffusion layer result Au-Al diffusion difference expansion coefficient between Au5A/l2 Au4Al layer causes joint strength lower difference diffusion coefficient between causes voids produced around joint (Kirkendall effect) this turn weakens joint strength[77][78] Au4Al alloy layer turned into high resistance layer oxidization taking place with bromide (Br), contained flame retardant resin material, catalyst[79][80]
4.1.3 TEST DATA
Wire Thermosonic Ball Bonding Fig. III-35 illustrates manufacturing procedure wire thermosonic ball bonding. wire purity 99.99% wire diameter usually 25-30µm. First, wire melt formed into ball with truly spherical shape. ball then thermosonically compressed onto thin film electrode with about thickness formed semiconductor chip under appropriate temperature load conditions. purpose using ultrasound process remove alumina (Al2O3) layer formed thin film thereby expose pure layer easy formation alloy layer. Fig. III-36 shows chip surface after bonding treatment. Heating bonded joint causes mutual diffusion occur. Although Au-Al diffusion takes place temperatures 150-200°C, diffusion proceeds quickly temperatures between 400°C, particular. After polishing section bonded joint embedded into resin, using metallographical microscope enables state Au-Al diffusion observed. distinguish between Au-Al alloy layers, sample etched using mixture (NH4)2S2O8 solution. Fig. III-37 shows section bonded joint Fig. III-38 schematically shows, basis result observation section obtained changing storage temperature storage time, Au-Al diffusion proceeds.
WIRE SPOOL CLAMPER CAPILLARY GOLD BALL LEAD FINGER BALL-FORMING TORCH ALUMINUM ELECTRODE SEMICONDUCTOR CHIP
BONDING AREA BONDING WIRE BALL BONDING WEDGE BONDING
Fig. III-35 Work Steps Wire Thermosonic Ball Bonding
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
LEAD FINGER WEDGE BONDING
BALL BONDING SEMICONDUCTOR CHIP
Fig. III-36 Surface View Thermosonic Ball Bonding
AuAl, AuAl2 Film
Fig. III-37 Sectional View Au-Al Bonding Joint
Au5Al2 Au4Al
AuAl, AuAl2 AuAl2
SiO2 Au4Al
HIGH RESISTANCE LAYER
Au4Al Void Au5Al2
Fig. III-38 Schematic Diagram Showing Au-Al System Diffusion Process
diffusion processes described below using Fig. III-38 guide: early stage bonding, thin diffusion layer formed between portion film; diffusion layer purple-colored estimated consist AuAl2 Further heating causes Au-Al diffusion proceed, with diffusing into thin film thereby causing pure layer disappear. same time, alloy layer distinguishable from Au-Al alloy formed ball side; this estimated consist Au5Al2 layer resulting from diffusion does exceed certain thickness; this thought limited supply difference diffusion velocity between direction toward that toward With denoting diffusion velocity, following relation exists DAuAl>DAlAu. With initial thickness evaporated film assumed 1µm, total thickness diffusion-formed portion about 4-5µm. Further heating causes diffuse into diffusion layer form Au4Al ball side, which grows into semiconductor chip side; Further heating causes diffusion into diffusion layer proceed thereby entire diffusion layer formed Au5Al2 Au4Al. addition, voids generated around diffusion layer result Kirkendall effect caused difference diffusion velocity between DAuAl DAlAu. [77][78] With heating still continued, diffusion into diffusion layer intensified except where voids generated, leading formation Au4Al layer central portion. With plastic molded IC's, known that contained flame retardant agents resin materials acts catalyst oxidize Au4Al layer.[79][80] penetrates from voids into joint oxidizes Au4Al layer, causing high resistance layer formed interface between center ball alloy layer; this leads disconnection failure. Fig. III-39 shows section joint under such condition.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
VOID
HIGH RESISTANCE LAYER
IMAGE
III-39 Formation High Resistance Layer (SEM Image)
measure relationship between state Au-Al diffusion bonding joint strength, push test shown Fig. III-40 used which joint strength measured storage temperature storage time changed. Fig. III-41 shows case where fracture took place. early stage diffusion, mode where pure left over, dominant, while middle stage diffusion mode with fracture taking place ball, mode with fracture taking place alloy layer, become dominant; mode considered result separation interface between Au5Al2 Au4Al portion. later phase diffusion, alloy layers separated expose base substrate; this called mode mode thought weak bonding Au4Al portion with oxide film base substrate, with mechanical strength joint being week also. Fig. III-42 shows relationship between progress diffusion results push test.
chip Bonding Gold wire
ball Push Spring balance
Fig. III-40 Push Test Method
THICKNESS BROKEN LAYER (µm) STORAGE TEMPERATURE 260°C
Fig. III-41 Fracture Mode Ball Bonded Joint Observed Push Test
SHEAR STRENGTH PERCENTAGE FRACTURE MODE Mode Mode THICKNESS FILM BONDING FORCE BONDING TIME BONDING TEMPERATURE 1.3µm 100g 0.3second 300°C
Mode
STORAGE TIME (SEC)
Fig. III-42 Relationship between Progress Diffusion Result Push Test
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
following Arrhenius equation holds between thickness diffusion layer, storage temperature storage time X2=D D=D0 (-Ea/kT) where Diffusion coefficient Activation energy Frequency factor Boltzmann's constant. Determining activation energy using results measurement diffusion layer, Colteryahn have value 15.5 kcal/mol (0.67eV)[70], Kashihara value 18kcal/mol (0.78eV)[72], Philofsky value 15.9kcal/mol (0.69eV)[75], Shimada value 13kcal/mol (0.56eV).[78] dispersion between these values thought difference between boundary conditions; however, activation energy Au-Al alloy thought range roughly extending from 18kcal/mol (0.6-0.8eV). following points must taken into consideration improve reliability ball bonding
(III-16)
initial bonding joint should processed time short possible temperature possible minimize AuAl mutual diffusion
Mechanical shocks should avoided where possible during bonding process prior resin sealing After package sealing, heating element should avoided where possible.
Wire Wedge Bonding Unlike wire ball bonding which supplied infinitely, wire wedge bonding carried with limited amount supply hence Au-Al diffusion takes place different mode, because Au-Al joint formed plated surface package lead. Kashihara have made report detailed study[72] regarding wire wedge bonding; results study summarized follows
Au-Al joint, cracking occurs Au-rich side progress Au-rich alloy layer formation depends thickness plating lead; thinner plating slower alloy layer formation proceeds
Abnormal resistance joint prevented from occurring less than where denotes thickness plating width effective joint. (The plating thickness will more than 10mm effective joint width 40mm.)
Initial Joint Properties Bonding described previously, bonding process been rapidly automated; same time, higher processing speed also been pursued improve processing capacity. goal increasing processing speed able finish bonding process short time possible while maintaining joint properties, many reports treat mechanism initial joint properties.[81][82] wire ball bonding, pressing ball onto electrode semiconductor chip causes ball start plastic deformation, with slip band being formed surface ball. oxide film destroyed contact surface between slip band electrode. minimum time required obtain sufficient initial joint properties bonding important factor realizing speedier wire bonding processing; time generally estimated 20ms wire bonding. [81] sequence time required wire bonding currently more than 0.3s/wire; this includes time required orbital movement capillary that bonding stitch side. prevent thermal effects from affecting joint, practice bonding relatively lower temperatures through wire thermosonic bonding method using ultrasonic vibration auxiliary means. Fig. III-43 shows relation between plastic deformation ball joint strength initial bonding stage thermosonic bonding process. increases proportion with some time delay, after certain time, both saturated, increasing longer. minimum bonding time required sufficient joint strength obtained thermosonic bonding ms.[83][84] ensure initial joint properties, controlling cleanliness surfaces materials strictly controlling bonding conditions (temperature, load, time) necessary.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
ULTRASONIC VIBRATION OPERATING TIME (ms)
Fig. III-43 Relation between Plastic Deformation Ball Joint Strength Wire Thermosonic Ball Bonding Structure
4.1.4 SUMMARY
Au-Al system wire bonding subject structural life limits imposed alloy system used. Under real-life conditions use, however, life described above pose serious problems. improve reliability bonding, more important effective that control manufacturing equipment selection materials properly conducted secure initial joint properties that unnecessary heating semiconductor devices after bonding process avoided where possible.
BOTTOM DIAMETER DEFORMED BALL
SHEAR STRENGTH
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
RELIABILITY EXTERNAL PLATING MIGRATION PHENOMENON) 4.2.1 INTRODUCTION
Silver migration type phenomenon which metal particles move under electrochemical effect; called electrochemical migration (referred simply "migration" this section) order distinguish from electro/stress migration which takes place wiring semiconductor chips. migration occurs with electrode materials other than such solder materials, adverse conditions prevail; however, that triggers migration most easily thereby tends pose problems. This section therefore describes migration.
4.2.2 PHENOMENON
When form foil, plating, paste, subjected voltage under high humidity temperature, electrolytic action causes migrate grow like blot tree-branches surface insulator shown Fig. III-44. This cause electrical insulation between electrodes decrease short-circuited. typical case migration, blot growth starts anode side while dendritic crystal growth starts cathode side. reality, however, effects difference types insulator, environmental conditions, like, ions eluted from anode side reduced halfway precipitate metallic precipitates from cathode side grow dendritically blot. Furthermore, because reacts easily with sulfur chlorine (Cl) atmosphere, these elements simultaneously detected analysis otherwise many cases.
COLLOIDAL BLACK-BROWN SILVER OXIDE WHITE REDUCED SILVER
SILVER ELECTRODE
INSULATING MATERIAL
POWER SUPPLY
Fig. III-44 Generation Silver Migration 4.2.3 GENERATION MECHANISM
Initially, when moisture settles between electrodes under voltage application, chemical reaction given Equation III-17 takes place anode: Ag+OH-AgOH+e (III-17)
Since silver hydroxide (AgOH) generated this reaction very instable, decomposition given Equation III-18 takes place: 2AgOHAg2O+H2O colloidal silver oxide (Ag2O) generated turn reacts given Equation III-19: 2AgO+H2O 2AgOH 2Ag++2OH(III-19) (III-18)
colloidal Ag2O generated ions move slowly ions, particular, pulled electric field), until they reach cathode reduced there silver metal: Ag++eAg (III-20)
silver precipitated exhibits white dendritic growth shown Fig. III-44. electric field strength dendrite increases with growth; therefore, growth, once initiated, proceeds with acceleration.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
4.2.4 ACCELERATION FACTORS COUNTERMEASURES
Listed below factors that accelerate occurrence migration; address them, necessary study them remove those having greater influence
Potential Difference Electrode Distance Being type electrolytic reaction, migration poses problems only when voltage applied between electrodes addition, time short-circuit between electrodes inversely proportional roughly potential difference proportional distance
Temperature Although temperature less involved than humidity, higher temperature accelerates chemical reaction hence migration;
Humidity (Specifically, condensation) Humidity affects migration greatly; general, migration does proceed under relative humidity more than 50%, rapidly accelerated under relative humidity less than
Types Insulating Material Like moisture, properties insulation materials affect migration greatly; general, migration generated remarkably highly hygroscopic phenolic resin laminated paper base materials nylon materials difficult occur poorly hygroscopic materials like glass epoxy substrates
Dust Content Water Quality Because dust itself contains water soluble contents acts retainer moisture, accelerates migration. Regarding water quality, higher electrolyte concentration accelerates migration.
4.2.5 SUMMARY
Measures against migration should examined into practice consideration working conditions (the environment voltage, particular), scope areas affected, quality requirements; matter course, allowing present anode best measure.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
SLIDING PHENOMENON 4.3.1 INTRODUCTION
failure phenomena arising from mechanical stress that semiconductor chip receives from package sliding. sliding phenomenon which, when semiconductor device subjected external thermal stress, stress from molding resin, applied wiring material semiconductor chip surface protecting film, causes wiring material slide. stress associated with sliding causes cracks produced passivation film protecting device surface; through these cracks external water impurities enter device corrode wiring, causing disconnection failures leaks between wires presence impurities; these failures pose problems affecting device reliability. This section describes sliding phenomenon caused stress from resin molding.
4.3.2 PHENOMENON
Because semiconductor chip, passivation film, molding resin have different coefficients thermal expansion, external thermal stress causes stress generated between different layers. When chip stored lower temperature, contraction stress from resin acts chip, causing wiring slide toward center chip. chip corner, particular, where stress coming from resin chip becomes large, sliding phenomenon more remarkable than center chip. Furthermore, this phenomenon more remarkable wide conductor which stress concentrated. sliding cracks passivation film closely related. Even wiring undergoes stress from resin under influence external stress, releasing wiring from thermal stress allows wiring restore original condition (elastic deformation) when passivation film normal; therefore, sliding phenomenon observed. With cracks developed passivation film under application repeated external thermal stress, however, original state cannot regained (plastic deformation). result, sliding phenomenon takes place. Fig. III-45 shows example sliding. This phenomenon accelerated temperature cycle test thermal shock test.[85]-[88]
Fig. III-45 Example Sliding 4.3.3 SUMMARY
sliding phenomenon caused difference coefficient thermal expansion between materials forming semiconductor device, giving rise passivation cracks which poses problems affecting reliability. address these problems, following methods available: form buffering film consisting polyimide resin similar substance between passivation film molding resin mitigate stress; place wider conductors chip corner portion; when such arrangement unavoidable, slits made onto wiring disperse stress.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
MECHANISM FAILURES TRIGGERED FILLER 4.4.1 INTRODUCTION
semiconductor chips packages become larger result tendency toward VLSI's, mechanical stress chip undergoes becomes ever larger. Disconnection failures thermal stress generated temperature cycle test have been known. Recently, charge quantity internal signals become smaller seen high density DRAM's; result, type failure arising from stress emerged. This section describes phenomenon which stress resin causes VLSI fail function normally.
4.4.2 PHENOMENON
When mechanical stress applied semiconductor chip, leakage current junction increases significantly shown Fig. III-46. stress arising from molding resin usually order 1kg/mm2 associated leakage current sufficiently small, which question.[89] However, when semiconductor device left alone high temperature environment, resin shrinks with internal stress increasing. Furthermore, when silica used filler resin compresses chip surface locally shown Fig. III-47, local stress grows further. result, leakage current becomes large enough cause VLSI malfunction; especially circuit, such sense amplifier DRAM, which senses microvoltage microcurrent, malfunction takes place easily.[90] reduce such stress, have taken such actions stress resin, spherical filler, chip coating, like. Another report gives example which local stress applied passivation film causes cracks develop passivation film.[91]
JUNCTION LEAKAGE CURRENT
10-2 10-4 10-6 10-8 10-10 10-12 10-14 MECHANICAL STRESS (kg/mm2) P-SUB 20µm chip Filler Ta=25°C
Plastic Resin
Fig. III-47 Section Portion Close Surface Semiconductor Device
Fig. III-46 Junction Leakage Current Mechanical Stress
4.4.3 SUMMARY
Failures arising from filler have potential occurring plastic mold semiconductor devices. cope with this problem, important mitigate stress which semiconductor chips undergo implementing measures described above.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
MECHANISMS FAILURES ARISING FROM MOUNTING PROCESSES OCCURRING ACTUAL
RELIABILITY SURFACE MOUNTED DEVICES (SMD) 5.1.1 CHANGES FORM SURFACE MOUNTING
Spurred recent needs thinner, smaller, lighter, multi-functional, high-reliability electronic equipment, high density mounting technology been almost established indispensable manufacturing technology major prime movers realization high density electronic equipment following
Advent electronic components including highly-integrated circuit components such IC's LS's chip components Rapid progress manufacturing technology materials circuit boards which form circuits Progress automatic mounting machines that mount electronic components onto circuit boards.
shown Fig. III-48, rapid progress that been made represented electronic components that have changed from vacuum tubes components with leads IC's, LSI's, chip components, thick film components, circuit boards that have changed from chassis sockets multi-layer printed circuit boards metal circuit boards, mounting methods that have changed from manual insertion automatic insertion mounting.
CHASSIS SOCKET PRINTED CIRCUIT BOARD THROUGH HOLE CIRCUIT BOARD FLEXBLE CIRCUIT BOARD VACUUM TUBE TRANSISTOR VLSI
METALLIC CIRCUIT BOARD
CHIP COMPONENT
COMPONENT WITH LEADS
THICK FILM COMPONENT
COMPOSITE COMPONENT THIN FILM COMPONENT
SUBSYSTEM COMPONENT
Mounting components terminals Soldering iron Long-nose pliers Nippers
Insertion components into Surface mounting printed circuit boards components onto printed Automatic inserter circuit boards Taping components Automatic chip mounter Forming components Automatic printer Laser trimming machine Chip taping method
multilayer mounting wireless bonding Precision micromachining High-precision film technology Light-sensitive metallized Improvement precision diversification circuit boards
TERMINAL MOUNTING
INSERTION
SURFACE MOUNTING
MULTILAYER HYBRID MOUNTING
1960
1970
1980
1990
Fig. III-48 Changes Mounting Technology
Figs. III-49, III-50, III-51 show lists packages. When area circuit board identical, necessary mount devices both sides circuit board. This necessity urged development surface mounted devices forward, which have become mainstream packages. shapes these packages various; recently, TSOP's (Thin Small Outline Packages) SQFP's (Shrink Quad Flat Packages, otherwise called VQFP's) becoming widespread push forward with miniaturization. order assure quality (reliability) after mounting these surface mounted devices, careful control required each step from storage devices mounting.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
PLASTIC MOLD PACKAGE
[MOUNTING METHOD] [NUMBER EDGES] [TYPE NAME] [OUTLINE]
(Single Inline Package)
SINGLE EDGE
HSIP (SIP with Heatsink)
INSERTION TYPE
(Zig-zag Inline Package)
DUAL EDGES
(Dual Inline Package) SDIP (Shrink Dual Inline Package)
(Small Outline Package) SSOP (Shrink Small Outline Package) DUAL EDGES TSOP (Thin Small Outline Package) (Small Outline J-leaded Package) SURFACE MOUNT TYPE (Quad Flat Package) LQFP (Low profile Quad Flat Package) FOUR EDGES TQFP (Thin Quad Flat Package)
(Quad Flat J-leaded Package)
ENTIRE SURFACE
(Chip Scale Package)
Fig. III-49 List Plastic Mold Packages
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
PACKAGE
[MOUNTING METHOD] [NUMBER EDGES] [TYPE NAME] [OUTLINE]
SURFACE MOUNT TYPE
ENTIRE SURFACE
BGA(Cavity Type) (Ball Grid Array)
BGA(Cavity Down Type)
Fig. III-50 List Ball Grid Array Packages
PACKAGE DUAL EDGES SURFACE MOUNT TYPE FOUR EDGES (Quad Tape carrier Package) (Dual Tape carrier Package)
Fig. III-51 List Tape Carrier Packages 5.1.2 SURFACE MOUNTING METHOD
forms mounting available: method which only surface mounted devices mounted side both sides circuit board another which surface mounted devices inserted devices simultaneously mounted. Soldering methods roughly classified into two: partial heating method which only soldered portion heated overall heating method which circuit board device heated whole. soldering methods given Table III-8. Soldering Iron Heating Method this method, soldering iron used; suitable volume production, frequently used correction purposes. Pulse Heater Method this method, heat collet pressed lead from device, pulse current passed heat collet solder lead. Because this method more suitable volume production than other versions partial heating method, used soldering connectors also. Heating Method this method, like nitrogen, heated heater, blown from nozzle solder objects. When this method used, thermal conductivity heat capacity used heat carrier small hence large supply required; therefore, uniform conditions stability difficult secure with this method. this reason, this method seldom used volume production. This method used remove failed devices because enables solder partially melt. Laser Heating Method this method, object soldered irradiated laser beams melt solder. Infrared Reflow Method entire surface device-mounted circuit board irradiated infrared light perform soldering. Enabling many devices simultaneously soldered, this method suitable volume production. drawback temperature difference produced between devices used depending their height, hence distance from infrared source. Some units both infrared air.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
TABLE III-8 SOLDERING METHODS USED SURFACE MOUNTED PACKAGES
Simplified designation mounting methods Mounting method Soldering iron Soldering iron method Productivity TemperTherEquipature Heating Soldera- Maintai- ment uni- capacity bility nability shock price formity
Partial heating method
Pulse current Pulse heater method Heater
heating method
Laser heating method
Laser
Infrared heater Infrared reflow method
Overall heating method
Vapor phase reflow method
Cooling coil Saturated vapor Inert liquid Heater Heater
reflow method
Flow soldering method Flow solder (surface soldering bath) Narrow pitch
Vapor Phase Reflow Method Also called (vapor phase soldering). According this method, special solution fluorocarbon solution, example) heated form vapor phase, which solder made reflow. vapor solvent makes temperature control easier prevents seizure solder flux materials. method well suited volume production also exhibits high solderability level. However, fleon used solvent, fleon content exhaust subject regulations; there many cases shifting from this method others. Reflow Method (Air Reflow Method) this method, inert gas, heated heater circulated furnace, supplies heat conduction make solder reflow. advantage this method similar that vapor phase reflow method, which difference temperature between board devices small their temperature controlled stay below predetermined value. Needing solvent, this method taking place vapor phase reflow method many cases; however, this method suffers such defects solder balls because solder placed more oxidizing atmosphere than atmosphere used vapor phase reflow method. Flow Soldering Method this method, device temporarily mounted circuit board adhesive, moved solder (flow solder) with device mounting surface down. Compared with reflow method, flow soldering method gives extremely large thermal stress device, necessitating sufficient preliminary heating alleviate thermal shock applied components. necessary mask portions that require soldering; some device outlines prevent soldering; therefore, this method suitable soldering highly densely mounted devices.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.1.3 FAILURE MODES ENCOUNTERED MOUNTING PROCESS
When surface mounted device mounted, only package leads also package itself exposed high temperature; this remarkable difference from mounting inserted device. actual temperature mounting between 250°C temperature greatly exceeding glass transition point (150-170°C) resin used package material applied; this means that very large stress, encountered insert devices, applied surface mounted devices. result, problems that occur surface mounted devices mounting process affect reliability following three:
Cracks developed resin package Degradation moisture resistance Effect wire bonding strength.
5.1.3.1 CRACKS GENERATION RESIN PACKAGE
most critical factor affecting reliability package thermal stress appearing mounting process. types thermal stress conceivable: thermal stress appearing moisture containing package that appearing one. former produced water vapor explosion moisture absorbed package latter produced difference coefficient thermal expansion. Fig. III-52 shows model cracks generated when moisture containing package undergoes solder reflow treatment. Moisture absorption (diffusion water vapor)
Condensation (water vapor water) CONDENSED WATER
Evaporation water associated with rapid temperature rise during mounting process
Delamination interface genaration cracks
Fig. III-52 Model Genaration Cracks Reflow Soldering Process[93]
simplified equation which incorporates factors affecting development package cracks given follows[92][93] (III-21)
where denotes stress generated rapid evaporation water, minimum length between package end, thickness resin below pad, length pad, bending strength package resin.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
When stress generated exceeds limit value right side Equation III-21, package cracks generated. When value right side Equation III-21 increases when stress water evaporation left side becomes smaller, package cracking suppressed. following four measures taken suppress cracking
Decrease moisture content package resin Make package resin low-stressed reduce residual thermal stress against thermal deformation Improve adhesion between package resin chip frame.
Next, method observing cracks resin package described. When cracks have substantially generated have extended outside, they observed stereoscopic microscope. However, cautions necessary overlook fine cracks when resin delaminated from chip frame when cracks have extended outward. following four methods generally used:
Observation outer cracks using microscope (Fig. III-53) Observation internal cracks delaminations polishing sections (Fig. III-54) Observation internal cracks delaminations using scanning acoustic microscope (Fig. III-55). device observed held water irradiated with ultrasonic beams; reflected waves received changed into images. This method allows non-destructive observation
Observation cracks delamination using fluorescent penetrant inspection method. package penetrated fluorescent penetrant section polished. Cracks delaminations observed using ultraviolet (fluorescent) microscope. Being highly sensitive, this method effective observing minute cracks delamination.
Fig. III-53 Example Microscopic Observation External Cracks
Fig. III-54 Example Observation Internal Cracks Delamination Polishing Sections
Product which cracks genarated
Product which cracks have genarated
Fig. III-55 Example Observation Internal Cracks Delamination Scanning Acoustic Microscope
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.1.3.2 DEGRADATION MOISTURE RESISTANCE
portions surface mounted device exposed high temperatures during mounting process; this results degrading moisture resistance device. Fig. III-56 compares results moisture resistance tests (PCT: 121C, 100% conducted under influence both moisture absorption thermal stress under influence moisture only.[94] MOISTURE RESISTANCE LIFE (TTF:Time Failure) 120°C 130°C 140°C 65°C 85°C
CUMULATIVE FAILURE RATE
85°C Solder after hours' moisture absorption
solder 121°C 100% TEST TIME (RELATIVE VALUE) Effect moisture absorption thermal stress 121°C 100%
121°C 100%
ABSOLUTE WATER VAPOR PRESSURE (kg/cm2) Acceleration under moisture resistance test conditions
Fig. III-56 Test Results (Effects Moisture Absorption Thermal Stress) Package
development cracks degradation moisture resistance, associated with stress occurring during mounting process, greatly affected thickness resin package, too. Fig. III-57 shows relation between dipping temperature incidence cracking with chip size taken parameter; figure shows that larger chip tends suffer crack development lower temperature. Fig. III-58 shows relation between percentage weight change moisture absorption incidence cracks with thickness resin taken parameter. seen that thicker package endures higher moisture absorption.
INCIDENCE CRACKS (ARBITRARY SCALE)
INCIDENCE CRACKS (ARBITRARY SCALE)
Moisture absorption 121°C, 100% hours Package: Chip size 50mm2 Chip size 4mm2
Thickness resin:1mm Thickness resin:2mm
Package: Moisture absorption 85°C, Solder dipping 260°C
Thickness resin 2.3mm
Chip size 2mm2
220°C sec. 260°C 330°C 350°C sec. sec. sec. 240°C 300°C sec. sec.
PERCENTAGE WEIGHT CHANGE
Fig. III-57 Chip Size Incidence Cracks
Fig. III-58 Change Weight Incidence Cracks
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.1.3.3 MEASURES IMPROVEMENT MOUNTING
described previously, handling storage after production very important surface mounted devices. However, Fig. III-59 shows that controlling environment alone sufficient. figure shows relation between time moisture absorption packages left alone environment with temperature 85°C relative humidity 85%. Because packages absorb moisture during storage cracks develop resin, control storage time baking prior mounting become necessary. Fig. III-60 shows dehumidification characteristics baked packages; seen from figure that baking process 125°C lasting 20-24 hours results sufficient dehumidification. moisture-proof packing pack Moisture Proof Packing) protection from exposure moisture during distribution phase also effective, being capable satisfactorily prevent external effect shown Fig. III-61. order ensure quality (reliability), important mount devices temperature possible short time possible with moisture absorption controlled manner described above. Fig. III-62 shows allowable upper limit reflow conditions mounting Mitsubishi surface mounted devices. have verified that discrepancies occur with mounting devices under this reflow conditions. therefore required that devices mounted reflow profiles lying below this upper limit reflow conditions. RELATIVE VALUE REFERRED SATURATION 85°C,
MOISTURE ABSORPTION RATE
Package
Cracks
develop Package
resin. Storage environment 85°C,
Storage temperature
150°C 125°C 70°C 50°C
1000 STORAGE TIME (hours)
STORAGE TIME (hours)
Fig. III-59 Storage Time Moisture Absorption Rate
Fig. III-60 Dehumidification Plastic Packages
MOISTURE ABSORPTION RATE
Package Storage environment 25°C,
Silica gel-impregnated moisture-proof packing
STORAGE TIME (hours)
Fig. III-61 Effect Moisture-proof Pack
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
215±5°C, 40±4s
REFLOW 235±5°C 10±1s 240°C above 200°C
TEMPERATURE
1~4°C/s 150±10°C 1~4°C/s 90±30s
TEMPERATURE
1~4°C/s 150±10°C
1~4°C/sec 90±30s
TIME
TIME
Fig. III-62 Reflow Conditions Surface Mounted Devices (Temperature Profile) 5.1.3.4 SUMMARY
ensuring quality (reliability) surface mounted devices, following points very important
Control moisture absorption packages (after opening packs) Minute adjustment mounting conditions.
ensure reliability moisture-sensitive surface mounted devices, stress associated with mounting process mitigated packaging them moisture-proof packing cases pack) containing drying agent protect from moisture during distribution phase using stress molding resin. However, depending type device conditions under which handle, problems occur; therefore, following precautions should taken:
control temperature humidity place where semiconductor devices stored duration storage, them earliest possible time
them soon pack opened should devices temporarily stored after opening pack, they should placed pack together with drying agent, with mouth pack folded over sealed with non-charging substance
devices temporarily stored after opening pack, they should dried prior mounting where possible they preferably dried 125°C 20-24 hours
mount devices temperature possible short time possible heat devices prior mounting avoid exposure sudden temperature rise.
5.1.4 FAILURE MODES APPEARING DURING ACTUAL (MOISTURE RESISTANCE PLASTIC MOLD SEMICONDUCTOR DEVICES) 5.1.4.1 INTRODUCTION
seal semiconductor device package, resins widely used cost reasons. Since time when plastic mold device first developed, degradation moisture resistance been highlighted reliability problem; however, plastic mold device since been reviewed improved from various standpoints reached level which problems hardly occur practical use. This section describes moisture resistance plastic mold device terms mechanisms failures, acceleration failures under actual conditions use, effects bias application, evaluation methods.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.1.4.2 MECHANISMS FAILURES
Water Penetration Path described below, water penetration paths possible plastic mold device: them passes straightforward through resin leads chip surface other passes through interface between resin frame leads chip surface (Fig. III-63). Various reports made thus far[95][96] relative significance these paths indicate that resin frame materials used package structure affect relative significance. recent data shows that greater role played path passing through resin than that passing frame interface, demonstrating improvement adhesion between frame material resin.
WATER PASSES THROUGH RESIN CHIP GOLD WIRE LEAD FRAME RESIN
WATER PASSES THROUGH INTERFACE
Fig. III-63 Water Penetration Paths Plastic Mold Device
Corrosion Metallization Aluminum chemically very active metal; left air, causes alumina 2O3) formed surface. Since this Al2O3 acts surface protection layer, reaction longer proceeds. presence sufficient water, other hand, aluminum hydroxide (Al(OH)3) formed. Al(OH)3 thus formed amphoteric, dissolving both acids alkalis; therefore, dissolves easily into water containing impurities. following typical corrosive reactions involving aluminum[97]: 2Al+6HCl2AlCl3+3H2 Al+3ClAlCl3+3 (III-22)
AlCl3+3H2lOAl(OH)3+3HCl 2Al+2NaOH+2H2O2NaAlO2+3H2 Al+3OHl-Al(OH)3+3 2Al(OH)3Al2O3+3H2O 2AlO2-+2H+Al2O3+H2O
5.1.4.3 EFFECTS BIAS APPLICATION
acceleration corrosive reaction involving aluminum external electric field easily understandable light fact that corrosion result electrochemical reaction that ionic substances involved reaction attracted electric field. Figs. III-64 III-65[98][99] show results study which made effects modes bias application values applied voltage moisture resistance. seen from figures that device life depends greatly mode bias application value voltage applied. Fig. III-66 shows example aluminum corrosion that developed during these tests. corrosion more frequently observed negatively biased portion (the cathode side) observation corroded surfaces reveals growth corrosion from grain boundaries. following reaction equation proposed model representing aluminum corrosion cathode side[100] Anode side 2H2O4H++4 e+O2 (III-23)
Cathode side 2Al+6H+2Al3++3H2 2Al3++6H2OAl(OH)3+6H+ 6H++6 e3H2
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
Reverse
CUMULATIVE FAILURE RATE
TIME FAILURE
"OFF"
85°C 85%RH
"ON"
Storage
85°C 85%RH 121°C 100% PRESSURE COOKER
TIME (hours)
VOLTAGE
Fig. III-64 Effects Bias Application Conditions
Fig. III-65 Effects Bias Voltages
Fig. III-66 Example Aluminum Internal Wiring Corrosion 5.1.4.4 ACCELERATION
Several acceleration models predicting reliability resin-sealed semiconductor device have been introduced basis moisture resistance test data failure rate function temperature (°C) relative humidity =exp [A+B (T+RH)] (where constants.) mean time failure, MTTF, affected separately joint temperature relative humidity Relation between MTTF Based Arrhenius' model 0.54 Relation between MTTF values logMTTF logRH linear relation time certain cumulative failure rate related with water vapor pressure [102]-[104] tVPm (III-25) MOISTURE RESISTANCE LIFE (ARBITARY UNIT) tVP-1.7 25°C/60%RH 30°C/70%RH 40°C/60%RH 60°C/90%RH ABSOLUTE STEAM PRESSURE (Pa) 85°C/65%RH 85°C/85%RH 120°C/85%RH 130°C/85%RH 140°C/85%RH
[101]
(III-24)
mean time related with square relative humidity
[105]
tm=t0 {-[n (RH)2]} (where constants.)(III-26) Although various acceleration models including those described above have been proposed, acceleration each them depends particular resin material, package structure, conditions metallization passivation, etc., which makes difficult determine generalized acceleration coefficient. Fig. III-67 shows acceleration properties plastic mold IC's currently relation with acceleration model described above Item (3).
Fig. III-67 Example Acceleration
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.1.4.5 METHODS EVALUATING MOISTURE RESISTANCE
Various methods evaluating moisture resistance available, with right method specific purpose being adopted. Table III-9 shows major test methods. Generally used pressure cooker storage test, pressure cooker bias test (primarily under unsaturated condition), high temperature high humidity storage test, high temperature high humidity bias test, varying combinations these tests. Furthermore, response widespread surface mounted devices (SMD), evaluation method been proposed which moisture resistance tests listed above preceded pretreatment consisting sequence hygroscopic thermal stress test.
TABLE III-9 IMPORTANT METHODS EVALUATING MOISTURE RESISTANCE
Evaluation method
Part test conditions 85°C/85%
Features substantial correlation with actual conditions use. Requires long time evaluation.
High temperature high humidity storage test High temperature high humidity bias test Pressure cooker storage test (Saturated type, unsaturated type) Pressure cooker bias test (Saturated type, unsaturated type) Combination tests
85°C/85% RH/with reversed bias substantial correlation with actual conditions use. Allows effects biasing evaluated. applied 121°C/100% 140°C/85%
121°C/100% RH/with bias applied 140°C/85% RH//with bias applied
Allows evaluation short time. Does allow effect biasing evaluated.
Allows effects biasing evaluated short time. Causes severe damage jigs like sockets.
121°C/100% RH/48hrs Allows effects biasing evaluated short time. 140°C/85% RH/with bias applied 121°C/100% RH/48hrs 85°C/85% RH/with bias applied 30°C/70% RH/168hrs reflow 140°C/85% 85°C/85% RH/with bias applied Allows evaluation shorter time than high temperature high humidity test. Allows SMD's evaluated light realworld use.
Combination tests
Moisture absorption thermal stress moisture resistance test
Pressure Cooker Bias Test This test method roughly classified into saturated type (121°C/100% example) unsaturated type (140°C/85% example). Originally, pressure cooker test been developed make water vapor penetrate into device quickly raising vapor pressure evaluating moisture resistance resin-sealed devices. beginning, therefore, storage test performed mainly saturated type pressure cookers. order respond need evaluating moisture resistance under biased conditions, bias test under saturated condition first developed ground problems with equipment. evaluation test under saturated condition, however, test tools such jigs were severely damaged this problem surfaced obstacle smooth operation tests. this reason, bias test under unsaturated condition developed. Fig. III-68 shows example results bias test under unsaturated condition. seen from figure, unsaturated pressure cooker bias test exhibits acceleration under 85°C/85% conditions, proving effective evaluation method. This method generally referred HAST (Highly Accelerated Temperature Humidity Stress Test).
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
CUMULATIVE FAILURE RATE
99.9 TEST TIME (hours)
150°C/85%RH 130°C/85%RH 120°C/85%RH 140°C/85%RH
85°C/85%RH
Sample: DRAM VCC=5.0V
Fig. III-68 Example Results Unsaturated Pressure Cooker Bias Test
Combination Test Power Devices Making advantages pressure cooker storage test high temperature high humidity bias test, combination tests have been developed which effective evaluating moisture resistance power devices, particular.[106][107] Fig. III-69 shows results test (Method
Table III-9) cyclically combining pressure cooker storage test (121°C/100% RH/24 hours) high
temperature high humidity bias test (85°C/85% RH/96 hrs), with Fig. III-70 showing correlation between total pressure cooker storage time high temperature high humidity biasing time cumulative failure rate. Both combinations conditions allow evaluation shorter time than continuous test would; example, evaluation requiring 10,000 hours under conditions completed 1,000 hours combination test. Fig. III-71 shows results combination test (Method
Table III-9) which pressure cooker storage (for hours)
followed pressure cooker biasing. This method also allows evaluation shorter time than continuous pressure cooker test would shortens biasing time, mitigating problem damage jigs continuous test.
CUMULATIVE FAILURE RATE CUMULATIVE FAILURE RATE
PRESSURE Reverse COOKER85°C, 85%RH
CUMULATIVE FAILURE RATE
Reverse Reverse
PCS+BPC
(24hrs)
hrs)
Combination 85°C 85%RH TEST
Output Output
NUMBER CYCLES
TEST TIME (hours)
TEST TIME (hours)
Fig. II-69 Results Combination Test
Fig. III-70 Comparison Results between Combination Test Continuous Test
Fig. III-71 Results Combination Test
Moisture Resistance Test Surface Mounted Devices (SMD's) mount SMD's circuit boards, mounting methods such infrared reflow vapor phase reflow (VPS) method used, with excessive thermal stress being applied devices. This causes only package cracking also peeling between resin lead frame chip interface occur, leading shorter moisture resistance life. confirm level moisture resistance SMD's, evaluation method using moisture absorption thermal stress test pretreatment into practice; details, refer Section 5.1.3.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.1.4.6 SUMMARY
moisture resistance used reliability evaluation, evaluation, failure rate confirmation, like semiconductor devices, evaluation methods suitable each these purposes used. guarantee moisture resistance plastic mold device under conditions actual use, device considered basically satisfactory withstands conditions 85°C hours, with conditions 30°C taken standard conditions based past acceleration test data.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
FAILURE MECHANISM SOLDER DEGRADATION LIFE ESTIMATION 5.2.1 INTRODUCTION
electronic systems downsized become versatile, high density mounting using surface mounting technology becomes widespread. reliability after mounting these surface mounted devices (SMD) frequently affected amount solder used mounting shape solder land. This section describes degradation solder heat cycle test solder joint estimation solder life.
5.2.2 DEGRADATION SOLDER
Fig. III-72 shows process solder degradation (Quad Flat Package). thermal fatigue micro solder joint thermal stress from heat cycle test causes cracks propagate cycle cycle, with cyclic propagation cracks leading ultimate rupture. addition, before mechanical rupture occurs, electrical failure (increase resistance) takes place; this defines rupture life.
INITIAL STAGE
CYCLES
300CYCLES
700CYCLES
1000CYCLES
Fig. III-72 Process Thermal Fatigue Micro Joint (Pb-63Sn) Temperature Cycle Condition (-50/+150°C)
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
5.2.3 RESULTS TEMPERATURE CYCLE TEST
Fig. III-73 shows distribution extreme values rupture failures temperature cycle test. AMOUNT SOLDER LARGE ACCUMULATED FAILURE RATE
-100°C~150°C -65°C~150°C -40°C~125°C
AMOUNT SOLDER SMALL ACCUMULATED FAILURE RATE 99.99 99.9 0.01 CYCLE 99.99 99.9 0.01 CYCLE
-100°C~150°C -65°C~150°C -40°C~125°C
99.99 99.9
SHAPE LAND
0.01 CYCLE 99.99 99.9 0.01 CYCLE
5001000
5001000
ACCUMULATED FAILURE RATE
ACCUMULATED FAILURE RATE
-100°C~150°C -65°C~150°C -40°C~125°C -40°C~125°C MOUNTED WITH EXTERNAL COATING
-100°C~150°C -65°C~150°C -40°C~125°C -40°C~125°C MOUNTED WITH EXTERNAL COATING
SHAPE LAND
5001000
5001000
Fig. III-73 Results Temperature Cycle Test
5.2.4 LIFE ESTIMATION
rupture life most strongly affected temperature dependence material used, environmental conditions, thermal fatigue strain amplitude qMAX which depends shape joint connection. Other parameters cycle frequency maximum temperature TMAX that affects diffusion atoms, rate propagation cracks. assumption that these parameters independent mutually related, general equation thermal fatigue life given follows[108]: General equation thermal fatigue NfµC p)-n/exp (Ea/kTMAX) where material constant indexes cycle frequency; plastic stress amplitude activation energy Boltzmann's constant TMAX maximum working temperature. Life equation incorporating crack propagation rate Nf=A af+B/A ao+B) where life; initial final crack dimensions Parameter that represents resistance crack propagation Parameter that gives initial propagation rate beginning crack (III-28) (III-27)
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
life crack propagation rate expressed Fig. III-74. propagation fatigue fracture usually divided into three stages. first crack generation life, second stage crack propagation life, third final rupture life. However, most thermal fatigue solder joint represented crack propagation life, second stage, with first third stage representing only percent total cases ending life. This great difference from other metals considered lower melting point softness inherent solder.
CRACK DEVELOPMENT RATE
Crack generation life Crack propagation life Final rupture life
NUMBER CYCLES (LOGARITHMIC SCALE)
Fig. III-74 Propagation Process Crack
5.2.5 SUMMARY
view trend further densification device mounting expected future, have established measures preventing solder rupture failures evaluating mechanical thermal stress method described above.
FAILURE MECHANISMS SEMICONDUCTOR DEVICES
RELIABILITY BONDING WIRES (FATIGUE RUPTURE RESONANCE PRODUCED ULTRASONIC CLEANING) 5.3.1 INTRODUCTION
process mounting IC's electronic equipment, ultrasonic cleaning with organic solvent often performed remove flux other stain after soldering IC's circuit board surface. this process, rupture, peeling, deformation bonded internal leads hollow package occur depending conditions such energy, amplitude, frequency ultrasound applied. From viewpoint fatigue rupture produced resonance internal leads attributable excitation frequency ultrasonic cleaning, investigated resonance phenomenon combining experimental verification logical analysis; this purpose, used numerical analysis which resonance mode natural frequency (resonance frequency) internal lead estimated. investigation revealed that cleaning ultrasonic cleaners with operating frequencies 20-40kHz, commonly used circuit board cleaning, cause bonded internal lead hollow package resonate ruptured, with incidence rupture with unprotected packages being order 0.1%. Based results this analysis, have selected appropriate profiles lengths internal leads hollow packages produced this measure enabled minimize probability putting internal lead into resonance process cleaning frequencies 20-40kHz.[109][110] This section describes outline numerical analysis experimental results.
5.3.2 NUMERICAL ANALYSIS
Fig. III-75 shows bonded internal lead schematically. resonance frequencies bonded leads having diameter 25µm each were determined following method INTERNAL LEAD
(CHIP) (PACKAGE)
Fig. III-75 Shape Bonded Internal Lead
natural frequency single beam with fixed ends generally obtained solving following equation (III-29) where denotes mode factor (1=4.73, 2=7.853), Young's modulus, mom
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