M16C/62 Group Application Note (Tentative) Mitsubish

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M16C/62 Group Application Note (Tentative) Mitsubish

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Mitsubishi Single Chip Microcomputers
M16C/62 Group Application Note <Simple Bus> (Tentative)
Mitsubishi Electric Corporation, Kitaitami Works Mitsubishi Electric Semiconductor Systems Corporation Mitsubishi Electric System Design Corporation REV.B
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Safety Considerations
Mitsubishi made every effort improve quality reliability products. Nevertheless, small percentage semiconductor products malfunction. Please incorporate redundancy features, fire countermeasures, malfunction prevention features, other safety measures prevent bodily injury, fire, inconvenience public.s
Using this Document
This document intended serve reference permit appropriate Mitsubishi semiconductor products customer applications. does represent consent implementation intellectual property other rights Mitsubishi Electric third-parties. Mitsubishi Electric takes responsibility damage infringement third-party rights arising from data, figures, tables, circuit charts presented this document. data, figures, tables, other information current publication this document; this information subject change without notice product features improved Mitsubishi Electric. Please have your company's technical specialists contact Mitsubishi Electric your retailer needed information about using products presented here. Mitsubishi Denki semiconductors been designed manufactured equipment upon which safety human life depend. Please contact Mitsubishi Denki your retailer information regarding transportation, moving vehicle, medical, aerospace, nuclear power control, sea-floor communications devices systems, other special applications. Written permission must obtained from Mitsubishi Electric Mitsubishi Semiconductor Systems prior excerpting duplicating this documentation. Export permits based foreign exchange overseas trade control laws applicable strategic products materials described herein must obtained prior export. Please contact Mitsubishi Electric your retailer with inquiries comments have about this document.
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Foreword
"M16C/62 Series Application Notes, "Simple Mode" reference materials intended help control simple mode which contained Mitsubishi CMOS microcomputer M16C/62 series. These materials intended serve guarantee communications operations bus. user, responsible performing adequate performance evaluation. Please these materials along with "M16C/60 Series Software Manual" information about M16C/62 series command system. Refer user manuals appropriate each hardware devices using, operating descriptions information about development support tools.
Chapter Appendix
Chapter Title Summary Mode Specifications M16C/62 UART2 Functions Functions Simple Mode Precautions Concerning Simple Mode
Page Number
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Summary
M16C/62 Series serial circuit (UART2) which provided with simple circuit. Using simple circuit combination with software enables control interface. This Application Note outlines specifications introduces various functions programs that used enable interface with simple function. this document, need fundamental knowledge about electrical circuits, logic circuits, microcomputers. document consists four chapters. refer appropriate chapters/sections information responding following needs:
need learn about protocol M16C/62 serial configuration M16C/62 simple block schematic register configuration functions M16C/62 simple mode Precautions regarding M16C/62 simple mode Refer mode interface program used M16C/62
Refer Chapter "Summary Mode Specifications" Chapter "M16C/62 UART2 Functions" Section Chapter "M16C/62 UART Functions" Sections 2.2~2.4 Chapter "Functions Simple Mode" Chapter "Precautions Concerning Simple Mode" reference program
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List Documents M16C Family
Applications (Microcomputer development flow)
Type Document
Microcomputer selection
Contents Hardware specifications (pin assignment, memory maps, specification peripheral functions, electrical properties, timing) Details hardware specifications, operations, application examples (connections with peripherals, relationship with software)
Datasheets/ Databooks Hardware
Schematic design system
Users' manual
Detailed design system
Programming manual Software
Assembly language, programming with C-language
Hardware development
Software development
Software manual Details each command operation (assembly language) Reference program collection Assembly language reference program collection
System evaluation
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Chapter
Summary Mode Specifications
Chapter Section Title Mode Features II2C Mode Concept Data Transmission Communication Coordination Definition First Byte Standard Mode High-Speed Mode Line Characteristics
multi-master communications inter-IC control protocol developed Philips that used many IC's. Refer information published Philips detailed specifications.
Mode Features
mode provides efficient control between IC's. two-way line with simple two-wire structure consisting serial data line (SDA) serial clock line (SCL). mode also includes following features: Each devices connected individual address. simple master1 slave2 relationship always established. master device functions either transmitting device reception device; slave device functions either slave transmitting device reception device. Collision detection3 communications coordination procedures4 incorporated into device prevent data destruction event that several masters attempt start data transmission simultaneously, permitting multi-master5 operations. Two-way serial data transfer enabled high-speed mode.
Note Note Note Note Note Devices that start data transmission, generate clock signals, data transmission. Devices that have addresses designated master. function that detects data transmitting levels other than when more than master device transmits data. procedure that enables control only master device when multiple masters attempt control simultaneously, ensuring that messages lost contents changed. This feature allows several masters control simultaneously without losing messages.
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Mode Concept
With wires (SDA SCL), performs data transmission among devices connected bus. Each piece equipment recognized individual address operated either transmitting receiving device, according functions equipment. Master devices those devices that transmit clock signals they transmit data; slave devices those devices that designate addresses response several masters. When master devices transfer data, master transmits clock signal obtain data transmission timing designates slave address (transmission). transmitting device then transmits data receiving device; data transmission ended master. clock signal always generated master with bus, each master generates clock signal whenever data exchanges take place bus. clock signal generated master low-speed slave device that maintains "low" then change another master during communications coordination procedures. (Refer 1.4, "Coordinating Procedures Using Synchronization" "SCL Synchronization".) Both two-way lines that connected positive power source through parallel resistance. When free, both lines into "high" status. Since output levels devices connected execute connection functions, either open drain open collector needed.
output terminals M16C/62 N-channel open drain output.
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Data Transmission
data transmission format defined follows:
Data effectiveness status between highs must remain constant. Changes level limited when low.
stable state Data effective.
Data change possible.
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Data Transmission Start Stop Conditions
communications procedures, data transmission begins with transmitting start condition master; data transmission stops with transmitting stop condition. When high, situation where changes from high called start condition.1 situation where changes from high called stop condition.2 Other than start stop conditions, level does change when high. Both start stop conditions always generated master. goes into busy status after start condition generated. goes into free status after stop condition generated.3
Start condition
Stop condition
M16C/62 simple mode "start condition detection interrupt" designed detect start conditions. (Refer Section 3.2, "Start/Stop Condition Detection".) M16C/62 simple mode "stop condition detection interrupt" designed detect stop conditions. (Refer Section 3.2, "Start/Stop Condition Detection".) M16C/62 simple mode "bus busy" flag indicating condition bus. (Refer Section 3.2, "Bus Busy Detection".)
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Byte Format
length each byte data output must eight bits. There limit number bytes that sent transmission (from time start condition generated time stop condition generated. number bytes sent continuously. Data sent sequence from uppermost (MSB) acknowledge attached after each byte (the ninth bit).
Acknowledgement signal from signal-receiving device Acknowledgement signal from signal-receiving device
Byte complete maintained Start condition Stop condition
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Acknowledge
Acknowledgements needed data transmission. clock signal acknowledgements generated master SCL. When clock signal acknowledgement (the ninth bit) generated, released transmitting device (high status). When acknowledgement clock signal rises each receiving device, acknowledgement signal generated because remains stable status.1 Receiving devices that have addresses designated must ordinarily generate acknowledgements whenever completion each byte received. slave receiver device does confirm address, slave maintains high status when acknowledgement signal rises does generate acknowledgement signal.2 this time, master transmits stop condition data transmission halted. When data cannot received during transmission, even slave receiving device confirmed address, condition indicated fact that acknowledgement generated. this time, slave maintains high status master generates stop condition. When master becomes receiving device, informs slave transmitting device data generating acknowledgement last data byte transmitted from slave. this time, slave transmitting device releases master able generate stop condition.,
Data output transmitting device
Data output receiving device
Acknowledgement generated
Acknowledgement generated
from master Start condition
Clock pulse acknowledgement
M16C/62 simple mode "acknowledgement detected" interrupt detect acknowledgement generation conditions. (Refer Section 3.3, "Acknowledgement Detection".) M16C/62 simple mode "acknowledgement detected" interrupt detect when acknowledgements have been generated. (Refer Section 3.3, "Acknowledgement Detection".)
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Communication Coordination
Communication performed according following procedures communications among several devices connected through bus.
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Communication Enabling Procedures
master only start data transmission when free condition. However, since multi-master bus, there situations which more masters generate start condition precisely same time. Communication enabling procedures exist prevent confusion when this occurs. These procedures performed using feature each device's open drain open collector output terminal. When high level, masters that transmitting high level turn data output level off, determining that communcation enabled when level (when arbitration loss occurs) detected (since other masters transmitting with level.)1 this way, communication enabling procedures executed through several masters attempt transmit their data. Simultaneous transmissions limit master that actually transmit data another device. masters that receive enabling immediately switched over slave signal-receiving mode they have slave capabilities. clock signal generated until byte that made determination grant communication enabling shut off. diagram below shows communication enabling procedures that take place between masters. When internal data level actual levels different master-generating DATA1, master's data output turned off. Thus data transmission that started master that iven communication enabling affected way. These procdures used only when many masters start same time; procedures priority masters order priority. Transmitting device enabled communication.
DATA
DATA
Stop condition
M16C/62 simple mode function that detects disparities between internal data levels levels timed rise (refer Section 3.5, "Arbitration Loss Detection Function") function turning output level output (refer Section 3.5, "SDA Output Prohibition Function when Arbitration Loss Occurs").
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Synchronization
M30622 chip does have register does operate multimaster environments.
procedures enable communication when several masters attempt start data transmission same time. clock signal output until last byte masters where communication enabled when arbitration lost, among masters that each generating their clock signals occurring bus. Synchronization different clock signals performed using feature open drain output open collector output terminals each device. clock signal device low, interval count started while maintained low. Even interval device ends clock signal goes from high, does change clock signals other devices remain interval. duration interval actually determined device with longest interval. During this interval, clock signal remains high devices with shorter interval (remaining high-impedance state). When devices finish interval, clock signal released system goes into high interval. clock signals output devices same status counting begins high intervals each device. reverts status according device that first finishes high interval. interval determined device that longest interval, while high interval determined device with shortest high interval, thereby synchronizing SCL.
Start HIGH interval count Hold status
CLK1
CLK2
Counter reset
M16C/62 simple mode "SCL Synchronization" function obtain synchronization. (Refer Section 3.5, "SCL Synchronization Function.")
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Definition First Byte
bus, first byte sent after start condition contains important data which designates slave. following definition first byte.
7-bit Address Format
bus, address with which master selects slave determined first byte continuing from start condition. following description explanation seven-bit address format. schematic below shows data transmission format. slave address sent after start condition (S). This address consists seven bits, with eighth constituting data direction (R/W). Transmitting slave indicated this data direction data request slave indicated However, retransmit start condition (SR) generated without first generating stop condition another address designated with next byte master wants continue communication bus. this case, slave address sent with seventh after retransmit start condition, with eighth serving data direction (R/W).
Acknowledged (SDA LOW) Unacknowledged (SDA HIGH) transmission direction change this point.
Acknowledged (SDA LOW) Unacknowledged (SDA HIGH)
Start condition
Slave address Read write
Sr=Resend start condition N-byte plus acknowledgement
Data
Stop condition Slave address Read write Data N-byte plus acknowledgement
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Definition First Byte Definitions Each First Byte
After start condition, first seven bits first byte show slave address. eighth data direction (R/W), which determines direction message. When address sent, after start condition, each device system compares first seven bits with their individual addresses. When addresses agree, device understands that been designated slave master puts line time with nineth clock pulse, returns acknowledgement signal, performs data reception (data direction "W") transmitting (data direction "R").
M16C/62 simple mode function that puts master into standby mode until address determination processing acknowledgement transmitting completed.
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Standard Mode High-Speed Mode
7-bit addresses standard mode maximum data transmitting rate kilobits/second. increasing from standard high-speed mode, 7-bit addresses well 10-bit addresses with data transmitting rates kilobits/second. devices which have interfaces handle high-speed mode.
M16C/62 simple mode also supports high-speed mode, with exception some restricted items. (Refer Chapter "Precautions Concerning Simple Mode"). Note,however,that address transmitting receiving performed software. (Refer "Example Auto Address Determination".)
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Line Characteristics
following table presents standard high-speed mode electrical characteristics line definitions:
Electrical Characteristics
Parameters level input voltage: When input level constant When input level varies according High level input voltage: When input level constant When input level varies according Input hysteresis Schmidt trigger: When input level constant When input level varies according Spike pulse width controlled input filter level output voltage (open drain open collector: When sink current When sink current Output fall time from VIhmin VIlmax when capacitance from 10pF 400pF maximum through VOL2 parallel resistance): Maximum sink current VOL1 Maximum sink current VOL2 Input current each when input current VDDmax Capacitance each
applicable
Note Note 0.5V. Capacitance (units: line. maximum lines (200 greater than maximum (250ns) output step. Thus, series protector resistor (RS) connected between SDA/SCL pins SDA/SCL line without exceeding maximum rated There interference with lines when supply cut. electrical properties M16C/62 different from standards bus. (Refer 4.1, "Electrical Characteristics".)
Symbol
Standard Mode Min. Max. -0.5 -0.5 0.7VDD 0.3VDD
High-Speed Mode Min. Max. -0.5 -0.5 0.7VDD 0.05VDD 0.3VDD
Units
Vhys
VOL1 VOL2
-n/a 20+0.1Cb 20+0.1Cb -250
Note Related Note:
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Timing Definitions
Standard Mode Parameters clock frequency free time between start stop conditions Hold time (retransmit) "start". Initial clock pulse generated after this interval. clock "low"status hold time clock "high" status hold time Retransmit "start" condition setup time Data hold time: CBUS compatibility master (see 9.3, "Precautions") Data setup time signal rise times tSU-DAT Symbol fSCL tBUF tHDSTA tLOW tHIGH tSU-STA tHD-DAT Min. Max. -High-Speed Standard Mode Min. -Max. -Units secs secs secs secs secs secs
Note
-1000
Note Note Note Note
Note -300
secs secs secs
signal fall times
secs secs
"Stop" condition setup time tSU-STD Load capacity each line above values correspond levels. Note
-400
-400
fill undefined region fall end, 300-ns minimum hold time signal signal min) must provided internally. When device does extend signal "low" (tLOW) hold time, only maximum data hold time tHD:DAT must met. Although high-speed mode used standard mode system, tSU:DAT>250ns condition that must satisfied. device does extend signal's "low" (tLOW) hold time, satisfaction this condition requested non-condition. device does extend signal's "low status hold time, following data bits need sent line before Rmax. tsu:dat 1000 1250 releasing line (according specifications standard mode bus.
Note
Note
Note Note
line total capacitance (units: electrical properties M16C/62 different from standards bus. Refer 4.1, "Electrical Characteristics".
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tBUF
tLOW
tHD:STA
tHD:STA tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STD
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Chapter
M16C/62 UART2 Functions
M16C/62 serial consists five channels, UART0, UART1, UART2, well I/O3 I/O4. Each these channels timer generating dedicated transmitting clocks, these timers function independently. this chapter, discuss detailed settings simple mode, which UART2.
Chapter Section Title Functions UART2 Block Diagram Simple Mode Terminal Functions That Change Mode Interrupt Causes Register Setup When Simple Mode
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Functions UART2
With exception some different functions, functions UART0~ UART2 channels essentially same. these channels, UART2 particular makes modes which handle interface, interface, interface. UART0~ UART2 make selective either clock synchronization-type serial mode clock non-synchronization-type serial mode. clock non-synchronization-type serial mode particular handle interface interface. M16C/62 serial data switching function collision detection function order enable interface interface. M16C/62 data sheets detailed information about these functions. Further, UART2 clock synchronization-type serial mode makes possible handle interface. this chapter, present M16C/62 simple mode block diagrams each type relevant register. next chapter, discuss functions needed make interface work with M16C/62. interface, interface, interface functions which limited UART2. M16C/62 serial configuration: UART0 Clock synchronization-type serial Clock non-synchronization-type serial UART1 Clock synchronization-type serial Clock non-synchronization-type serial UART2 Clock synchronization-type serial interface Clock non-synchronization-type serial interface interface I/O3 I/O4 Clock synchronization-type serial Clock non-synchronization-type serial
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Block Diagram Simple Mode
M16C/62 simple mode used enable interface. simple mode effectuates circuit interface setting selector (IICM) "1." following mode block diagram.
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Terminal Functions That Change Mode Interrupt Causes
M16C/62 simple mode into effect setting mode selector (IICM). following tables show each function when simple mode selected.
Terminal Functions
P7_0 terminal function P7_0 output initial value P7_1 terminal function P7_1 terminal read P7_2 terminal function (IICM) (Simple mode) (input/output) value P7_0 when serial valid (input/output) terminal reads, regardless directional register Port P7_2 (IICM) (Common mode) TxD2 (output) level RxD1 (input) accordance with directional register settings CLK2
Main Interrupt Causes
(IICM) (Simple mode) Cause: interrupt Cause: interrupt Cause: interrupt DMA1 cause when request factor selector "1101" (IICM2) (IICM2) Start/stop condition detected Acknowledge UART2 transmission detected Acknowledge detected UART2 reception Acknowledge detected UART2 reception (IICM) (Common mode) collision detected UART2 transmission UART2 reception UART2 reception
Precautions concerning processing commands port: When input/output port data register (port latch), rewritten using processing commands, bits which have values designated them change. Reason: processing commands read-modify-write commands which perform reading writing units. Therefore, when these commands executed relation certain bits input/output ports data register, following processing takes place relation entire data register:
Bits with input terminal value read CPU, this read after processing. Bits which values have been data register values read CPU, these bits written after processing. Please note that output values changed when read-modify-write commands executed port
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Register Setup When Simple Mode
Registered configured follows when using simple mode M16C/62 UART2:
UART2-relevant register
read this figure: with simple mode with simple mode Select either valid with simple mode
UART2 transmitting buffer register
Function
Values that
(b15)
(b8)
Symbol U2TB
Address 037B16, 037E16 0016 FF16
reset Undefined
Transmitting data (bit ACK)
Nothing located here. when writing. Value undefined when reading.
UART2 reception buffer register
Name
Function
(b15)
(b8)
Symbol U2RB
Address 037F16, 037E16 Reception data
reset Undefined
Nothing located here. when writing. Value undefined when reading. Arbitration lost detection flag Overrun error flag detected (success) Detected (defeat) overrun Overrun valid mode valid mode valid mode
Framing error flag Parity error flag Error flag
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UART2 transmitting speed register
Function
Values that
Symbol U2BRG Address 037916 0016 FF16 reset Undefined value BRG2 will divide count source.
UART2 transmit/receive mode register
Name
Function
Symbol U2MR SMD0 SMD1 SMD2 CKDIR Internal clock selector Serial mode selector
Address 037816
reset 0016
b2=0 b1=0 b0=0: serial valid (port control) b2=0 b1=1 b0=0: simple mode
Internal clock (set when master) External clock (set when slave) valid mode valid mode valid mode Reversal reversal
STPS
Stop length selector Parity odd/even selector Parity authorization TxD, input/output polarity switching
PRYE IOPOL
(set when mode)
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UART2 transmit/receive control register
Name
Function
Symbol U2C0 CLK0 count source selector
Address 037C16
reset 0816
b1=0 b0=0: selected b1=0 bo=1: selected b1=1 b0=0: selected b1=1 b0=1: permitted.
CLK1 CTS/RTS function selector Transmitting register blank flag valid when
TXEPT
Data transmitting register data transmitting register CTS/RTS function allowed CTS/RTS function prohibited. (set when mode)
CTS/RTS prohibition
Nothing located here. when writing. Value when reading. CKPOL Clock polarity selection Transmitting data output fall transmitting clock reception data output rise. Transmitting data output rise transmitting clock reception data output fall. format format
UFORM
Transmitting format selector
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UART2 transmit/receive control register
Name
Function
Symbol U2C1 Transmitting authorization Transmitting buffer open flag
Address 037D16
reset 0216
Transmitting denied Transmitting authorized Data transmitting buffer register data transmitting buffer register Reception denied Reception authorized Data transmitting buffer register data transmitting buffer register Transmitting buffer open (TI=1) Transmitting complete (TXEPT=1)
Reception authorization Reception completed flag
U2IRS
UART2 transmit/ receive interrupt cause selector (Note: U2IRS valid when (IICM)-1 (IICM2). UART2 continuous reception mode authorization Data logic selector
U2RRM
UART2 clock
output
U2LCH
reversal
Reversal
(set simple mode) U2ERE Error signal output authorization simple mode.
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UART2 special mode register
Name
Function
Symbol U2SMR IICM mode selector (Note: serial mode selector when simple mode.)
Address 037716 Normal mode Simple mode
reset 0016
Arbitration lost detection flag control (Note: when (IICM) (IICM2). busy flag (can written SCLL synchronization output authorization (Note: Valid only when port control; this valid when serial I/O). collision detection sampling clock selector Transmitting authorization automatic clearing function selector Transmitting start condition selector
Update each Update each byte
Stop condition detected Start condition detected Denied Authorized
LSYN
ABSCS
ACSE
Nothing located here. when writing. Value when reading.
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UART2 special mode register
Name
Function
Chapter explaining bits
Symbol U2SMR2 IICM2 mode selector Clock synchronization wait output
Address 037616 Table Denied Authorized Denied Authorized Denied Authorized Denied Authorized UART2 clock output Denied Authorized (high impedance) This must when mode
reset 0016
output stop
STAC
UART2 initialization
SWC2
wait output
SDHI
output prohibition
SHTC
Start/stop condition control (Table
Table
Function Interrupt signal cause IICM2 acknowledgement detected (NACK) Acknowledgement detected (ACK) IICM2 UART2 transmitting (rise last transmitting clock) UART2 reception (fall last reception clock) UART2 reception (fall last reception clock) Fall last reception clock
Interrupt signal cause
cause when request cause selector Timing data transmitting from UART2 reception shift register reception buffer Timing UART2 reception/acknowledgement detection interrupt request generation
Acknowledgement detected (ACK)
Rise last reception clock
Rise last reception clock (acknowledgement detected)
Fall last reception clock (UART2 reception)
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Table Start/stop condition detection timing characteristics (Note
Setup time
Hold time
cycles setup time (Note cycles hold time (Note Note When start/stop condition control SHTC=1. Note number cycles indicates main clock input oscillation frequency (XIN) number cycles.
Start condition
Stop condition
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Chapter
Functions Simple Mode
this chapter, discuss methods using hardware functions when M16C/62 uses simple mode realize interface.
Chapter Section Title Byte-Data Transmission/Reception Methods Start/Stop Conditions Acknowledgement Own-address Designation Determination Communication Coordination Other Functions
Byte-Data Transmission/Reception Methods
Here present simple mode transmitting setup method where M16C/62 used master, well 1-byte transmitting setup methods reception.
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Generation Method master)
sending clock (SCL) speed must when using M16C/62 master. following registers just they would normal serial transmitting. After writes transmitting data buffer, transmitting performed cycles SCL. transmitting timing (BRG count source)
Maximum cycles
transmitting UART2 transmitter/receiver mode register (U2MR: 037816 address)
[SMD] When simple mode [CKDIR] Selects internal clock (when master). When slave, select external clock. [IOPOL] reversal polarity
UART2 transmitter/receiver mode register (U2SMR: 037716 address)
[IICM] Simple mode [ABC] Arbitration lost updated each Update every byte
[LSYN] SCLL synchronization ouput denied SCLL synchronization output authorized UART2 transmitter/receiver mode register (U2C0: 037C16 address)
[CLK1] count source selection Select Select [illegible] Select denied [CRD] CTS/RTS function denied. [CKPOL] polarity outputs transmission data fall inputs rise. [UFORM] Transmission format format format
UART2 transmission speed register (U2BRG: 037916 address) 0016 FF16
Count source division Settings when device slave Setup example When using 1-MHz source oscillation transmission speed Kbps: U2MR 00000010b (I2C mode, internal clock selected) U2C0 10010000b (BRG count source selected) U2BRG When using device slave, (CKDIR) UART2 send/receive mode register (U2MR) select external clock. this time, count source selector (CLK0) (CLK1) UART2 transmission speed register (U2BRG) settings valid.
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Byte-Data Transmission/Reception Methods
When M16C/62 used transmitting device, eight-bit transmission data sent from terminal, terminal must free receive transmission clock acknowledgement ninth bit. This operation performed with data that sets transmission buffer. Nine-bit data used transmission buffer. bus, data sent with fast "first"]. M16C/62, transsmission format fast nine-bit data sent b7>b6>.>b0>b8 order. Since uppermost timed transmission when acknowledgement received, terminal free uppermost M16C/62's into high-impedance status.
Relevant register
Sending data release timed
Timing pattern
M16C/62 (transmission-side transmission SDA)
Transmission data
U2TB<-1XX16
release (Hi-Z)
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Byte Data Reception Methods
When M16C/62 being used receiving device, M16C/62 terminal needs released while receiving eight-bit data from terminal. Also, terminal must into generate acknowledgement ninth clock. With this, address determination receiving device that been designated master completed. Acknowledgement transmissions easily executed value that been written transmission buffer when been confirmed that transmission taken place this master-designated device. Also, nine-bit data transmission buffer dummy data when M16C/62 receives data. While lower eight bits sent, these bits because terminal released. Moreover, last transmitted (b8) generate acknowledgement. This indicates that byte data received. Relevant register UART2 transmission buffer register (U2TB, 037B16, 037A16 address)
release transmission
M16C/62 (receiving side) transmitting
released (Hi-Z)
ACK(`L') transmission U2TB<-0FF16
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Transmission Interrupt/Reception Interrupt
completion data transmission detected with aUART2 transmission interrupt when M16C/62 used transmission device. Also, completion data reception detected with UART2 reception interrupt when M16C/62 used receiving device. These interrupts allocated interrupt registers interrupt causes UART2 transmission reception, respectively, determined mode selector (IICM2) being timing generation transmission interrupt this case determined fall clock's start when UART2 transmission interrupt cause selector (U2IRS) generation transmission interrupt timed rise (U2IRS) selector when timing generation reception interrupt coordinated with fall last reception clock. (See 2.4, "Register Setting when Simple Mode", UART2-relevant register (4), Table Note that reception buffer read before rise last reception clock (during simple mode reception complete interrupt), reception data will read with positions altered. Relevant register UART2 special mode register (U2SMR 037716 address)
Simple mode Arbitration lost Each updated Each byte updated SCLL synchronization output denied SCLL synchronization output authorized
UART2 special mode register (U2SMR 037616 address)
IICM2 UART2 transmission/UART2 reception interrupt valid (CSC) Clock synchronization denied Clock synchronization authorized (SWC) clock output denied clock output authorized (ALS) output stop function denied output stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output denied
wait output authorized
(SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected. UART2 send/receive control register (U2C1: 037D16 address)
(TE) Transmission authorized (RI) Reception authorized (U2IRS) UART2 transmission interrupt cause selector Transmission buffer open (fall start bit) Transmission complete (rise last bit) (U2RRM) UART2 continuous reception denied (U2LCH) Data logic reversal (U2ERE) Error signal output denied
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Start Conditions/Stop Conditions
UART2 transmission interrupt control register (S2TIC 004F16) when transmission interrupt used.
(ILVL) Interrupt priority level interrupt level this (denied) when using interrupt. Will when interrupt request occurs. UART2 transmission interrupt control register (S2TIC 005016) when reception interrupt used.
(ILVL) Interrupt priority level interrupt level this (denied) when using interrupt. Will when interrupt request occurs. Timing pattern
UART2 transmission interrupt request occurs (when U2IRS
UART2 reception interrupt request occurs.
UART2 transmission interrupt request occurs (when U2IRS
Reception data read during this interval. UART2 reception buffer register (U2RB 037F16 037E16 addresses) (Transmission format: when fast)
Undefined first eight bits received data stored this way.
(Transmission format: when fast)
Undefined
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Start Condition/Stop Condition Detection
M16C/62 provided with "start condition/ stop condition detection interrupt" detect start conditions where changes from high when high, detect stop conditions when high goes from high. This interrupt allocated tosoftware interrupt number When mode selected ([IICM] =1), interrupt number causes changes "start condition/stop condition detection interrupt. Determine whether start stop condition occurred busy flag (BBS) when this interrupt detected. Please aware that start stop condition setup hold times vary from standartds. (See 4.1, "Start/stop condition setup hold times.) Relevant register UART2 special mode register (U2SMR 033716 address)
(IICM) Simple mode (ABC) Arbitration lost updated. byte (BBS) cleared when stop condition detected Start condition detected when (LSYN) synchronization output denied synchronization output authorized
collision detection interrupt control register (BCNIC 004A16 address)
(IIVL) Interrupt priority level interrupt level setup this (denied) when interrupt request occurs. (IR) when interrupt occurs. flag (when interrupt generated interrupt request) Timing pattern start condition stop condition
st/sp detected interrupt request occurs (BBS) occurs.
st/sp detected interrupt request occurs (BBS) occurs.
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Start Condition/Stop Condition
When M16C/62 used master, port control generates start conditions. simple mode M16C/62, transmission initial value becomes value that port p7_0 when serial control denied time port control), this function used. following example control that generates start condition.
Flow Chart Transmission start condition Port direction register (PD7 03FE16 address) terminal port input
with input (SDA terminal when p7_0 port control) with input (SCL terminal when p7_1 port control) UART2 send/receive mode register (U2MR: 037816 address) Serial valid. P7_0, P7_1 port control. Port 03ED16 address)
UART2 serial function denied (port control)
initial value setup
initial value This does become start condition since port P7_0 direction register with input. UART2 special mode register (U2SMR 037716 address)
mode (U2SMR register)
with simple mode UART2 send/receive mode register (U2MR 037816 address)
mode (U2MR register)
with simple mode (port control denied)
UART2 send/receive control register (U2C1 037D16 address) Transmission authorized Transmission authorized UART2 transmission buffer register (U2TB 037B16 address)
Transmission data written
Data transm initial value (p7_0 value transmitted, start condition generated, transmission data sent. released time
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Busy Detection
necessary confirm that open before sending start condition. M16C/62 simple mode, status detected with busy flag (BBS). When start condition detected, When stop condition detected, cleared Therefore, when equals when device attempts send start condition, device must wait start sending untl clears
Relevant register
(IICM) Simple mode (ABC) Arbitration lost Each updated Each byte updated (BBS) open (can only written (LSYN) synchronization output denied synchronization output authorized
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Start Condition/Stop Condition Terminal Output Function
maximum period cycles transmission clock (SCL) needed M16C/62 serial from when transmission data written into transmission buffer until transmission transmission clock (the simple mode). Also, there possibility that could caused (upper timing pattern) another device transmits first interval from time start condition generated until clock line (SCL) synchronization function (see 3.5, Communication Coordination) effective from first transmission. M16C/62 terminal L-output function prohibit clock transmissions from other devices after start condition. using this function, output from terminal other devices into wait status same time that data written into buffer (lower timing pattern). This function made operable assigning value wait output (SWC2), which output from SCL. function released making wait output equal
IICM2 Acknowledgement detected/not detected interrupt effective UART2 transmit/UART2 receive interrupt effective (CSC) Clock synchronization denied Clock synchronization authorized (SWC) clock output denied clock output authorized (ALS) output stop function denied output stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) outputs UART2 clock
output from (SCL terminal output function effective)
(SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected.
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Timing pattern When terminal output function used Writing transmitted data M16C/62 transmission
Other device's transmission
Maximum cycles normally happens
synchronization function valid
When terminal output function used Writing transmission data [SWC2] [SWC2]
M16C/62 transmission Maintains cycles greater
synchronization function valid
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Acknowledgement
acknowledgement added each byte transmission data. There must means, byte byte, receiving device detect whether there acknowledgement when M16C/62 being used transmission device. This hardware provided with "acknowledgement detection interrupt" "acknowledgement undetected interrupt." Also, acknowledgement easily generated setting transmission data when M16C/62 used receiving device one-to-one communication performed. (See 3.1, "Byte Data Reception Method.") mode selector (IICM2) must when "acknowledgement detection interrupt" "acknowledgement undetected interrupt" used. This setting makes interrupt numbers into "acknowledgement detection interrupt" acknowledgement undetected interrupt," respectively. this case, data transmission from UART2 reception register reception buffer register timed rise last reception clock. (See 2.4, "Register Setup When Simple Mode.")
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Acknowledgement Detected
reception device determine that acknowledgement occurred time rise transmission clock's when open line transmitting side level reaches "L." M16C/62 detect this condition with "acknowledgement detection interrupt" function. This interrupt assigned "software interrupt number 16." interrupt number interrupt cause "acknowledgement detection interrupt" case only when mode selected ([IICM] "1") mode selector [IICM2]= "0."
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reception device determine that acknowledgement occurred time rise transmission clock's ninth when open line transmitting side level reaches M16C/62 detect this condition with "acknowledgement detection interrupt" function. This interrupt assigned software interrupt number interrupt number causes "acknowledgement detection interrupt" this case only when mode selected ([IICM] mode selector [IICM2] Relevant registers UART2 special mode register (U2SMR 037716 address)
Simple mode Arbitration lost Each updated Each byte updated SCLL synchronization output denied SCLL synchronization output authorized
UART2 special mode register (U2SMR 037616 address)
IICM2 UART2 transmission/UART2 reception interrupt valid (CSC) Clock synchronization denied Clock synchronization authorized (SWC) clock output denied clock output authorized (ALS) output stop function denied output stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output denied
wait output authorized
(SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected. UART2 reception control register (S2RIC 005016 address) When acknowledgement detection interrupt used.
[ILVL] interrupt priority level; interrupt level setup [IR] when there interrupt request flag (when interrupt occurs because interrupt request) Timing pattern
Acknowledgement detected Interrupt request occurs
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Acknowledgement Undetected
reception device determine that acknowledgement occurred time rise transmission clock's ninth when open line transmitting side level reaches M16C/62 detect this condition with "acknowledgement undetected interrupt" function. This interrupt assigned software interrupt number interrupt number causes "acknowledgement undetected interrupt" this case only when mode selected ([IICM] mode selector [IICM2] Relevant registers UART2 special mode register (U2SMR 037716 address)
Simple mode Arbitration lost Each updated Each byte updated SCLL synchronization output denied SCLL synchronization output authorized
UART2 special mode register (U2SMR 037616 address)
IICM2 UART2 transmission/UART2 reception interrupt valid (CSC) Clock synchronization denied Clock synchronization authorized (SWC) clock output denied clock output authorized (ALS) output stop function denied output stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output denied
wait output authorized
(SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected. UART2 reception control register (S2RIC 005016 address) When acknowledgement detection interrupt used.
[ILVL] interrupt priority level; interrupt level setup [IR] when there interrupt request flag (when interrupt occurs because interrupt request) Timing pattern
Acknowledgement undetected Interrupt request occurs
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Own-address Designation Determination
reception device determine that acknowledgement occurred time rise transmission clock's ninth when open line transmitting side level reaches M16C/62 detect this condition with "acknowledgement undetected interrupt" function. interrupt assigned software interrupt number interrupt number causes "acknowledgement undetected interrupt" this case only when mode selected ([IICM] mode selector [IICM2]
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Terminal Output Function
With bus, designated slave's address sent first byte after start condition detected (when seven-bit address mode). slave must compare with address reception data first seven bits tthe clock sent another master first byte perform processing generate generate), synchronizing acknowledgement clock's ninth bit. M16C/62 terminal output function perform this processing. using this function, M16C/62's terminal outputs timed SCL's ninth after receiving data first eight bits, forcing master into waiting status. Then after software completes address comparison processing, port control generate generate acknowledgement. (See 3.1, "Byte Data Reception Method" one-to-one communications other where address reception acknowledgement generation performed. Permission this function given setting wait output [SWC] denied setting Also when terminal with this function, function released setting [SWC] When address comparison processing performed with this function, contents reception buffer read prior rise last clock, aware fact that location reception data which been read changed. (See 3.1, "Transmission Interrupt/Reception Interrupt", timing pattern.) Relevant register UART2 special mode register (U2SMR2: 037616 address)
IICM2 UART2 transmission/UART2 reception interrupt valid (CSC) Clock synchronization denied Clock synchronization authorized (SWC) clock output authorized (ALS) output stop function denied output stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output denied
wait output authorized
(SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected.
Timing pattern
M16C/62 output
fixed. [SWC] Address comparison processing Fixed released setting [SWC]
IICM2 hour UART2 reception interrupt request occurs.
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Example Address Recognition
There types address designation formats: 7-bit addresses 10-bit addresses. Although following example 7-bit address recognition, same kind control used recognize 10-bit addresses. This example shows generation byte reception interrupt after reception start bit. Here, [SWC] (SCL terminal L-output function authorization), already before receiving byte, only portion reception interrupt routine shown.
Example main routing settings (SCL terminal L-output function authorization) IICM (interrupt cause #16: UART2 reception interrupt, interrupt generation timing: rise last bit) S2RIC (UART2 reception interrupt authorization) Flag (interrupt authorized) UART2 reception buffer register Acquisition reception data
Flow Chart
Reception interrupt first byte
(U2RB 037F16, 037E16)
Reception data Does slave address address? SCL, terminal port levels. (SDA="L") Port 03ED16 address) Slave address
terminal output release [SWC]=0
terminal terminal (Input/output settings when port control)
REIT terminal port input terminal port output.
UART2 Serial valid
Port direction register 03EF16 address)
terminal output port terminal input port (Input/output settings when port control) sent UART2 reception buffer register (U2MR 037816 address)
port control [SWC]=0
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Communication Coordination
possible that more than master could generate start condition attempt start sending data same time arbitration occurrence), when used multiplexed master. this case, communication coordination performed between masters system. M16C/62 simple mode, hardware provided with "arbitration lost detection function" "SDA output prohibition function time arbitration lost occurrence" order recover communications when there arbitration lost occurrence. Also, "SCL synchronization function" provided apart from arbitration lost means communication coordination using clock synchronization.
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Communication Coordination Arbitration Lost Detection Function
M16C/62 simple mode arbitrartion lost detection flag (ABT). This detection flag located UART2 reception buffer register. arbtration lost detection flag (SBT) when internal data level level agree time rise, indicating error. arbitration lost detction flag control (ABC) updates arbitration lost detection flag select bits bytes (1). flag (ABC) when both mode selector (IICM) mode selector (IICM2) Output becomes input becomes when acknowledgement received arbitration lost detection flag ends being set. Therefore, time next transmission, perform sending after arbitration lost detection flag clears
Relevant register UART2 reception buffer register (U2RB: 037F16 address)
Reception data (ABT) detected (victory) Detected (defeat) (Only written.)
UART2 special mode register (U2SMR: 037716 address)
(IICM) Simple mode (ABC) Arbitration lost: Updates Updates byte (ABC) when (IICM) (IICM2) (LYSYN) Denies SCLL synchronous output Authorizes SCLL synchronous output
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Communication Coordination Output Prohibition Function Time Arbitration Lost Occurrence
output masters that have detected arbitration lost must turned that time. M16C/62 simple mode select function that automatically turns with hardware when there arbitration lost occurrence. This function authorized setting output stop (ALS) denied setting this When output turned with this function, function released clearing either output stop (ALS) arbitration detection (ABT) before sending byte data, since arbitration lost determined have occurred output turned off, even timing acknowledgement. Also, arbitration detection flag control (ABC) Relevant register UART2 special mode register (U2RB: 037616 address)
IICM2 Acknowledgement detected/not detected interrupt invalid UART2 transmission/UART2 transmission interrupt valid (CSC) Clock synchronization denied Clock synchronization authorized (SWC) wait output denied 1:SCL clock output authorized (ALS) ouput stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output denied
wait output authorized
(SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected. Timing pattern
Arbitration lost occurrence output M16C/62 output
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Communication Coordination
When M16C/62 connected slower device, other device L-hold clock sent from master into forced waiting status. M16C/62 simple mode synchronization function that automatically enters wait status response L-hold from other device that also releases wait status releasing L-hold. operation this function authorized setting clock synchronization (CSC) This function should used only when M16C/62 master (internal clock mode). Relevant register UART2 special mode register (U2SMR2: 037616 address)
IICM2 Acknowledgement detected/not detected interrupt invalid UART2 transmission/UART2 transmission interrupt valid (CSC) Clock synchronization denied Clock synchronization authorized (SWC) wait output denied 1:SCL clock output authorized (ALS) ouput stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output denied
wait output authorized
Timing pattern terminal (SDHI) output authorized output denied (high impedance) (SHTC) This must when mode selected.
M16C/62 internal Normally M16C/62 internal outputs terminal fall count starts L-interval. UART2 clock
Even M16C/62 internal this interval count stopped this interval, since terminal
Although M16C/62 internal terminal remains since M16C/62 clock
synchronization functions work during this interval. Transmission data writing
Synchronization Function
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Other Functions
addition functions described above, M16C/62 simple mode provided with following hardware designed make control easier.
L-Synchronized Output Function
M16C/62 simple mode L-synchronized output function. This function authorized setting L-synchronized output authorization (LSYN) denied setting setting L-synchronized output authorization (LSYN) terminal synchronized level going P7_1 data register (the port assigned terminal) reset This function valid when SCL/SDA used ports (when serial mode selector (SMD0, SMD1, SMD2 000) invalid serial mode. This function used transmit first-byte acknowledgement M16C/62 slave receiver, normally should terminal L-output function instead.
Relevant registers
UART2 reception mode register (U2MR: 037816 address)
(SMD) 000: Port control 010: Simple (serial I/O) mode (CKDIR) Selects external clock (when slave) (IOPOL) reversal polarity
UART2 special mode register (U2SMR: 037716 address)
(IICM) Simple mode (ABC) Update Update byte (LSYN) Authorizes SCLL synchronized output
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Communication Coordination Output Prohibition Function
When M16C/62 used slave, M16C/62 must turn output (high impedance), address designated master different from address when address determined after reception start condition. this case, turned M16C/62's setting transmission buffer register 1FFh every ninth clock each occurrence reception interrupt request). Also, output turned even output prohibition function provided with M16C/62 used. function made valid setting output prohibition (SDHI) that M16C/62`s output high impedance, even transmission buffer register 1FFh. This function released setting (SDHI) that value that synchronized transmission buffer output next input. Relevant register
UART2 reception mode register (U2SMR2: 037616 address)
(IICM2) Acknowledgement detected/not detected interrupt valid UART2 transmission/UART2 transmission interrupt valid (CSC) Clock synchronization denied Clock synchronization (SWC) wait output denied clock output authorized (ALS) output stop function authorized (STAC) UART2 initialization denied UART2 initialization authorized (SWC2) wait output2 denied wait output authorized (SDHI) output authorized output denied (high impedance (SHTC) This must when mode selected.
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Communication Coordination UART2 Initialization Function
M16C/62 simple mode provided with function that automatically initializes UART2 time when start condition detected. function used when M16C/62 slave. This function authorized setting start condition initialization (STAC) denied setting following initialization performed when start condition detected: transmission register initialized contents transmission buffer register transferred transmission register. doing, there need reset data transmission register when data received. Transmission begins with input next clock first bit. Note, however, that should prohibit output transmission data setting output prohibition (SDHI) since this transmission data identical last transmission data. receiving register initialized next clock input first bit, thus starting reception. Overrun errors occur, even though initialization reception timed begin prior reading reception buffer register. wait output (SWC) doing, terminal L-output function becomes valid output from terminal fall ninth transmission clock.
this function only when external clock been selected. Also aware that transmission buffer open flag's value does change this function used UART2 transmission started. Relevant register UART2 special mode register (U2SMR2: 037616 address)
[IICM2] Acknowledgement detected/not detected interrupt valid UART2 transmission/UART2 transmission interrupt valid [CSC] Clock synchronization denied. Clock synchronization authorized. [SWC] wait output denied. clock output authorized. [ALS] output stop function authorized. [STAC] UART2 initialization denied. UART2 initialization authorized. [SWC2] SCLwait output2 denied. wait output authorized. [SHDI] output authorized. output denied (high impedance) [SHTC] This must when mode selected.
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Chapter
Precautions Concerning Simple Mode
Please observe following precautions restrictions protocol control when using M16C/62 simple mode.
Chapter Section Title Electrical Characteristics Maximum Transmission Speed Limits with Count Source
Electrical Characteristics
There difference electrical characteristics M16C/62 with standard: (See Standard, "I2C Line Characteristics")
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Start/Stop Condition Setup Time/Hold Time
M16C/62 setup hold times vary from standard values when start/stop conditions detected (when high-speed mode). During start/stop conditions, M16C/62 setup hold times detected having following values. (Note
Start condition
Stop condition
Setup time Setup time cycles (Note
Hold time Hold time cycles (Note Note sure start/stop condition SHTG Note number cycles indicates main clock input oscillation frequency f(XIN) number cycles.
high-speed mode, standard start/stop condition setup hold times minimum nanoseconds. contrast, M16C/62 ssetup/hold time minimum cycles (f(XIN) cycles). Therefore, when main clock (f(XIN) used MHz, M16C/62 simple mode setup/hold time minimum nanoseconds handle high-speed mode standard. However, setup hold times longer satisfy highspeed mode standard when main clock used less than MHz.
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Electrical Characteristics Level/High Level Input Voltages
electrical characteristics M16C/62 when runs 2.7V~5.5V are: input voltage (VIH) min. (guaranteed level) input voltage (VIL) max. (guaranteed level) Therefore, these different from standard values Running Running other than 1.5V 0.7V, 0.3V
Also, when M16C/62 output voltage 5mA: output voltage (VOL) max. 2.0V (guaranteed level) Which different from standard value output voltage (VOL) max. 0.6V (when 6mA) However, standard M16C/62 characteristics when 5mA: output voltage (VOL) 0.6V.
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Electrical Characteristics Data Hold Time
provision minimum 300ns hold time signal signal min.), requested order fill undefined region fall width standard. However, M16C/62, TxDi hold time min.0ns 300ns hold time requested standard generated internally.
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Maximum Transmission Speed Limits with Count Source
time takes M16C/62 recognize level depends sampling cycle. maximum count source clocks needed. Therefore, maximum transmission speed connected M16C/62 simple limited according operating frequency bits count source speed. There danger transmission speeds satisfy following conditions: maximum transmission speed (Hz) count source (Hz) Example: Source oscillation 10Hz, with count source fc32 selected:
maximum transmission speed (Hz) 10MHz)32 104Kbps (BRG count source) this example, maximum transmission speed 104Kbps.
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Appendix Reference Programs
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Appendix Reference Programs
conclusion, present reference programs used when sending receiving performed using M16C/62 simple mode multi-master. These programs guarantee communication operations, please evaluate them fully when using them.
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Appendix Soft Control Specification Contents
Summary. Explanation functions Address Transmission speed. Transmission data length. Multi-master. Explanation hardware. Method use. build Memory used. Function. Communication methods. 4.4.1 Preparations 4.4.2 Master communications. 4.4.3 Slave communications. Evaluation. Program list
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Appendix
Reference Programs Summary
This software controls simple mode hardware installed M16C/62 series, enabling communications protocol. communications protocol based upon following conditions: Operating conditions Source frequency: 10MHz (non-wait, frequency divider) Specification restrictions1 assumed that line locked. line locked, this software's processing will also lock will impossible restore user's program. recommend line monitoring recovery processing from lock status (such watchdog timer), upper level applications deal with this issue. Comm unication with slave units having 10-bit addresses supported. C-BUS, M3L-BUS, other interchangeable protocols supported. reuse comm unication formats that have restart conditions which switch over slaves. (These will bring about communication abnormalities.)
Explanation functions Address
Master Device Sending receiving with slaves having 7-bit addresses. Slave Device 7-bit address Note: Sending/receiving with special addresses (such general call addresses), supported.
Transmission Speed
Transmission speeds between 0~100Kbps, device cannot communicate with high-speed mode masters. this program, 15us software wait inserted until synchronization function becomes valid when start condition sent. This assumes communication 100Kbps. Change timing software wait insertion when communication takes place speeds other than 100Kbps.
Could typo "Use restrictions." [translator]
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Transmission Data Length
Master Device
send/receive data between bytes length.
Slave Device
Operates same 24LC01 (E2PROM supporting 128-byte bus). However, soft optionally device address with user program. This function primarily other masters which connected bus, there status provided Also, advantage permitting writing reading device into this domain without going through bus.
Multi-Master
Data relayed from several devices which connected other devices. However, cannot composite formats master. (This because restart condition cannot generated.) Therefore, E2PROM random access reading cannot performed between M16C/62s which doing control same bus.
Explanation Hardware
Only M16C/62 UART2 internal simple hardware used order implement protocol. Choose pullup resistance which most appropriate system.
M16C/62
SCL(29) UART2 SDA(30) Simple hardware mode
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Method Build
User Program Include i2c.h, since function provided soft used. ncrt.a30 _Add following descriptions final section entries near region. doing, will establish location used soft byte region. .section iicbus,data,align ,Add following interrupt vectors: Software interrupt number (bus collision detection interrupt) .glb stsp_int .lword stsp_int Software interrupt number (UART2 reception interrupt) .glb u2rcv_int .lword u2rcv_int i2cbus.a30 Sets maximum interrupt level used soft bus. second place i2cbus.a30 IICIPL .equ Enter descriptions area. soft bus, X-1~X used. Please select most appropriate value since there strong relationship between value communication speed execution speed. possible that larger value higher communication speed, there also chance that interrupt prohibition time would extended. This program uses UART2 reception interrupt collision detection; interrupt levels relate each other follows: UART2 reception interrupt level collision detection interrupt level Both interrupts have same priority level, software interrupt denied status, they also detect stop conditions, performing following operations when collision detection interrupt UART2 reception interrupt occur reception byte next frame.
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UART2 reception interrupts executed order priority according hardware priority when interrupt authorized from status outlined above, then collision detection interrupt processing executed. this case, difficult determine whether frame received previously (which ended collision detection), normal not. these reasons, UART2 reception interrupt level level lower than collision interrupt, allowing collision detection interrupt processing performed priority basis. Access Denied Register change following registers:
ress
Name Register collision detection interrupt register UART2 transmission interrupt control register UART2 reception interrupt control register UART2 special mode register UART2 special mode register UART2 send/receive mode register UART2 transmission speed register UART2 transmission buffer register UART2 send/receive control register UART2 send/receive control register UART2 reception buffer Port Port direction register
Note:When registers combining access denied bits authorization bits written, bset, bclr commands, etc., command write-operate complete method.
Memory Used
size size data stack Interrupt stack bytes bytes bytes 1,239 bytes
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Functions provided soft
Function1
including i2c.h, following functions used: void iic_ini(unsigned char unsigned char *E2PROM) Functionality: Performs initialization processing transmission with bus. device operates slave this processing completed status such that interrupt authorized. other hand, device will operate master following functions which start master transmitting/ receiving called: Stack used: bytes Arguments: address address last bits addresses other than special addresses. *E2PROM leading address used E2PROM. Prepare unsigned char-type array global variable bytes size with user program, that leading address. Return values: None Other: Interrupts denied while this being executed. unsigned char iic_stop(void) Functionality: Halts send/receive functions. send/receive functions halted with functions during slave transmitting/receiving. However, transmitting/receiving functionality cannot halted. soon function used halt transmitting/receiving, transmitting/receiving operations cannot started, even function starting master transmitting receiving functionality called, since communication operations taking place. will need call iic_ini want restart transmitting/receiving functionality. Stack used: bytes Arguments: None Return values: transmitting/receiving functionality able halted. transmitting/receiving functionality could halted since device itself master. Other: Interrupts denied while this being executed.
unsigned char iic_mr_start(unsigned char MR_LNG, unsigned char*MR_DATA, unsigned char MR_SLAVE) Functionality: Starts master reception. will need usable status with iic_ini this function. Stack used: bytes. Arguments: MR_LNG: Designates data length received master. (Note that means bytes.) *MR_DATA: Designates leading address stored data received master. MR_SLAVE: Designates device which want have receive data. Indicate address slave device latter bits. upper reflected. Return values:0 Reception master begun. Reception master begun being busy. (Does
mathematical function [the translator]
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M16C/62 Specification (ABB)
Other:
perform retry.) Interrupts denied while this being executed.
unsigned char iic+mw_start(unsigned char MW_LNG, unsigned char *MW_DATA, unsigned char MW_SLAVE Functionality: Starts master reception will need usable status with iic_ini this function. Stack usage: bytes Arguments: MR_LNG: Designates data length received master. (Note that means bytes.) *MR_DATA: Designates leading address stored data received master. MR_SLAVE: Designates device which want have receive data. Indicate address slave device latter bits. upper reflected. Return values:0 Reception master begun. Reception master begun being busy. (Does perform retry.) Other: Interrupts denied while this being executed.
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Soft Functions Made User following functions called soft arguments transmit/ receive status data number. user must provide these functions soft bus. void iic_mw_end(unsigned char MW_STATUS,unsigned char MW_LNG Functionality: Uses following arguments inform user master's transmission complete status: Stack usage: bytes (interrupt stack) auto variable function itself. Arguments: MW_STATUS: Indicates completion master's transmission. Master transmission completed normally. Slave returned NACK first byte. Slave returned NACK data region. competition detected master operation completed. Improper start condition detected. Improper stop condition detected. MW_LNG: Indicates master reception data number. Return values:None Other: Calls made from within soft interrupt processing. void iic_mr_end(unsigned char MR_STATUS,unsigned char MR_LNG Functionality: Uses following arguments inform user master's transmission complete status: Stack usage: bytes (interrupt stack) auto variable function itself. Arguments: MR_STATUS: Indicates completion master's reception. Master reception completed normally. Slave returned NACK first byte. Slave returned NACK data region. competition detected master operation completed. Improper start condition detected. Improper stop condition detected. MW_LNG: Indicates master reception data number. Return values:None Other: Calls made from within soft interrupt processing.
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4.4.1
Communication Methods Preparation
program operation initial stage, following iic_ini calls needed initial routine order perform communications. this point, makes difference whether flag interrupts permitted during execution iic_ini. arguments transferred when iic_ini called. first argument indicates device's address, while those arguments after this receive slave assignments from other masters. designate functional address device's address. argument designates region leading address used salve transmission/ reception. Therefore, will need this region before issuing iic_ini call. Reserve bytes static variable region near attributes region.
Example:
//global variable declarator unsigned char iic_ram[128] tion. System initialization processing iic_ini(0x54,iic_ram); //RAM region used slave transmission recep//global variable which becomes like static variable //I2C=BUS initialization //Own address 1010100b //iic_ram leading address I-flag
asm("fset I");
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4.4.2
Master Communications Master Transmission
iic_mw_start called start master transmission. Three arguments transferred when iic_mw_start called. first argument sets transmission length. setting indicates maximum transmission data length, sending bytes. second argument designates leading address transmission data storage destination. this transmission data storage destination released until master transmission complete, transmission data storage destination assigned anywhere near attribute region. third argument designates transmission counterpart address. designate functional address transmission counterpart address. Also, iic_mw_start return values, returned when master transmission starts, returned does start. following example shows 5-byte data transmission from iic_ram slave device which address called 5516:
Example:
!=0) //master transmission failure confirmation processing else //master transmission start confirmation processing When master transmission complete, soft calls iic_mw_end. user must create this function. arguments transferred when soft calls iic_mw_end. first argument indicates completion master transmission. Section shows status contents. second argument indicates actual number data transmitted. following example iic_mw_end.
M16C/62 Specification (ABB)
12/9/98
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Master Reception
iic_mw_start called start master transmission. Three arguments transferred when iic_mw_start called. first argument sets transmission length. setting indicates maximum transmission data length, sending bytes. second argument designates leading address transmission data storage destination. this transmission data storage destination released until master transmission complete, transmission data storage destination assigned anywhere near attribute region. third argument designates transmission counterpart address. designate functional address transmission counterpart address. Also, iic_mw_start return values, returned when master transmission starts, returned does start. following example shows 5-byte data transmission from iic_ram slave device which address called 5516: Example: !=0) //master transmission failure confirmation processing else //master transmission start confirmation processing
[translator's note: this page duplicates page
M16C/62 Specification (ABB)
12/9/98
Page
When master reception complete, soft calls iic_mr_end. user must create this function. arguments transferred when soft calls iic_mr_end. first argument indicates completion master transmission. second argument shows actual number data received. following example iic_mr_end.
4.4.3
Slave Communications
controlled same 24LC01 (E2PROM supporting 128-byte bus). However, differs that device address (with exception functional address) freely chosen, that address increment 128-bytes linear.
M16C/62 Specification (ABB)
12/9/98
Page
Evaluation
recommend that when evaluate device that line following i2cbus.a30 file follows that logic analyzer check operational performance. unused ports lines ports stated here output with your user program initialization. (Port this example.) execution time software varies according system with which integrated, this method check actual execution time (interrupt prohibited time).
M16C/62 Specification (ABB)
12/9/98
Page
keep safety first your circuit designs Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) non-flammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Mitsubishi semiconductor product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Mitsubishi Electric Corporation third party. Mitsubishi Electric Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts circuit application examples contained these materials. information contained these materials, including product data, diagrams charts, represent information products time publication these materials, subject change Mitsubishi Electric Corporation without notice product improvements other reasons. therefore recommended that customers contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor latest product information before purchasing product listed herein. Mitsubishi Electric Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Mitsubishi Electric Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations JAPAN and/or country destination prohibited. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor further details these materials products contained therein.

M16C/62 Group Application Note (Tentative) Mitsubish

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