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MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER FAMILY 7470 SERIES 747


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MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER FAMILY 7470 SERIES
7470/7471 7477/7478
Group
User's Manual
keep safety first your circuit designs Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) non-flammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Mitsubishi semiconductor product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Mitsubishi Electric Corporation third party. Mitsubishi Electric Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts circuit application examples contained these materials. information contained these materials, including product data, diagrams charts, represent information products time publication these materials, subject change Mitsubishi Electric Corporation without notice product improvements other reasons. therefore recommended that customers contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor latest product information before purchasing product listed herein. Mitsubishi Electric Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Mitsubishi Electric Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations JAPAN and/or country destination prohibited. Please contact Mitsubishi Electric Corporation authorized Mitsubishi Semiconductor product distributor further details these materials products contained therein.
Preface
This user's manual describes Mitsubishi's CMOS 8-bit microcomputers 7470/7471/7477/7478 group. After reading this manual, user should have through knowledge functions features 7470/7471/7477/7478 group, should able fully utilize product. manual starts with specifications ends with application examples. detailes software, refer "SERIES MELPS 740<SOFTWARE> USER'S MANUAL." details development support tools, refer "DEVELOPMENT SUPPORT TOOLS MICROCOMPUTERS" data book.
BEFORE USING THIS USER'S MANUAL
Organization
This user's manual consists following three chapters. Refer chapter appropriate your conditions, such hardware design software development. CHAPTER HARDWARE This chapter describes features microcomputer operation each peripheral function. CHAPTER APPLICATION This chapter describes usage application examples peripheral functions, based mainly setting examples related registers. CHAPTER APPENDIX This chapter includes list registers, necessary information systems development using microcomputer, masking confirmation (mask version), programming confirmation, mark specifications which submitted when ordering.
Structure Register
figure each register structure describes functions, contents reset, attributes follows:
(Note
mode register
Bits
mode register (CPUM) [Address: Name Stack page selection
attributes
(Note
Contents immediately after reset release
Function
reset
these bits "0." page area page area Nothing allocated this bit. This write enabled undefined reading. P50, P50, P51/XCIN, XCOUT selection CIN, XCOUT XCOUT drive capacity High selection Main clock IN-XOUT) stop Internal system clock selection Oscillates Stops IN-XOUT selected (Ordinary mode) CIN-XCOUT selected (low-speed mode)
which nothing arranged Note Contents immediately after reset release reset release reset release Undefined reset release Note attributes
Read Read enabled Undefined reading reading reading
Write Write enabled Write disabled to"0". cleared software "1".
Table contents
Table contents
CHAPTER HARDWARE
Description Group expansion Performance overview configuration 1-10 description 1-14 Functional block diagram 1-17 Central processing unit (CPU) 1-23 1.7.1 Accumulator 1-24 1.7.2 Index register (X), Index register 1-24 1.7.3 Stack pointer 1-24 1.7.4 Program counter (PC) 1-26 1.7.5 Processor status register (PS) 1-26 Access area 1-28 1.8.1 Zero page (Addresses 0000 00FF 1-29 1.8.2 Special page (Addresses FF00 FFFF 1-29 Memory allocation 1-30 1.10.1 port 1-35 1.10.2 Port block diagram 1-40 1.10.3 Notes 1-45 1.11 Interrupts 1-48 1.11.1 Description interrupt source 1-48 1.11.2 Operation description 1-52 1.11.3 Interrupt control 1-55 1.11.4 Notes 1-57 1.11.5 Related registers 1-59 1.12 Timers 1-62 1.12.1 Operation description 1-64 1.12.2 Description modes 1-65 1.12.3 Input latch function 1-79 1.12.4 Updating contents Timer Timer latch 1-80 1.12.5 Notes 1-82 1.12.6 Related registers 1-83 1.13 Serial 1-89 1.13A 7470/7471 group part 1-90 1.13A.1 Operation description 1-90 1.13A.2 Byte specification mode 1-98 1.13A.3 Pins 1-101 1.10 pins 1-35
7470/7471/7477/7478 GROUP USER'S MANUAL
Table contents
1.13A.4 Notes 1-101 1.13A.5 Related registers .1-102 1.13B 7477/7478 group part 1-105 1.13B.1 Operation description 1-105 1.13B.2 Pins 1-127 1.13B.3 Notes 1-128 1.13B.4 Related registers .1-131 1.14 converter 1-139 1.14.1 conversion method 1-140 1.14.2 Pins 1-144 1.14.3 Notes 1-144 1.14.4 References .1-145 1.14.5 Related registers .1-147 1.15 Reset. 1-149 1.15.1 Operation description 1-149 1.15.2 Internal status immediately after reset release 1-151 1.15.3 Notes 1-152 1.16 Oscillation circuit 1-153 1.16.1 Oscillation circuit .1-153 1.16.2 Sub-clock oscillation circuit 1-155 1.16.3 Oscillation operation .1-156 1.16.4 Oscillation stabilizing time 1-158 1.16.5 Notes 1-159 1.17 Low-power dissipation function 1-160 1.17.1 Stop mode 1-162 1.17.2 Wait mode 1-166 1.17.3 Notes 1-169 1.17.4 Related register 1-170 1.18 State transitions 1-171 1.19 Built-in PROM version .1-175 1.19.1 EPROM mode .1-176 1.19.2 description 1-182 1.19.3 Writing, reading, erasing built-in PROM 1-185 1.19.4 Notes 1-186 1.20 Electrical characteristics .1-188 1.20.1 Electrical characteristics 1-188 1.20.2 Timing requirements, switching characteristics 1-200 1.20.3 Power source current standard characteristics 1-202 1.20.4 Port standard characteristics 1-207 1.20.5 conversion standard characteristics 1-212
7470/7471/7477/7478 GROUP USER'S MANUAL
Table contents CHAPTER APPLICATION
pins 2.1.1 port 2.1.2 Notes Interrupts 2.2.1 Memory allocation 2.2.2 Processor status register (PS) .2-8 2.2.3 Application example 2.2.4 Notes Timers 2-10 2.3.1 Memory allocation 2-10 2.3.2 Application example 2-11 2.3.3 Notes 2-22 Serial 2-23 2.4.1 7470/7471 group memory allocation 2-23 2.4.2 Application example 2-24 2.4.3 7477/7478 group memory allocation 2-29 2.4.4 Application examples 2-30 2.4.5 Notes 2-34 converter 2-35 2.5.1 Memory allocation 2-35 2.5.2 Application examples 2-36 2.5.3 Notes 2-38 Reset 2-39 2.6.1 Reset circuit 2-39 2.6.2 Notes 2-39 Oscillation circuit 2-40 Low-power dissipation function 2-41 2.8.1 mode register 2-41 2.8.2 Application examples 2-42 2.8.3 Notes 2-47 Countermeasures against noise 2-48 2.9.1 Shortest wiring length 2-48 2.9.2 Connection bypass capacitor across line line 2-51 2.9.3 Wiring analog input pins 2-51 2.9.4 Consideration oscillator 2-52 2.9.5 Setup ports 2-53 2.9.6 Providing watchdog timer function software 2-54 2.10 Notes programming 2-56 2.10.1 Processor status register 2-56 2.10.2 Decimal calculations 2-57 2.11 Differences between 7470/7471 group 7477/7478 group 2-58
7470/7471/7477/7478 GROUP USER'S MANUAL
Table contents
2.12 Example application circuit 2-59
CHAPTER APPENDIX
Control registers Mask ordering method .3-14 programming ordering method 3-34 Mark specification form 3-46 Package outline 3-51 memory 3-53 configuration 3-54
7470/7471/7477/7478 GROUP USER'S MANUAL
List tables
List tables
CHAPTER HARDWARE
Table 1.2.1 List supported products Table 1.3.1 Performance overview 7470 group .1-6 Table 1.3.2 Performance overview 7471 group .1-7 Table 1.3.3 Performance overview 7477 group .1-8 Table 1.3.4 Performance overview 7478 group .1-9 Table 1.5.1 description 1-14 Table 1.5.2 description 1-15 Table 1.5.3 description 1-16 Table 1.8.1 Addressing mode accessible each area 1-29 Table 1.9.1 area 1-30 Table 1.9.2 area 1-30 Table 1.10.1 Port register address allocation 1-36 Table 1.10.2 Termination unused pins 1-47 Table 1.11.1 Interrupt sources priority 1-48 Table 1.11.2 Interrupt control bits individual interrupt sources 1-55 Table 1.12.1 Modes each timer 1-62 Table 1.12.2 Setting count stop 1-67 Table 1.12.3 Setting timer count source 1-67 Table 1.12.4 Setting timer count source 1-67 Table 1.12.5 Setting timer count source 1-68 Table 1.12.6 Setting timer count source 1-68 Table 1.12.7 Address allocation Timer 1-68 Table 1.12.8 Count start setting 1-68 Table 1.12.9 Event counter mode setting 1-71 Table 1.12.10 Pulse output mode initial value setting 1-73 Table 1.12.11 Pulse output mode setting 1-73 Table 1.12.12 External pulse width measurement mode setting 1-76 Table 1.12.13 Edge polarity selection register setting 1-79 Table 1.12.14 Frequency CNTR 1-82 Table 1.13.1 7470/7471 group 7477/7478 group serial 1-89 Table 1.13A.1 Serial transmit setting 1-94 Table 1.13A.2 Serial receive setting 1-97 Table 1.13B.1 Clock synchronous serial transmit setting 1-110 Table 1.13B.2 Clock synchronous serial receive setting 1-113 Table 1.13B.3 Baud rate reference value 1-116 Table 1.13B.4 Each function UART transmit data 1-117 Table 1.13B.5 UART transmit setting 1-122 Table 1.13B.6 value UART control register 1-122
7470/7471/7477/7478 GROUP USER'S MANUAL
List tables
Table 1.13B.7 UART receive setting 1-126 Table 1.13B.8 Error flag clear method 1-134 Table 1.13B.9 Transmit enable function. 1-136 Table 1.13B.10 Receive enable function. 1-137 Table 1.14.1 Setting conversion 1-143 Table 1.15.1 Timer reset 1-150 Table 1.17.1 State stop mode .1-162 Table 1.17.2 State wait mode .1-166 Table 1.19.1 7470/7471/7477/7478 group built-in PROM version supporting products 1-175 Table 1.19.2 functions EPROM mode 1-176 Table 1.19.3 description .1-182 Table 1.19.4 description .1-183 Table 1.19.5 description .1-184 Table 1.19.6 Input/Output signal each mode 1-185 Table 1.20.1 Absolute maximum ratings (7470 group) 1-188 Table 1.20.2 Recommended operating conditions (7470 group) 1-188 Table 1.20.3 Electrical characteristics (7470 group) 1-189 Table 1.20.4 converter characteristics (7470 group) 1-190 Table 1.20.5 Absolute maximum ratings (7471 group) 1-191 Table 1.20.6 Recommended operating conditions (7471 group) 1-191 Table 1.20.7 Electrical characteristics (7471 group) 1-192 Table 1.20.8 converter characteristics (7471 group) 1-193 Table 1.20.9 Absolute maximum ratings (7477 group) 1-194 Table 1.20.10 Recommended operating conditions (7477 group) 1-194 Table 1.20.11 Electrical characteristics (7477 group) 1-195 Table 1.20.12 converter characteristics (7477 group) 1-196 Table 1.20.13 Absolute maximum ratings (7478 group) 1-197 Table 1.20.14 Recommended operating conditions (7478 group) 1-197 Table 1.20.15 Electrical characteristics (7478 group) 1-198 Table 1.20.16 converter characteristics (7478 group) 1-199 Table 1.20.17 Timing requirements switching characteristics (7470/7471 group) 1-200 Table 1.20.18 Timing requirements switching characteristics (7477/7478 group) 1-201
CHAPTER APPLICATION
Table 2.1.1 Port register memory allocation Table 2.1.2 Port direction register memory allocation Table 2.1.3 ports that permit pull-up software Table 2.1.4 Double function port control register Table 2.3.1 Relation between timer-used pins modes 2-11 Table 2.11.1 Differences between 7470/7471 group 7477/7478 group 2-58
7470/7471/7477/7478 GROUP USER'S MANUAL
List figures
List figures
CHAPTER HARDWARE
Fig. 1.2.1 Memory expansion plan 7470/7471/7477/7478 group Fig. 1.4.1 configuration 7470 group 1-10 Fig. 1.4.2 configuration 7471 group 1-11 Fig. 1.4.3 configuration 7477 group 1-12 Fig. 1.4.4 configuration 7478 group 1-13 Fig. 1.6.1 M37470Mx/Ex-XXXSP functional block diagram 1-17 Fig. 1.6.2 M37471Mx/Ex-XXXSP, M37471E8SS functional block diagram 1-18 Fig. 1.6.3 M37471Mx/Ex-XXXFP functional block diagram 1-19 Fig. 1.6.4 M37477Mx/E8-XXXSP/FP functional block diagram 1-20 Fig. 1.6.5 M37478Mx/E8-XXXSP, M37478E8SS functional block diagram 1-21 Fig. 1.6.6 M37478Mx/E8-XXXFP functional block diagram 1-22 Fig. 1.7.1 Structure registers 1-23 Fig. 1.7.2 Register push interrupt generation subroutine call 1-25 Fig. 1.8.1 Access area 1-28 Fig. 1.9.1 Memory allocation 7470/7471 group 1-31 Fig. 1.9.2 Memory allocation 7477/7478 group 1-32 Fig. 1.9.3 Special function register (SFR) memory 1-33 Fig. 1.9.4 Interrupt vector memory 1-34 Fig. 1.10.1 port writing reading 1-36 Fig. 1.10.2 Structure Port direction register (i=0, 1-37 Fig. 1.10.3 Structure Port pull-up control register 1-38 Fig. 1.10.4 Structure Ports pull-up control register 1-39 Fig. 1.10.5 Block diagram Ports 1-40 Fig. 1.10.6 Block diagram Ports (7470/7471 group) 1-41 Fig. 1.10.7 Block diagram Ports (7477/7478 group) 1-42 Fig. 1.10.8 Block diagram Ports 1-43 Fig. 1.10.9 Block diagram Port 1-44 Fig. 1.11.1 Block diagram interrupt input key-on wake circuit 1-50 Fig. 1.11.2 Interrupt operation 1-52 Fig. 1.11.3 Changes contents Program counter Stack pointer upon acceptance interrupt 1-53 Fig. 1.11.4 Processing time execution interrupt processing routine 1-54 Fig. 1.11.5 Timing after acceptance interrupt 1-54 Fig. 1.11.6 Interrupt control diagram 1-55 Fig. 1.11.7 Example register setting 1-57 Fig. 1.11.8 Structure Edge polarity selection register 1-59 Fig. 1.11.9 Structure Interrupt request register 1-60 Fig. 1.11.10 Structure Interrupt request register 1-60
7470/7471/7477/7478 GROUP USER'S MANUAL
List figures
Fig. 1.11.11 Structure Interrupt control register 1-61 Fig. 1.11.12 Structure Interrupt control register 1-61 Fig. 1.12.1 Timer block diagram 1-63 Fig. 1.12.2 Timer count timing 1-64 Fig. 1.12.3 Example timer mode operation. 1-66 Fig. 1.12.4 Example event counter mode operation 1-70 Fig. 1.12.5 Example pulse output mode operation 1-72 Fig. 1.12.6 Example operation external pulse width measurement mode. 1-75 Fig. 1.12.7 Example operation output mode 1-78 Fig. 1.12.8 Example updating Timer Timer Timer latch 1-80 Fig. 1.12.9 Example updating Timer Timer Timer latch mode 1-81 Fig. 1.12.10 Relation between timer value change timing read value change timing 1-82 Fig. 1.12.11 Structure Timers .1-83 Fig. 1.12.12 Structure Timer mode register 1-84 Fig. 1.12.13 Structure Timer mode register 1-85 Fig. 1.12.14 Structure Timer mode register 1-86 Fig. 1.12.15 Structure Timer register 1-86 Fig. 1.12.16 Structure Input latch register 1-87 Fig. 1.12.17 Sturucture Edge polarity selection register. 1-88 Fig. 1.13A.1 Serial block diagram 1-90 Fig. 1.13A.2 Serial transmit operation 1-93 Fig. 1.13A.3 Serial transmit timing chart 1-93 Fig. 1.13A.4 Serial receive operation .1-96 Fig. 1.13A.5 Serial receive timing chart 1-96 Fig. 1.13A.6 Transmit/receive operation byte specification mode 1-99 Fig. 1.13A.7 Structure Serial register 1-102 Fig. 1.13A.8 Structure Serial counter Byte counter 1-103 Fig. 1.13A.9 Structure Serial mode register 1-104 Fig. 1.13B.1 Clock synchronous serial block diagram 1-105 Fig. 1.13B.2 Transmit operation clock synchronous serial 1-108 Fig. 1.13B.3 Transmit timing chart clock synchronous serial 1-109 Fig. 1.13B.4 Receive operation clock synchronous serial 1-112 Fig. 1.13B.5 Receive timing chart clock synchronous serial 1-112 Fig. 1.13B.6 UART block diagram 1-114 Fig. 1.13B.7 UART data format. 1-117 Fig. 1.13B.8 Transmit/receive format UART 1-118 Fig. 1.13B.9 Transmit operation UART 1-120 Fig. 1.13B.10 Transmit timing chart UART 1-121 Fig. 1.13B.11 Receive operation UART 1-124 Fig. 1.13B.12 Receive timing chart UART 1-125 Fig. 1.13B.13 Structure Transmit/receive buffer register 1-131 Fig. 1.13B.14 Structure Serial status register 1-132 Fig. 1.13B.15 Structure Serial control register 1-135
7470/7471/7477/7478 GROUP USER'S MANUAL
List figures
Fig. 1.13B.16 Structure UART control register 1-138 Fig. 1.14.1 converter block diagram 1-139 Fig. 1.14.2 Contents conversion register reference voltage during conversion 1-141 Fig. 1.14.3 Definition conversion precision 1-146 Fig. 1.14.4 Structure conversion register 1-147 Fig. 1.14.5 Structure control register 1-148 Fig. 1.15.1 Internal processing sequence after reset release 1-149 Fig. 1.15.2 Internal status immediately after reset release 1-151 Fig. 1.16.1 Clock generating circuit block diagram 1-153 Fig. 1.16.2 Oscillation stabilizing wait time after power 1-158 Fig. 1.17.1 Operation states microcomputer low-power dissipation 1-160 Fig. 1.17.2 State transition low-power dissipation 1-161 Fig. 1.17.3 Oscillation stabilizing wait time recovery from stop mode reset input 1-163 Fig. 1.17.4 Example recovery sequence from stop mode interrupt 1-165 Fig. 1.17.5 Reset input time 1-167 Fig. 1.17.6 Structure mode register 1-170 Fig. 1.18.1 State transitions 1-172 Fig. 1.19.1 connection EPROM mode 7470 group 1-176 Fig. 1.19.2 connection EPROM mode 7471 group 1-177 Fig. 1.19.3 connection EPROM mode 7471 group 1-178 Fig. 1.19.4 connection EPROM mode 7477 group 1-179 Fig. 1.19.5 connection EPROM mode 7478 group 1-180 Fig. 1.19.6 connection EPROM mode 7478 group 1-181 Fig. 1.19.7 Programming testing Time PROM version 1-187 Fig. 1.20.1 Timing chart (7470/7471 group) 1-200 Fig. 1.20.2 Timing chart (7477/7478 group) 1-201 Fig. 1.20.3 Power source current standard characteristics measuring circuit 1-202 Fig. 1.20.4 CC-V characteristics (f(X MHz, 7470/7471 group) 1-203 Fig. 1.20.5 CC-V characteristics (f(X MHz, 7470/7471 group) 1-203 Fig. 1.20.6 CC-V characteristics (f(X CIN) kHz, 7470/7471 group) 1-204 Fig. 1.20.7 CC-V characteristics (f(X MHz, 7477/7478 group) 1-205 Fig. 1.20.8 CC-V characteristics (f(X MHz, 7477/7478 group) 1-205 Fig. 1.20.9 CC-V characteristics (f(X CIN) kHz, 7477/7478 group) 1-206 Fig. 1.20.10 Port standard characteristic measuring circuits 1-207 Fig. 1.20.11 OH-VOH characteristics programmable port (CMOS output) P-channel side (7470/7471 group) 1-208 Fig. 1.20.12 OL-V characteristics programmable port (CMOS output) N-channel side (7470/7471 group) 1-208 Fig. 1.20.13 IL-V characteristics programmable port (CMOS output) pull-up transistor (7470/7471 group) 1-209
7470/7471/7477/7478 GROUP USER'S MANUAL
List figures
Fig. 1.20.14 IOH-V characteristics programmable port (CMOS output) P-channel side (7477/7478 group) 1-210 Fig. 1.20.15 -VOL characteristics programmable port (CMOS) N-channel side (7477/7478 group) 1-210 Fig. 1.20.16 -VIL characteristics programmable port (CMOS output) pull-up transistor (7477/7478 group) 1-211 Fig. 1.20.17 conversion standard characteristics, relative precision error 1-212 Fig. 1.20.18 conversion standard characteristics, relative precision error 1-213 Fig. 1.20.19 conversion standard characteristics, absolute precision error 1-214 Fig. 1.20.20 conversion standard characteristics, absolute precision error 1-215 Fig. 1.20.21 conversion standard characteristics, absolute precision error 1-216 Fig. 1.20.22 conversion standard characteristics, absolute precision error 1-217 Fig. 1.20.23 conversion standard characteristics, absolute precision error 1-218
CHAPTER APPLICATION
Fig. 2.1.1 Example port direction register setting. Fig. 2.1.2 Example external circuit design port Fig. 2.2.1 Memory interrupt related registers Fig. 2.2.2 Structure Processor status register Fig. 2.3.1 Memory timer related registers 2-10 Fig. 2.3.2 Example control procedure [Clock function] 2-13 Fig. 2.3.3 Example measurement method frequency 2-14 Fig. 2.3.4 Example control procedure [Frequency measurement] 2-15 Fig. 2.3.5 Example peripheral circuit [Pulse output mode] 2-16 Fig. 2.3.6 Connection timer setting division ratio 2-16 Fig. 2.3.7 Example control procedure [Piezoelectric buzzer output] 2-17 Fig. 2.3.8 Example peripheral circuit [Pulse width measurement mode] 2-18 Fig. 2.3.9 Example control procedure [Pulse width measurement mode] 2-19 Fig. 2.3.10 Example peripheral circuit [PWM mode] 2-20 Fig. 2.3.11 Example control procedure [PWM mode] 2-21 Fig. 2.3.12 Timing which timer value read value change case where timers connected series .2-22 Fig. 2.4.1 Memory serial related registers 7470/7471 group 2-23 Fig. 2.4.2 Example connections [Clock synchronous serial mode, 7470/7471 group] 2-24 Fig. 2.4.3 Example control procedure [Clock synchronous serial mode, 7470/7471 group] 2-25 Fig. 2.4.4 Example connections [Byte specification mode, 7470/7471 group] 2-26 Fig. 2.4.5 Example control procedure [Byte specification mode, 7470/7471 group] 2-27 Fig. 2.4.6 Example control procedure [Byte specification mode, 7470/7471 group] 2-28 Fig. 2.4.7 Memory serial related registers 7477/7478 group 2-29 Fig. 2.4.8 Example connections [Clock synchronous serial mode, 7477/7478 group] 2-30
7470/7471/7477/7478 GROUP USER'S MANUAL
List figures
Fig. 2.4.9 Example control procedure [Clock synchronous serial mode, 7477/7478 group] 2-31 Fig. 2.4.10 Example connections [Clock asynchronous serial mode, 7477/7478 group] 2-32 Fig. 2.4.11 Example control procedure [Clock asynchronous serial mode, 7477 /7478 group] 2-33 Fig. 2.5.1 Memory conversion related registers 2-35 Fig. 2.5.2 Example conversion control procedure 2-37 Fig. 2.5.3 Analog input internal equivalent circuit 2-38 Fig. 2.6.1 Example reset circuit 2-39 Fig. 2.7.1 Example Oscillation circuit using ceramic resonator 2-40 Fig. 2.7.2 Example external clock input circuit 2-40 Fig. 2.8.1 Structure mode register 2-41 Fig. 2.8.2 Example control procedure [Ordinary mode Stop mode Ordinary mode] 2-43 Fig. 2.8.3 Example control procedure [Ordinary mode Wait mode Ordinary mode] 2-44 Fig. 2.8.4 Example control procedure [Ordinary mode Low-speed mode] 2-45 Fig. 2.8.5 Example control procedure [Low-speed mode Ordinary mode] 2-46 Fig. 2.9.1 Wiring RESET 2-48 Fig. 2.9.2 Wiring clock pins 2-49 Fig. 2.9.3 Wiring Time PROM EPROM version 2-50 Fig. 2.9.4 Bypass capacitor across line line 2-51 Fig. 2.9.5 Analog signal line resistor capacitor 2-51 Fig. 2.9.6 Wiring large current signal line 2-52 Fig. 2.9.7 Wiring signal line where potential levels change frequently 2-52 Fig. 2.9.8 Setup ports 2-53 Fig. 2.9.9 Watchdog timer software 2-55 Fig. 2.10.1 Initialization flags 2-56 Fig. 2.10.2 Stack memory contents after instruction execution 2-56 Fig. 2.10.3 Note execute instruction 2-56 Fig. 2.10.4 Note decimal operation 2-57 Fig. 2.12.1 Application circuit example (cleaner) 2-59
CHAPTER APPENDIX
Fig. 3.1.1 Structure Port direction register Fig. 3.1.2 Structure Port pull-up control register Fig. 3.1.3 Structure Ports pull-up control register Fig. 3.1.4 Structure Edge polarity selection register Fig. 3.1.5 Structure Input latch register Fig. 3.1.6 Structure control register Fig. 3.1.7 Structure conversion register Fig. 3.1.8 Structure Serial mode register .3-5
7470/7471/7477/7478 GROUP USER'S MANUAL
List figures
Fig. 3.1.9 Structure Serial register Fig. 3.1.10 Structure Secial counter Byte counter Fig. 3.1.11 Structure Transmit/receive buffer register Fig. 3.1.12 Structure Serial status register Fig. 3.1.13 Structure Serial control register .3-8 Fig. 3.1.14 Structure UART control register Fig. 3.1.15 Structure Timers Fig. 3.1.16 Structure Timer register Fig. 3.1.17 Structure Timer mode register 3-10 Fig. 3.1.18 Structure Timer mode register 3-10 Fig. 3.1.19 Structure Timer mode register 3-11 Fig. 3.1.20 Structure mode register 3-11 Fig. 3.1.21 Structure Interrupt request register 3-12 Fig. 3.1.22 Structure Interrupt request register 3-12 Fig. 3.1.23 Structure Interrupt control register 3-13 Fig. 3.1.24 Structure Interrupt control register 3-13 Fig. 3.6.1 memory 3-69 Fig. 3.7.1 configuration 7470 group .3-70 Fig. 3.7.2 configuration 7471 group .3-71 Fig. 3.7.3 configuration 7477 group .3-72 Fig. 3.7.4 configuration 7478 group .3-73
7470/7471/7477/7478 GROUP USER'S MANUAL
CHAPTER HARDWARE
Description Group expansion Performance overview configuration description Functional block diagram Central processing unit (CPU) Access area Memory allocation 1.10 pins 1.11 Interrupts 1.12 Timers 1.13 Serial 1.14 converter 1.15 Reset 1.16 Oscillation circuit 1.17 Low-power dissipation function 1.18 State transitions 1.19 Built-in PROM version 1.20 Electrical characteristics
HARDWARE
Description
Description
7470/7471/7477/7478 group 8-bit single-chip microcomputer which utilizes silicon gate CMOS processing simple instruction system family using same memory space ROM, I/O.
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Group expansion
Group expansion
7470/7471/7477/7478 group develops with M37470M2-XXXSP base chip 7470 series. classification 7470 series follows. 7470 series 7470 7471 7477 7478 7480 7481 group group group group group** group**
**:Under development
this manual, when multiple models described collectively, their names arranged putting among them separation. 7470 group, 7471 group 7470/7471 group 7477 group, 7478 group 7477/7478 group 7470 group, 7477 group 7470/7477 group 7471 group, 7478 group 7471/7478 group
7470/7471/7477/7478 group permits group expansion shown Figure 1.2.1. This group expansion performed only differences memory type capacity number ports. This allows user select optimum elements according user's system. 7470/7471/7477/7478 group supports following addition mask version. Support Time PROM version Time PROM version programmable microcomputer perform one-time write operation built-in programmable (PROM). details, refer "1.19 Built-in PROM version." Support EPROM version (with window) built-in EPROM version programmable microcomputer with window perform write erase operations built-in EPROM. details, refer "1.19 Built-in PROM version." Support emulator emulator microcomputer designed program development which facilitates program development optimum element system evaluation. details, refer to"1.20 Emulator MCU." Table 1.2.1 shows products which 7470/7471/7477/7478 group supports.
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Group expansion
qMemory Expansion Plan 7470/7471 group
size (bytes) M37470M8/E8-XXXSP M37471M8/E8-XXXSP/FP M37471E8SS
M37470M4/E4-XXXSP M37471M4/E4-XXXSP/FP
M37470M2-XXXSP M37471M2-XXXSP/FP
size (bytes)
qMemory Expansion Plan 7477/7478 group
size (bytes) M37477M8/E8-XXXSP/FP M37478M8/E8-XXXSP/FP M37478E8SS
M37477M4-XXXSP/FP M37478M4-XXXSP/FP
size (bytes)
Fig. 1.2.1 Memory expansion plan 7470/7471/7477/7478 group
Dec. 1997)
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Group expansion
Table 1.2.1 List supported products Product M37470M2-XXXSP M37470M4-XXXSP M37470E4-XXXSP M37470M8-XXXSP M37470E8-XXXSP M37471M2-XXXSP M37471M2-XXXFP M37471M4-XXXSP M37471M4-XXXFP M37471E4-XXXSP M37471E4-XXXFP M37471M8-XXXSP M37471M8-XXXFP M37471E8-XXXSP M37471E8-XXXFP M37471E8SS M37471RSS M37477M4-XXXSP M37477M4-XXXFP M37477M8-XXXSP M37477M8-XXXFP M37477E8-XXXSP M37477E8-XXXFP M37478M4-XXXSP M37478M4-XXXFP M37478M8-XXXSP M37478M8-XXXFP M37478E8-XXXSP M37478E8-XXXFP M37478E8SS M37478RSS Port (bytes) (bytes) 4096 ports: (Including analog 8192 input pins.) 16384 Input ports: 4096 Package Dec. 1997) Remarks Mask version 32P4B Time PROM version Mask version Time PROM version Mask version
8192
16384
42P4B 56P6N-A 42P4B 56P6N-A 42P4B ports: (Including analog 56P6N-A 42P4B input pins.) 56P6N-A Input ports: 42P4B 56P6N-A 42S1B-A 42S1M 32P4B 32P2W-A 32P4B 32P2W-A 32P4B 32P2W-A 42P4B ports: 56P6N-A (Including analog 42P4B 56P6N-A input pins.) 42P4B Input ports: 56P6N-A ports: 42S1B-A Input ports: (Including analog 42S1M input pins.) ports: (Including analog input pins.) Input ports:
Time PROM version Mask version Time PROM version EPROM version Emulator Mask version Mask version Time PROM version Mask version Mask version Time PROM version EPROM version Emulator
63.5K (Note) 8192
16384
8192
16384
16384 63.5K (Note)
Note: Address space usable area.
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Performance overview
Performance overview
Tables 1.3.1 1.3.4 show performance overview 7470/7471/7477/7478 group. Table 1.3.1 Performance overview 7470 group Functions Parameter basic instructions family multiplication Number basic instructions division instructions) (the minimum instructions, clock input Instruction execution time oscillation frequency) Clock input oscillation frequency (max.) 4096 bytes M37470M2 8192 bytes M37470M4/E4 Memory 16384 bytes M37470M8/E8 size bytes M37470M2 bytes M37470M4/E4 bytes M37470M8/E8 8-bit Input/ 8-bit Output 4-bit port 2-bit 4-bit Input 8-bit Serial 8-bit timer Timers common with timer) 8-bit channels) converter levels max. M37470M2 levels max. Subroutine nesting M37470M4/E4 levels max. M37470M8/E8 external interrupts, internal interrupts, software interrupt Interrupt Built-in circuit with internal feedback resistor external Clock generating circuit ceramic resonator quartz-crystal oscillator) (2.2 clock input oscillation frequency) Power source voltage clock input oscillation frequency) typ. Power dissipation clock input oscillation frequency) Input/Output Input/Output withstand voltage characteristics Output current (P0, CMOS 3-state) Operating temperature Device structure CMOS silicon gate Package 32-pin shrink plastic molded M37470Mx/Ex-XXXSP
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Performance overview
Table 1.3.2 Performance overview 7471 group Functions basic instructions family multiplication Number basic instructions division instructions) (the minimum instructions, clock input Instruction execution time oscillation frequency) Clock input oscillation frequency (max.) M37471M2 4096 bytes M37471M4/E4 8192 bytes Memory M37471M8/E8 16384 bytes size M37471M2 bytes M37471M4/E4 bytes M37471M8/E8 bytes 8-bit 8-bit Input/ 8-bit Output 4-bit port 4-bit Input 4-bit Serial 8-bit Timers 8-bit timer common with timer) converter 8-bit channels) M37471M2 levels max. Subroutine nesting M37471M4/E4 levels max. M37471M8/E8 levels max. Interrupt external interrupts, internal interrupts, software interrupt Built-in circuit with internal feedback resistor external Clock generating circuit ceramic resonator quartz-crystal oscillator) Built-in circuit with internal feedback resistor guartzSub-clock generating circuit crystal oscillator) (2.2 CC-2) clock input oscillation frequency) Power source voltage clock input oscillation frequency) typ. Power dissipation clock input oscillation frequency) Input/Output withstand voltage Input/Output characteristics Output current (P0, CMOS 3-state) Operating temperature Device structure CMOS silicon gate 42-pin shrink plastic molded M37471Mx/Ex-XXXSP Package 56-pin plastic molded M37471Mx/Ex-XXXFP 42-pin shrink ceramic M37471E8SS Parameter
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Performance overview
Table 1.3.3 Performance overview 7477 group Parameter Functions basic instructions family multiplication Number basic instructions division instructions) (the minimum instructions, clock input Instruction execution time oscillation frequency) Clock input oscillation frequency (max.) M37477M4 8192 bytes Memory M37477M8/E8 16384 bytes size M37477M4 bytes M37477M8/E8 bytes 8-bit Input/ 8-bit Output 2-bit port 4-bit Input 4-bit 8-bit (operable UART mode) Serial 8-bit timer Timers common with timer) 8-bit channels) converter level max. M37477M4 Subroutine nesting level max. M37477M8/E8 external interrupts, internal interrupts, software interrupt Interrupt Built-in circuit with internal feedback resistor external Clock generating circuit ceramic resonator quartz-crystal oscillator) (2.2 CC-2) clock input oscillation frequency) Power source voltage clock input oscillation frequency) typ. Power dissipation clock input oscillation frequency) Input/Output Input/Output withstand voltage characteristics Output current (P0, CMOS 3-state) Operating temperature CMOS silicon gate Device structure 32-pin shrink plastic molded M37477Mx/E8-XXXSP Package 32-pin plastic molded M37477Mx/E8-XXXFP
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Performance overview
Table 1.3.4 Performance overview 7478 group Parameter Number basic instructions Instruction execution time Clock input oscillation frequency M37478M4 Memory M37478M8/E8 size M37478M4 M37478M8/E8 Input/ Output port Input Serial Timers converter M37478M4 Subroutine nesting M37478M8/E8 Interrupt Clock generating circuit Sub-clock generating circuit Functions basic instructions family multiplication division instructions) (the minimum instructions, clock input oscillation frequency) (max.) 8192 bytes 16384 bytes bytes bytes 8-bit 8-bit 4-bit 8-bit 4-bit 4-bit 8-bit (operable UART mode) 8-bit timer common with timer) 8-bit channels) level max. level max. external interrupts, internal interrupts, software interrupt Built-in circuit with internal feedback resistor external ceramic resonator quartz-crystal oscillator) Built-in circuit with internal feedback resistor quartzcrystal oscillator) (2.2 clock input oscillation frequency) clock input oscillation frequency) typ. clock input oscillation frequency) (P0, CMOS 3-state) CMOS silicon gate 42-pin shrink plastic molded 56-pin plastic molded 42-pin shrink ceramic
Power source voltage
Power dissipation Input/Output Input/Output withstand voltage characteristics Output current Operating temperature Device structure M37478Mx/E8-XXXSP Package M37478Mx/E8-XXXFP M37478E8SS
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
configuration
configuration
Figures 1.4.1 1.4.4 show configuration "7470/7471/7477/7478 group." connections EPROM mode built-in programmable version, refer "Figures 1.19.1 1.19.6 connections EPROM mode."
CONFIGURATION (TOP VIEW)
P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XOUT
P33/CNTR P32/CNTR P31/INT1 P30/INT0 RESET
M37470M8-XXXSP M37470E8-XXXSP
Outline
32P4B (Note)
Note: M37470M2-XXXSP M37470M4/E4-XXXSP included 32P4B package. these products pin-compatible.
Fig. 1.4.1 configuration 7470 group
1-10
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
configuration
CONFIGURATION (TOP VIEW)
P17/SRDY P16/CLK P15/SOUT P14/SIN P13/T1 P12/T0 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XOUT P33/CNTR1 P32/CNTR0 P31/INT1 P30/INT0
RESET
M37471M8-XXXSP M37471E8-XXXSP M37471E8SS
P51/XCOUT P50/XCIN
Outline
42P4B (Note 42S1B-A (M37471E8SS)
P33/CNTR P32/CNTR0 P31/INT1 P30/INT0
P17/SRDY P16/CLK P15/SOUT
RESET
M37471M8-XXXFP M37471E8-XXXFP
P51/XCOUT P50/XCIN AVSS XOUT
P14/SIN P13/T1 P12/T0 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF
Outline
56P6N-A (Note
connection
Notes M37471M2-XXXSP M37471M4/E4-XXXSP included 42P4B package. these products pin-compatible. M37471M2-XXXFP M37471M4/E4-XXXFP included 56P6N-A package. these products pin-compatible. only differences between 42P4B package product 56P6N-A package product package shape, absolute maximum ratings fact that 56P6N-A package product AVSS pin.
Fig. 1.4.2 configuration 7471 group
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
configuration
CONFIGURATION (TOP VIEW)
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XOUT
P33/CNTR P32/CNTR P31/INT1 P30/INT0
RESET
M37477M8-XXXSP M37477E8-XXXSP
Outline
32P4B (Note
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XOUT
P33/CNTR P32/CNTR P31/INT1 P30/INT0
RESET
M37477M8-XXXFP M37477E8-XXXFP
Outline
32P2W-A (Note
Notes M37477M4-XXXSP included 32P4B package. These products pin-compatible. M37477M4-XXXFP included 32P2W-A package. These products pin-compatible. only differences between 32P4B package product 32P2W-A package product package shape absolute maximum ratings.
Fig. 1.4.3 configuration 7477 group
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
configuration
CONFIGURATION (TOP VIEW)
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XOUT Outline
P33/CNTR P32/CNTR P31/INT1 P30/INT0
RESET
42P4B (Note 42S1B-A M37478E8SS)
P33/CNTR P32/CNTR0 P31/INT1 P30/INT0
M37478M8-XXXSP M37478E8-XXXSP M37478E8SS
P51/XCOUT P50/XCIN
P17/SRDY P16/SCLK P15/TXD
RESET
M37478M8-XXXFP M37478E8-XXXFP
P51/XCOUT P50/XCIN AVSS XOUT
P14/RXD P13/T1 P12/T0 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF Outline 56P6N-A (Note
connection
Notes M37478M4-XXXSP included 42P4B package. These products pin-compatible M37478M4-XXXFP included 56P6N-A package. These products pin-compatible only differences between 42P4B package product 56P6N-A package product package shape, absolute maximum ratings fact that 56P6N-A package product AVSS pin.
Fig. 1.4.4 configuration 7478 group
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
description
description
Tables 1.5.1 1.5.3 show description. functions EPROM mode built-in programmable version, refer "1.19.2 description." Table 1.5.1 description Name Power source Input/ Output Functions Apply following voltage pin: (2.2 VCC-2) clock input oscillation frequency) clock input oscillation frequency). Apply pin. Ground level input converter. Apply same voltage AVSS pin. Note: This dedicated 56P6N-A package products among 7471/7478 group. Reference voltage input converter. When using converter, apply [V]. When using converter, connect Reset input microcomputer into reset state keeping RESET more, and_ reset state released returning RESET "H." input output main clock generating circuit. Connect ceramic resonator quartz-crystal oscillator between pins XOUT feedback resistor incorporated between XOUT pins. external clock input, connect clock oscillation source leave open. Port 8-bit port. output structure CMOS output. input mode, pull-up transistor connectable units bit. input mode, key-on wake function provided.
Analog power source
Reference voltage input
Input
RESET
Reset input
Input
Clock input
Input
Clock output
Output
0-P0
port
1-14
7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
description
Table 1.5.2 description -P17 Name port Input/ Output Functions Port 8-bit port. output structure CMOS output. input mode, pull-up transistor connected units 4-bit. Pins common with timer output pins respectively. case 7470/7471 group, -P17 common with serial pins SOUT CLK, respectirely. case 7470/7471 group, outputs pins SOUT SRDY N-channel open drain outputs. case 7477/7478 group, -P17 common with serial pins CLK, RDY, respectively. Port 8-bit port. output structure CMOS output. input mode, pull-up transistor connected units 4-bit. Pins -P27 common with analog input pins -IN7 respectively. Note: 7470 group only pins 0-P23 0-IN3 Port 8-bit input port. impossible connect pull-up transistor. Pins -P27 common with analog lnput pins -IN7 respectively. Note: 7477 group only pins 0-P23 0-IN Port 4-bit input port. Pins common with external interrupt input pins INT1 respectively. Pins P32, common with timer input pins CNTR0 CNTR1 respectively. Port 4-bit port. output structure CMOS output. input mode, pull-up transistor connected units 4-bit. Note: 7470/7477 group only pins
-P27
port (7470/7471 group)
Input port (7477/7478 group)
Input
-P33
Input port
Input
-P43
port
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
description
Table 1.5.3 description 0-P5 Name Input port Input/ Output Input Functions Port 4-bit input port. Pull-up transistor connected units 4-bit. Pins common with input/output pins sub-clock generating circuit XCIN, COUT respectively. When using pins pins XCIN COUT connect quartz-crystal oscillator between pins COUT. When using pins pins COUT, feedback resistor connected between pins COUT. external clock input, connect clock oscillation source leave COUT open. Note: Only 7471/7478 group pins -P53.
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7470/7471/7477/7478 GROUP USER'S MANUAL
M37470M8/E8-XXXSP BLOCK DIAGRAM
Clock input
Clock output XOUT Data
Reset input
RESET
Clock generating circuit (Note 16384 bytes Instruction decoder Timer 2(8) Control signal Index register X(8) Index register Y(8) Timer 3(8) Timer 4(8) control Stack pointer S(8) Timer 1(8) bytes Program counter PCH(8) Program counter Instruction register(8) (Note
Functional block diagram
Fig. 1.6.1 M37470MX -XXXSP functional block diagram
Byte counter(4) INT1 converter Serial I/O(8) P3(4) P2(4) P1(8) P0(8) CNTR0 INT0
functional block diagram 7470/7471/7477/7478 group shown Figure 1.6.1 Figure 1.6.6.
7470/7471/7477/7478 GROUP USER'S MANUAL
8-bit Arithmetic logical unit
Accumulator A(8)
Processor status register PS(8)
CNTR1
P4(2)
VREF Input port
Reference voltage input
port
port
port
port
HARDWARE
Notes 4096 bytes M37470M2-XXXSP, 8192 bytes M37470M4/E4-XXXSP bytes M37470M2-XXXSP, bytes M37470M4/E4-XXXSP
Functional block diagram
1-17
1-18
Reset input
RESET
M37471M8/E8-XXXSP, M37471E8SS BLOCK DIAGRAM
Clock input
Clock output XOUT Data
HARDWARE
Clock generating circuit (Note 16384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Index register Y(8) Timer 3(8) Timer 4(8) control Stack pointer S(8) Timer 1(8) Instruction decoder bytes Program counter PCH(8) Program counter Instruction register(8) (Note
Functional block diagram
XCIN
XCOUT
8-bit Arithmetic logical unit
Accumulator A(8)
Byte counter(4) INT1 converter Serial I/O(8) P3(4) P2(8) P1(8) P0(8) CNTR1 CNTR0 INT0
XCOUT
Fig. 1.6.2 M37471M -XXXSP, M37471E8SS functional block diagram
7470/7471/7477/7478 GROUP USER'S MANUAL
XCIN
P5(4)
P4(4)
VREF Input port Reference voltage input port port port
Input Port
port
Notes 4096 bytes M37471M2-XXXSP, 8192 bytes M37471M4/E4-XXXSP bytes M37471M2-XXXSP, bytes M37471M4/E4-XXXSP
M37471M8/E8-XXXFP BLOCK DIAGRAM
Clock input Reset input
RESET
Clock output XOUT
AVSS Data
Clock generating circuit (Note bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Timer 3(8) Timer 4(8) control Index register Y(8) Stack pointer S(8) Program counter PCH(8) Program counter PCL(8) 16384 bytes Timer 1(8) Instruction decoder Instruction register(8) (Note
XCIN
XCOUT
Fig. 1.6.3 M37471MX -XXXFP functional block diagram
Byte counter(4) INT1 converter Serial I/O(8) P3(4) P2(8) P1(8) P0(8) CNTR1 CNTR0 INT0
8-bit Arithmetic logical unit
Accumulator A(8)
7470/7471/7477/7478 GROUP USER'S MANUAL
XCOUT
XCIN
P5(4)
P4(4)
VREF Input port Reference voltage input port port port
Input port
port
HARDWARE
Notes 4096 bytes M37471M2-XXXFP, 8192 bytes M37471M4/E4-XXXFP bytes M37471M2-XXXFP, bytes M37471M4/E4-XXXFP
Functional block diagram
1-19
1-20
Reset input
RESET
M37477M8/E8-XXXSP/FP BLOCK DIAGRAM
Clock input
Clock output XOUT Data
HARDWARE
Clock generating circuit (Note bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Timer 3(8) Timer 4(8) control Index register Y(8) Stack pointer S(8) Program counter PCH(8) Program counter 16384 bytes Timer 1(8) Instruction decoder Instruction register(8) (Note
Functional block diagram
Fig. 1.6.4 M37477M X/E8-XXXSP/FP functional block diagram
INT1 converter Serial I/O(8) P3(4) P2(4) P1(8) P0(8) CNTR1 CNTR0 INT0
7470/7471/7477/7478 GROUP USER'S MANUAL
8-bit Arithmetic logical unit
Accumulator A(8)
P4(2)
VREF Input port Reference voltage input Input port port port
port
Notes 8192 bytes M37477M4-XXXSP/FP bytes M37477M4-XXXSP/FP
M37478M8/E8-XXXSP, M37478E8SS BLOCK DIAGRAM
Clock input Reset input
RESET
Clock output XOUT
Clock generating circuit (Note bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Timer 3(8) Timer 4(8) control Index register Y(8) Stack pointer S(8) Program counter PCH(8) Program counter PCL(8) 16384 bytes Timer 1(8) Instruction decoder Instruction register(8) (Note
XCIN
XCOUT
8-bit Arithmetic logical unit
Accumulator A(8)
XCOUT converter CNTR1 P3(4) P2(8) CNTR0 INT0
INT1
Fig. 1.6.5 M37478MX /E8-XXXSP, M37478E8SS functional block diagram
Serial I/O(8)
7470/7471/7477/7478 GROUP USER'S MANUAL
P1(8)
XCIN
P5(4)
P4(4)
P0(8)
VREF Input port Reference voltage input Input port port port
Input port
port
HARDWARE
Notes 8192 bytes M37478M4-XXXSP bytes M37478M4-XXXSP
Functional block diagram
1-21
1-22
Reset input
RESET
M37478M8/E8-XXXFP BLOCK DIAGRAM
Clock input
Clock output XOUT AVSS Data
HARDWARE
Clock generating circuit (Note 16384 bytes Timer 2(8) Control signal Processor status register PS(8) Index register X(8) Index register Y(8) Timer 3(8) Timer 4(8) control Stack pointer S(8) Timer 1(8) Instruction decoder bytes Program counter PCH(8) Program counter PCL(8) Instruction register(8) (Note
Functional block diagram
XCIN
XCOUT
Fig. 1.6.6 M37478M X/E8-XXXFP functional block diagram
INT1 converter Serial I/O(8) P3(4) P2(8) P1(8) P0(8) CNTR1 CNTR0 INT0
8-bit Arithmetic logical unit
Accumulator A(8)
XCOUT
7470/7471/7477/7478 GROUP USER'S MANUAL
XCIN
P5(4)
P4(4)
VREF Input port Reference voltage input Input port port port
Input port
port
Notes 8192 bytes M37478M4-XXXFP bytes M37478M4-XXXFP
HARDWARE
Central processing unit (CPU)
Central processing unit (CPU)
7470/7471/7477/7478 group following registers (referred "CPU registers"). Accumulator 8-bit Index register 8-bit Index register 8-bit Stack pointer 8-bit Processor status register (PS) 8-bit Program counter (PC) 16-bit
high-order 8-bit low-order (PCL 8-bit
Figure 1.7.1 shows structure registers.
Accumulator
Index Register
Index Register
Stack Pointer
Program Counter
Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index Mode Flag Overflow Flag Negative Flag
Fig. 1.7.1 Structure registers
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
Central processing unit (CPU)
register states provided immediately after hardware reset described below. interrupt disable flag Processor status register (PS) "1." high-order bits (PCH) Program counter (PC) become contents address FFFF16 low-order bits become contents address FFFE contents other registers undefined, sure initialize registers with program. 1.7.1 Accumulator Accumulator central microcomputer 8-bit register. This accumulator used arithmetic operations, data transfer, temporary storage, condition judgment, general-purpose register with highest frequency use. 1.7.2 Index register (X), Index register Index register Index register 8-bit registers. addressing mode using these Index registers, value resulting from adding contents this register operand becomes real specified address. This addressing mode used make reference subroutine table memory table. Index registers provided with increment, decrement, comparison data transfer functions also used simplified accumulator. Index register when index mode flag Processor status register "1," contents Index register become operand address. 1.7.3 Stack pointer Stack pointer 8-bit register which used call subroutine generate interrupt. branch from routine being executed subroutine interrupt processing routine, necessary temporarily store (push) memory return address termination this processing. Usually, internal used push destination, this area called stack area. stack pointer indicates address stack area which data will pushed next. Figure 1.7.2 shows push operation stack area register operation from Stack area register. Program counter registers other than Processor status register automatically pushed. Accordingly, sure push necessary registers with program. instruction instruction used push operations Accumulator instruction instruction used push operations Processor status register. 7470/7471/7477/7478 group, page page available stack area. Select stack page (bit mode register (address 00FB16 which will described later ("0" page page). some products whose capacity bytes less, does exist page, sure this "0." stack pointer undefined state immediately after hardware reset. sure initialize destroy data arranged area.
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Central processing unit (CPU)
On-going routine
When interrupt accepted Interrupt request (Note) M(S) M(S) When subroutine called Execute M(S) (PCH) (S)-1 (PCL (S)-1 (PS) (S)-1
Push contents Processor status register stack Push return address stack
M(S)
Push return address stack
(PCH) (S)-1 (S)-1
Interrupt Service Routine
M(S)
Flag from Fetch Jump Vector
Execute Subroutine (PS) Execute
return address from stack
(S)+1 M(S) (S)+1 M(S) (S)+1 M(S)
contents Processor status register from stack
(PCL)
return address from stack
(S)+1 M(S) (S)+1 M(S)
(PCH)
Operation instructed software Operation which automatically performed hardware
Note Condition acceptance interrupt
Interrupt disable flag (enable state) Interrupt enable (enable state)
Fig. 1.7.2 Register push interrupt generation subroutine call
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
Central processing unit (CPU)
1.7.4 Program counter (PC) Program counter 16-bit counter consisting 8-bit register 8-bit register PCL. This counter indicates address which next instruction executed stored. contents this counter automatically pushed stack when subroutine called interrupt occurs. high-order bits (PCH) program counter become contents address FFFF16 loworder bits (PCL become contents address FFFE16 immediately after hardware reset. 1.7.5 Processor status register (PS) Processor status register 8-bit register consisting flags indicate state immediately after arithmetic processing flags determine operation CPU. Each Processor status register described below. Carry flag carry flag holds carry borrow from arithmetic logical unit after arithmetic processing. This flag also changed Shift instruction Rotate instruction. This flag instruction cleared instruction. Zero flag zero flag when arithmetic processing data transfer result cleared other cases. decimal operation mode, this flag invalidated. There instruction change contents this flag. Interrupt disable flag interrupt request flag disables instructions (except interrupt instruction). When this flag "1," interrupt disable state provided. This flag accepting interrupt, thereby disabling multi-interrupt. This flag instruction cleared instruction. This flag (interrupt disable state) immediately after hardware reset. Decimal mode flag decimal mode flag determines whether addition subtraction should performed binary decimal notation. When contents this flag "0," ordinary binary operation performed. When they "1," arithmetic operation performed assuming that word 2-digit decimal number. decimal operation, decimal compensation automatically performed (decimal operation performed only instruction instruction). This flag instruction cleared instruction. This flag undefined state immediately after hardware reset. this flag directly affects arithmetic operations, sure initialize Break flag break flag identifies whether interrupt been caused instruction. instruction used program debugging performs same operation interrupt performed executing instruction. Processor status register pushed stack, after flag automatically case instruction interrupt, after flag automatically cleared case other interrupts. There instruction change contents this flag.
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Central processing unit (CPU)
Index mode flag When Index mode flag "0," arithmetic operations performed between Accumulator memory. When this flag "1," direct arithmetic operations direct data transfer between memory another, between memory I/O, between another without passing through accumulator. arithmetic operation result between memory directly specified Index register memory specified operand stored into memory When flag When flag Denotes arithmetic operation Content accumulataor Contents memory directly specified Index register Contents memory specified operand
This flag instruction cleared instruction. This flag undefined state immediately after hardware resetting. This flag direct effect arithmetic operations. Accordingly, sure initialize Overflow flag contents overflow flag have significance when addition subtraction performed assuming that word signed binary number. When addition subtraction result exceeds range +127 -128, this flag "1." When instruction executed other cases, contents executed memory into overflow flag. This flag cleared instruction, there instruction this flag "1." decimal operation mode, this flag invalidated. Negative flag negative flag when arithmetic processing data transfer result negative (bit "1"). contents executed memory into this flag when instruction executed. There instruction change contents this flag. decimal operation mode, this flag invalidated.
7470/7471/7477/7478 GROUP USER'S MANUAL
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HARDWARE
Access area
Access area
7470/7471/7477/7478 group, ROM, various control registers located same memory area. Accordingly, same instructions used data transfer arithmetic operations without discriminating between memory I/O. Program counter consists bits access space 64K-byte memory area: addresses 0000 FFFF area least significant bytes (addresses 0000 00FF called "zero page," memories with high frequency such internal RAM, ports timers located here. area most significant bytes (addresses FF00 FFFF16 called "special page," internal interrupt vectors located here. zero page special page accessed with bytes using each special addressing mode. Figure 1.8.1 shows outline accsess area.
000016
00C016 00FF16
Zero page
area
FF0016
Special page
FFFF16
Interrupt vector area
Fig. 1.8.1 Access area
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7470/7471/7477/7478 GROUP USER'S MANUAL
HARDWARE
Access area
1.8.1 Zero page (Addresses 0000 00FF area bytes from addresses 0000 00FF called zero page. internal special function register (SFR) located this area. specify memory register this area, addressing mode shown Table 1.8.1. this area, especially, possible access this area shorter instruction cycle using zero addressing mode. 1.8.2 Special page (Addresses FF00 FFFF area bytes from addresses FF00 FFFF16 called special page. internal interrupt vector area located this area. specify memory subroutine this area, addressing mode shown Table 1.8.1. this area, especially, possible jump this area shorter instruction cycle using special page addressing mode. Ordinary, subroutines with high frequency located this area. Table 1.8.1 Addressing mode accessible each area Addressing mode (bytes required) Zero page Zero page indirect Zero page Zero page Zero page Zero page relative Absolute Absolute Absolute Relative Indirect Indirect Indirect Special page Zero page reference Special page reference Other area reference
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Memory allocation
Memory allocation
Figure 1.9.1 Figure 1.9.2 show memory allocation 7470/7471/7477/7478 group. memories, I/Os others located access area explained below. internal located each area shown Table 1.9.1. internal used data storage area stack area subroutine call interrupt occurrence. When used stack area, careful about subroutine nesting depth interrupt levels that data destroyed. Special function register (SFR) (Addresses 00C016 00FF area from addresses 00C0 00FF16 assigned (Special Function Register). Various control registers such ports, timers, serial I/Os, converters interrupts located this SFR. Figure 1.9.3 shows special function register (SFR)memory map. internal located each area shown Table 1.9.2. internal used store data tables programs. internal ROM, vector area store jump destination addresses upon reset occurrence interrupt assigned addresses FFEA16 FFFF16 7470/7471 group addresses FFE816 FFFF16 7477/7478 group. Figure 1.9.4 shows interrupt vector memory map. Table 1.9.1 area Product Range M3747xM2 Addresses 0000 007F16 M3747xM4/E4 Addresses 0000 00BF16 M3747xM8/E8 Addresses 0000 00BF16, Addresses 0100 01BF Table 1.9.2 area Product Memory type M3747xM2 Mask M3747xM4 Mask M3747xE4 Programmable M3747xM8 Mask M3747xE8 Programmable
Memory size 8-bit 8-bit 8-bit
Range Addresses F000 FFFF Addresses E00016 FFFF Addresses C00016 FFFF
Memory size 8-bit 8-bit 8-bit
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Memory allocation
M37470M2 M37471M2
000016 007F16 00C0 00FF16 (128 bytes) used area 000016 007F16
M37470M4/E4 M37471M4/E4
(192 bytes) 000016 007F16
M37470M8/E8 M37471M8/E8
(192 bytes) Zero page area (192 bytes)
00C0 00FF16
area
00C0 00FF 010016
01BF16
used
used
used
C00016
E00016
F00016
(4096 bytes)
(8192 bytes) FF0016 FFEA16 Interrupt vector area FFFF16
(16384 bytes) FF00 FFEA16 Interrupt vector area FFFF16 Special page
FF0016 FFEA16 Interrupt vector area FFFF16
Fig. 1.9.1 Memory allocation 7470/7471 group
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Memory allocation
M37477M4 M37478M4
000016 007F16 00C016 00FF16 (192 bytes)
M37477M8/E8 M37478M8/E8
000016 007F16 00C0 00FF16 010016 (192 bytes) Zero page area (192 bytes)
area
01BF16
used
used
C00016
E00016
(8192 bytes) FF0016 FFE816 FFFF16
Interrupt vector area
(16384 bytes) FF0016 FFE816 Interrupt vector area FFFF16 Special page
Fig. 1.9.2 Memory allocation 7477/7478 group
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00C0 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16
Port Port direction register Port Port direction register Port Port direction register (Note Port Port Port direction register Port (Note
Port pull-up control register
Port P1-P5 pull-up control register (Note
Edge polarity selection register Input latch register
control register conversion register Serial mode register Serial register Serial counter Byte counter
(Note
00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Transmit/receive buffer register Serial status register Serial control register UART control register Baud rate generator
(Note
Timer Timer Timer Timer
Timer register Timer mode register Timer mode register Timer mode register mode register Interrupt request register Interrupt request register Interrupt control register Interrupt control register
Notes 7477/7478 group, this register located. 7470/7477 group, this register located. This address allocated P1-P4 pull-up control register 7470/7477 group. 7477/7478 group, this register located. 7470/7471 group, this register located.
Fig. 1.9.3 Special function register (SFR) memory
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FFEA FFEB FFEC16 FFED16 FFEE FFEF FFF0 FFF1 FFF2 FFF3 FFF4 FFF5 FFF6 FFF7 FFF8 FFF9 FFFA FFFB FFFC FFFD FFFE FFFF
instruction interrupt
conversion completion interrupt
Serial interrupt Timer interrupt Timer interrupt Timer interrupt Timer interrupt
CNTR0 interrupt CNTR interrupt INT1 interrupt wake interrpt
INT0 interrupt RESET
FFE8 FFE9 FFEA16 FFEB16 FFEC16 FFED16 FFEE16 FFEF FFF0 FFF1 FFF2 FFF3 FFF4 FFF5 FFF6 FFF7 FFF8 FFF9 FFFA FFFB FFFC16 FFFD16 FFFE FFFF
instruction interrupt
conversion completion interrupt
Serial transmit interrupt Serial receive interrupt Timer interrupt Timer interrupt Timer interrupt Timer interrupt
CNTR0 interrupt CNTR interrupt INT1 interrupt wake interrpt
INT0 interrupt RESET
7470/7471 group
7477/7478 group
Fig. 1.9.4 Interrupt vector memory
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1.10 pins
1.10 pins
7470/7471/7477/7478 group provided with following pins. port Reset input RESET) Clock input/output XCIN COUT) convesion reference voltage input (VREF Power supply voltage input (VCC, Notes 7470/7477 group provided with port pins COUT AVSS dedicated 56P6N-A package product. outline each pin, refer "1.5 description." 1.10.1. port port writing reading input-only programmable port input port values (pin states) which input input-only programmable port input port read reading Port register corresponding each port. When data written into Port register corresponding each port, only written Port register effect state. programmable port output port value written into Port register corresponding programmable port output port output outside transistor. When Port register corresponding each port been read, each state read value written into Port register read. Accordingly, output voltage been reduced output voltage been increased external load, previous output value correctly read. Figure 1.10.1 shows port writing reading Table 1.10.1 shows port register address allocation.
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1.10 pins
input write operation enabled Port register. Each state read reading Port register.
output output value writing Port register. Port register read out.
Port direction register
level output Port direction register
Port register (When Writing) Port register
Port register (When Reading)
level output
channel transistor channel transistor cut-off state.
Fig. 1.10.1 port writing reading
Table 1.10.1 Port register address allocation Port register Address 00C0 00C2 00C4 00C6 00C8 (Note) 00CA Note: 7470/7477 group provided with
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Input/output selection programmable ports input/output selection programmable ports made Port direction register corresponding each port. Figure 1.10.2 shows structure Port direction register. Note: Each direction register initialized into reset, that ports into input state.
Port direction register
Port direction register (PiD) 0,1,2,4) [Address 00C1 00C316, 00C5 00C9 Name Function Port input mode Port output mode Port input mode Port output mode Port input mode Port output mode Port input mode Port output mode Port input mode Port output mode Port input mode Port output mode Port input mode Port output mode Port input mode Port output mode
reset
Port direction register
Notes 7477/7478 group provided with port direction register (input only). Port provided below: group bits group bits
Fig. 1.10.2 Structure Port direction register (i=0,
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1.10 pins
Pull-up control When input been selected Port direction register, pull-up control exerted units shown Table 1.10.1 Port pull-up control register (address 00D0 Port P1-P5 pull-up control register* (address 00D1 this time, control exerted turning pull-up transistor. Port P1-P4 pull-up control register arranged 7470/7477 group. Note: Ports other than cannot controlled one-bit units. example, when pulled (pull-up control units bits), also pulled Figure 1.10.3 shows structure Port pull-up control register, Figure 1.10.4 shows structure Port P1-P5 pull-up control register.
Port pull-up control register
Port pull-up control register [Address 00D0 Name Port pull-up control Port pull-up control Port pull-up control Port pull-up control Port pull-up control Port pull-up control Port pull-up control Port pull-up control Function pull-up Pull-up pull-up Pull-up pull-up Pull-up pull-up Pull-up pull-up Pull-up pull-up Pull-up pull-up Pull-up pull-up Pull-up
reset
Fig. 1.10.3 Structure Port pull-up control register
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Ports pull-up control register
Ports pull-up control register [Address 00D1 Name Ports pull-up control Ports pull-up control Ports pull-up control (Note Function
reset
pull-up Pull-up pull-up Pull-up pull-up Pull-up Ports pull-up pull-up control (Notes Pull-up Ports pull-up pull-up control (Note Pull-up Nothing allocated this bit. This write disabled undefined reading. Ports pull-up pull-up control (Note Pull-up Nothing allocated this bit. This write disabled undefined reading.
Notes 7470/7477 group, Pull-up control register provided. 7477/7478 group, nothing allocated these bits. They undefined reading. 7470/7477 group, nothing allocated these bits. They undefined reading. 7470/7477 group provided with only
Fig. 1.10.4 Structure Ports pull-up control register
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1.10 pins
1.10.2 Port block diagram Figure 1.10.5 Figure 1.10.9 show block diagram ports.
Port
Pull-up control register
Direction register
Data
Port latch
Port
Port
Data
Interrupt control circuit
Pull-up control register
T34M7
Direction register
Data
Port latch
Port
T12M3
Direction register
Data
Port latch
Port
Direction register
Data
Port latch
Port
Direction register
Data
Port latch
Port
Tr1-Tr5 pull-up transistors
Fig. 1.10.5 Block diagram Ports
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1.10 pins
Port P14-P17
Direction register
Data
Port latch
Port
SRDY
Direction register
Data
Port latch
Port
output
input
Direction register
Data
Port latch
Port
SOUT
Direction register
Data
Port latch
Port
Data
Pull-up control register
Tr6-Tr9 pull-up transistors
Fig. 1.10.6 Block diagram Ports (7470/7471 group)
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1.10 pins
Port P14-P17
SIOE SIOM SRDY
Direction register
Data
Port latch
Port
SRDY SIOE SIOM SIOE
Direction register
Data
Port latch
Port
SCLK output SIOE
SCLK input
Direction register
Data
Port latch
Port
SIOE
Direction register
Data
Port latch
Port
Data
Pull-up control register
Tr6-Tr9 pull-up transistors
Fig. 1.10.7 Block diagram Ports (7477/7478 group)
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1.10 pins
Port (7470/7471 group)
Control units 4-bit
Data
Pull-up control register
Tr10
Direction register Data Port latch Port
conversion circuit
Multiplexer
Port (7477/7478 group)
Data Port
conversion circuit
Multiplexer
Port
Data Port
INT0, INT1 CNTR0, CNTR
Control units 4-bit (Control units 2-bit
7470/7477 group
Port
Data Pull-up control register
Tr11 (7470/7471 group) Tr10 (7477/7478 group)
Port
Direction register Data Port latch
Tr10 Tr11 pull-up transistors
Fig. 1.10.8 Block diagram Ports
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1.10 pins
Port (7471/7478 group)
Pull-up control register
Tr12 (7471 group) Tr11 (7478 group Data Port
Data
Tr13 (7471 group) Tr12 (7478 group) Data Port
Tr14 (7471 group) Tr13 (7478 group)
Data Port
XCIN
Tr15 Tr14
(7471 group) (7478 group)
Data Port
Tr11-Tr15 pull-up transistors
Fig. 1.10.9 Block diagram Port
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1.10 pins
1.10.3 Notes When using ports, note following. Modify content port latch When content port latch port modified with managing instruction*, value unspecified changed. Reason managing instruction read-modify-write instruction reading writing data byte unit. Accordingly, when this instruction executed port latch port, following executed bits port latch. which input port: state read CPU, written this after managing. which output port: value read CPU, written this after managing. Make sure following: Even when port which output port changed input port, port latch holds output data. Even when port latch which input port specified with managing instruction, value changed case where content differs from content port latch. managing instructions: instruction Pull-up control pull-up ports software, note following. When used serial mode, pull-up settings corresponding invalidated (pull-up impossible). Refer port block diagram details. When port output mode, pull-up setting corresponding port invalidated (pull-up impossible). Ports other than cannot controlled one-bit units. example, when pulled (pull-up control units bits), also pulled
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1.10 pins
port input level stand-by state input levels input port getting effect low-power dissipation stand-by state especially ports N-channel open-drain. Pull-up (connect port pull-down (connect port these ports through resistor. When determining resistance value, make sure following: External circuit Variation output levels during ordinary operation "Stand-by state": stop mode execution instruction wait mode execution instruction: Reason Even when setting output port with direction register, following state: N-channel when content port latch transistor becomes state, which causes ports high-impedance state. Make sure that level becomes "undefined" depending external circuits. Accordingly, potential which input input buffer microcomputer unstable state that input levels input port "undefined." This cause power source current.
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1.10 pins
Termination unused pins Table 1.10.2 shows termination unused pins. Table 1.10.2 Termination unused pins Terminations Pull-up (connect VCC) Pull down (connect Connect Connect ports through resistor ports through resistor (Note (Note (Note (Note (Note (Note (Note
Port (7470/7471 group)
Open
(Note (Note (Note
(Note (7477/7478 group) (Note (Note (Note (Note (Note (Note (Note (Note AVSS Notes that opened unused time circuit that does allow current flow into itself unless read signal internally input even medium-level input applied open state. programmable ports, connect more ports together through resistor Note following when setting them output mode making pins open. ports function input ports period from reset release till switching ports output mode software. Accordingly, power source current increased depending input levels pins. Port direction register been changed into input mode runaway noise, re-set Port direction register output mode periodically software. pull pin, Port direction register Port latch that this into input mode output state. pull down pin, Port direction register, Port pull-up control register Port latch that this pull-up transistor state input mode output state. These pins connect without resistor when wiring shortest. However, they connect through resistor. addition, built-in programmable version used common with pin, insert resistor about series connect shortest wiring. When using neither (used common with COUT pin), mode register (P50 functions). pull down pin, port pull-up control register that pull-up transistor will provided this pin.
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1.11 Interrupts
1.11 Interrupts
Interrupts used following cases. When requested execute higher-priority processing than processing routine being executed. When necessary observe timing processing. 7470/7471 group generate interrupts from sources 7477/7478 group generate interrupts from sources. 1.11.1 Description interrupt source Priority interrupt interrupts vector interrupts with fixed priority sequence. When more interrupt requests occur same sampling time, they accepted starting with highest-priority interrupt. This priority determined hardware. However, variety priority processing executed software when interrupt control flags (interrupt enable interrupt disable flag) used. Acceptance interrupt corresponding interrupt request upon occurrence interrupt. When following conditions satisfied this state, this interrupt accepted. details, refer "1.11.3 Interrupt control." When interrupt disable flag cleared (interrupt enable state) When interrupt enable (interrupt enable state) Table 1.11.1 shows interrupt priority, interrupt sources vector addresses. Table 1.11.1 Interrupt sources priority Interrupt source Vector Priority 7470/7471 group 7477/7478 group High Reset (Note) FFFF INT0 interrupt FFFD INT1 interrupt key-on wake interrupt FFFB CNTR0 interrupt CNTR1 interrupt FFF916 Timer interrupt FFF716 Timer interrupt FFF516 Timer interrupt FFF316 Timer interrupt FFF116 Serial interrupt Serial receive interrupt FFEF conversion completion interrupt Serial transmit interrupt FFED conversion instruction interrupt FFEB completion interrupt instruction interrupt FFE9 Note: reset operation performed same
address Lower FFFE16 FFFC FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE FFEC FFEA
Remark Non-maskable Polarity programmable INT1: polarity programmable Polarity programmable
FFE816 interrupt, described table.
instruction interrupt nonmaskable software interrupt
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1.11 Interrupts
interrupt When detecting rising edge falling edge each (INT microcomputer generates interrupt request.These polarity selected edge polarity selection register (EG: Address 00D4 pins INT0 pins used common with pins always detect levels stop mode/wait mode When Edge polarity selection register "0," restoration attained interrupt from stop mode/wait mode state provided STP/WIT instruction. details, refer "1.17 Low-power dissipation function." After reset reset release, Edge polarity selection register cleared "0016," interrupts generate interrupt request detecting falling edge. reset release, however, Interrupt control register into interrupt disable state, interrupt accepted. Note: INT1 pins used common with input port however, there register switching between pins ports, active edges always detected. When these pins used ports, corresponding interrupt into disable state. interrupt enable state, interrupt generated level change, thereby causing program away. Key-on wake interrupt When Edge polarity selection register "1," key-on wake interrupt request generated applying level being input port stop mode/wait mode provided STP/WIT instruction, that recovery attained from stop mode/wait mode. After reset reset release, Edge polarity selection register cleared that key-on wake interrupt request does occur stop mode/wait mode. Notes modes other than stop mode/wait mode, key-on wake interrupt disabled. select stop mode/wait mode STP/WIT instruction when interrupt disable flag cleared Edge polarity selection register "1," every input "H."
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1.11 Interrupts
Figure 1.11.1 shows block diagram interrupt input key-on wake circuit.
P33/CNTR1 Port data read circuit P32/CNTR0 Port data read circuit XCIN P30/INT0 Port data read circuit P31/INT1 Port data read circuit
Noise elimination circuit Noise elimination circuit
CNTR interrupt request signal
INT0 interrupt request signal
INT1 interrupt request signal
stop state signal Pull-up control register
Direction register
Pull-up control register Direction register
Port data read circuit
Pull-up control register Direction register
Note: 7470/7477 group provided with XCIN pin.
Fig. 1.11.1 Block diagram interrupt input key-on wake circuit
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1.11 Interrupts
CNTR interrupt When detecting rising edge falling edge each CNTR (CNTR0 CNTR1), microcomputer generates CNTR interrupt. selecting active edge interrupt CNTR0/CNTR pin, Edge polarity selection register (EG) used. After reset reset release, Edge polarity selection register cleared "0016 CNTR0 interrupts generate interrupt request detecting falling edge. reset release, however, Interrupt control register into interrupt disable state, interrupt accepted. Note: CNTR CNTR1 pins used common with input port P33, however there register switching between CNTR pins ports, active edges always detected. When these pins used ports, corresponding CNTR interrupt into disable state. CNTR interrupt enable state, CNTR interrupt generated level change, thereby causing program away. Timer interrupt microcomputer generates interrupt request rise next count source after respective timer overflows. details timer interrupt, refer "1.12 Timers." Serial interrupt There difference serial interrupt between 7470/7471 group 7477/7478 group. Serial interrupt 7470/7471 group interrupt request generated upon termination serial transmit/receive. Serial interrupt 7477/7478 group serial transmit interrupt serial receive interrupt available. Serial transmit interrupt Serial transmit interrupt, interrupt request generation timing selected Serial control register (SIOCON: Address 00E2 shown below. data written Transmit buffer transferred Transmit shift register, when Transmit buffer becomes empty, interrupt request generated. interrupt request generated when shift operation Transmit shift register terminates. Note: When transmit enable enable state, Transmit buffer becomes empty transmit shift terminates. Accordingly, interrupt request generated selecting these sources. transmit interrupt, transmit enable "1," clear transmit interrupt request "0," then transmit interrupt enable enable state. Serial receive interrupt When data been Receive shift register contents shift register have been transferred Receive buffer, interrupt request generated. details serial interrupt, refer "1.13 Serial I/O." conversion completion interrupt soon conversion terminates, interrupt request generated. details conversion completion interrupt, refer "1.14 Converter." instruction interrupt This lowest-priority software interrupt without corresponding interrupt enable flag, affected interrupt disable flag. (Non maskable) details, refer "SERIES SOFTWARE USER'S MANUAL."
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1.11 Interrupts
1.11.2 Operation description Interrupt operation After interrupt accepted, contents register shown below automatically pushed stack area sequence order Program counter high-order Program counter low-order Processor status register (PS) After above register pushed, branch made vector address accepted interrupt. When instruction executed interrupt processing routine, contents above register which were pushed onto stack area popped respective registers sequence order processing precedent acceptance interrupt restarted. Figure 1.11.2 shows interrupt operation.
Executing routine Interrupt occurs (Accepting interrupt request)
Suspended Contents Program counter (high-order) pushed onto stack operation
Contents Program counter (low-order) pushed onto stack
Resume processing
Contents Processor status register pushed onto stack
Interrupt processing routine instruction
Contents Processor status register popped from stack Contents Program counter (low-order) popped from stack Contents Program counter (high-order) popped from stack
Operation commanded software Internal operation performed automatically
Fig. 1.11.2 Interrupt operation
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1.11 Interrupts
Processing upon acceptance interrupt When interrupt accepted, following operations automatically performed. processing being executed interrupted. contents Program counter Processor status register pushed stack area. Figure 1.11.3 shows change contents Program counter Stack pointer upon acceptance interrupt. vector address (start address interrupt processing routine) stored vector area corresponding generated interrupt concurrently with pushing Program counter interrupt processing routine executed. After interrupt processing routine started, corresponding interrupt request automatically cleared "0." interrupt disable flag "1," thereby disabling multi-interrupt. execute interrupt processing routine, necessary vector address vector area corresponding each interrupt beforehand.
Program counter
Program counter (low-order)
Stack area
Program counter (high-order) Interrupt disable flag
Stack pointer
Interrupt request accepted
Program counter
Vector address (from Interrupt vector area) Interrupt disable flag
Stack area
Processor status register Program counter (low-order)
Stack pointer
Program counter (high-order)
Fig. 1.11.3 Changes contents Program counter Stack pointer upon acceptance interrupt
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1.11 Interrupts
Timing after acceptance interrupt interrupt processing routine starts with machine cycle after termination instruction being executed. Figure 1.11.4 shows processing time execution interrupt processing routine Figure 1.11.5 shows timing after acceptance interrupt.
Interrupt request occurs
Interrupt operation starts
Main routine
Waiting time pipeline postprocessing
Push onto stack Vector fetch
Interrupt processing routine
cycles
cycles
cycles
cycles internal system clock 1.75 5.75
instruction executed.
Fig. 1.11.4 Processing time execution interrupt processing routine
Waiting time pipeline postprocessing
Push onto stack Vector fetch
Interrupt operation starts
SYNC Address Data
S-1, S-2,
used
SYNC operation code fetch cycle (This internal signal which cannot observed from external unit.) Vector address each interrupt Jump destination address each interrupt "0016" "0116" (when stack page "0," 0016," when "1," "0116")
Fig. 1.11.5 Timing after acceptance interrupt
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1.11.3 Interrupt control Regarding interrupts other than instruction, acceptance them controlled interrupt request bit, interrupt enable interrupt disable flag. This section describes interrupt control other than instruction. Figure 1.11.6 shows interrupt control diagram.
Interrupt request Interrupt enable Interrupt accepted Interrupt disable flag instruction Reset
Fig. 1.11.6 Interrupt control diagram interrupt request bit, interrupt enable interrupt disable flag function independently affect another. interrupt accepted when following conditions satisfied. Interrupt request Interrupt enable Interrupt disable flag priority determined hardware. However, variety priority processing executed software when above flag bits used. Table 1.11.2 shows interrupt control bits individual interrupt sources. Table 1.11.2 Interrupt control bits individual interrupt sources Interrupt request bits Interrupt source Address Bits 00FC Timer 00FC Timer 00FC Timer 00FC Timer 00FC (Note Serial (7470/7471 group) 00FC (Note Serial receive (7477/7478 group) 00FC (Note Serial transmit (7477/7478 group) 00FC conversion 00FD INT0 00FD INT1 00FD CNTR0 /CNTR1 Notes This provided 7477/7478 group. This provided 7470/7471 group.
Interrupt enable bits Bits Address 00FE16 00FE16 00FE16 00FE16 (Note 00FE16 (Note 00FE16 (Note 00FE16 00FE16 00FF16 00FF16 00FF16
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1.11 Interrupts
Interrupt request interrupt request bits assigned each Interrupt request register 1(IR1: Address 00FC Interrupt request register 2(IR2: Address 00FD16 interrupt request occurs, corresponding interrupt request "1." interrupt request held state until interrupt accepted. After accepted, this automatically cleared "0." interrupt request cleared software cannot software. Interrupt enable interrupt enable bits assigned each Interrupt control register (IE1: Address 00FE Interrupt control register (IE2: Address 00FF16 interrupt enable controls acceptance corresponding interrupt. When interrupt enable "0," acceptance corresponding interrupt disabled. interrupt request occurs when this "0," corresponding interrupt request "1," this interrupt accepted. this case, interrupt request cleared software remains state until interrupt enable "1." When interrupt enable "1," corresponding interrupt enabled. interrupt request occurs when this "1," this interrupt accepted. (However, interrupt disable flag that will described later must "0.") interrupt enable cleared software. Interrupt disable flag interrupt disable flag controls acceptance interrupt, assigned Processor status register (PS). When this flag "1," interrupt disable state provided. When this flag "0," acceptance interrupt enable state. This flag instruction cleared instruction. This flag (interrupt disable state) automatically after interrupt processing routine. multi-interrupt, this flag using instruction interrupt processing routine. Interrupt setting interrupt according procedure shown below. 1The interrupt disable flag "1." 2The interrupt enable cleared "0." 3For interrupt CNTR interrupt, active edge Edge polarity selection register. Select above interrupts Edge polarity selection register because CNTR interrupt CNTR interrupt used simultaneously. CNTR CNTR1 4The request interrupt used cleared "0." (Refer "Table 1.11.2.") 5The enable interrupt used "1." (Refer "Table 1.11.2.") 6The interrupt disable flag cleared "0."
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1.11.4 Notes When using input ports, corresponding interrupt CNTR interrupt into disable state. interrupt request interrupt enable preparations interrupt following order. Clear interrupt request "0." interrupt request) interrupt enable "1." (Interrupt enabled) When using interrupt CNTR interrupt, first interrupt detection edge then above items (Refer that will described later.) interrupt request cleared software, still remained value precedent change immediately after execution clear instruction. this reason, when executing instruction after changing interrupt request bit, first execute interrupt request change instruction then execute instruction after instruction more. When detection edge interrupt that CNTR interrupt switched, corresponding interrupt request "1." Accordingly, perform setting referring register setting example shown Figure 1.11.7.
Clear corresponding interrupt enable interrupt active edge Clear corresponding interrupt request Execute more instructions (NOP instruction, corresponding interrupt enable
Fig. 1.11.7 Example register setting Whether interrupt caused instruction judged contents break flag Processor status register pushed stack area. Break flag interrupt been caused instruction Break flag case other interrupts Note: Make this judgment interrupt processing routine. When interrupt request generated executing STP/WIT instruction following states, stop mode/wait mode released. When active edge interrupt rising edge input level When active edge interrupt falling edge input level Accordingly, when executing STP/WIT instruction, necessary consider input level polarity edge. Examples countermeasures shown below. example countermeasure case where stop mode/wait mode released rising edge input level Point: release stop mode/wait mode normally, perform mode release processing interrupt processing routine only when STP/WIT instruction executed input level.
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1.11 Interrupts
Main routine main routine, edge polarity according input level just precedent execution STP/WIT instruction. interrupt disable Select falling edge when input level "H." Select rising edge when input level "L." Clear interrupt request enable interrupt after instruction more. Clear interrupt disable flag "0." Execute STP/WIT instruction interrupt processing routine interrupt processing routine, change active edge interrupt without performing release processing proceed stop mode/wait mode case where stop mode/wait mode released detecting falling edge. When input level (when rising edge detected) Processing releasing stop mode/wait mode When input level (when falling edge detected) Select rising edge Clear interrupt request from stack Perform processing main routine. example countermeasure case where stop mode/wait mode released rising edge input level falling edge input level after same signal input pin. Point: Select interrupt, main routine, that becomes source release stop mode/wait mode according input level just precedent execution STP/WIT instruction. Main routine interrupt disable Select rising edge active edge interrupt. Select falling edge active edge interrupt. When input level Clear INT1 interrupt request enable INT1 interrupt after instruction more. When input level Clear INT0 interrupt request enable INT0 interrupt after instruction more. Clear interrupt disable flag "0." Execute STP/WIT instruction. ordinary operation, pulse width input signal internal clocks f(XIN)/2 more built-in noise elimination circuit, accepted interrupt input. Input input signal with pulse width more stop mode wait mode. Reference: hardware-level means prevent incorrect interrupt processing noise, noise elimination circuit incorporated pins that interrupt generated pulse (when rising edge selected) pulse (when falling edge selected) machine cycle less modes other than stop mode wait mode. software-level means, levels pins judged beginning interrupt processing routine.
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1.11 Interrupts
1.11.5 Related registers Edge polarity selection register (EG: Address 00D4 Edge polarity selection register selects active edge each interrupt each CNTR interrupt selects source interrupt. Figure 1.11.8 shows structure Edge polarity selection register.
Edge polarity selection register
Edge polarity selection register (EG) [Address 00D416] Name INT0 edge selection INT1 edge selection CNTR edge selection CNTR edge selection CNTR 0/CNTR1 interrupt selection Function Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge CNTR CNTR
reset
source selection 1/INT1 level input instruction execution) (for key-on wake-up) Nothing allocated these bits. These write disabled bits undefined reading.
Fig. 1.11.8 Structure Edge polarity selection register
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1.11 Interrupts
Interrupt request register (IR1: Address 00FC16 Interrupt request register (IR2: Address 00FD16 Interrupt request register Interrupt request register consist bits that indicate whether interrupt request exists not. Figure 1.11.9 shows structure Interrupt request register Figure 1.11.10 shows structure Interrupt request register
Interrupt request register
Interrupt request register (IR1) [Address 00FC16] Name Function
reset
interrupt request Timer interrupt Interrupt requested request Timer interrupt interrupt request request Interrupt requested interrupt request Timer interrupt Interrupt requested request Timer interrupt interrupt request request Interrupt requested Nothing allocated this bit. This write disabled undefined reading. Serial receive interrupt request (7477/7478 group)(Note) Serial interrupt request (7470/7471group) Serial transmit interrupt request (7477/7478 group) conversion completion interrupt request interrupt request Interrupt requested interrupt request Interrupt requested
interrupt request Interrupt requested
Note: 7470/7471group, nothing allocated This write disabled undefined reading. software, "1."
Fig. 1.11.9 Structure Interrupt request register
Interrupt request register
Interrupt request register (IR2) [Address 00FD Name Function
reset
INT0 interrupt request interrupt request Interrupt requested INT1 interrupt request interrupt request Interrupt requested interrupt request CNTR CNTR interrupt request Interrupt requested Nothing allocated these bits. There write disabled bits undefined reading. software, "1."
Fig. 1.11.10 Structure Interrupt request register
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1.11 Interrupts
Interrupt control register (IE1: Address 00FE16 Interrupt control register (IE2: Address 00FF16 Interrupt control register Interrupt control register control acceptance interrupt source. Figure 1.11.11 shows structure Interrupt control register Figure 1.11.12 shows structure Interrupt control register
Interrupt control register
Interrupt control register (IE1) [Address 00FE Name Function
reset
Interrupt disabled Timer interrupt Interrupt enabled enable Interrupt disabled Timer interrupt Interrupt enabled enable Interrupt disabled Timer interrupt Interrupt enabled enable Timer interrupt Interrupt disabled enable Interrupt enabled Nothing allocated this bit. This write disabled undefined reading. Serial receive interrupt enable (7477/7478 group) (Note) Serial interrupt enable (7470/7471 group) Serial transmit interrupt enable (7477/7478 group) conversion completion interrupt enable Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled
Interrupt disabled Interrupt enabled
Note: 7470/7471 group, Nothing allocated This write disabled undefined reading.
Fig. 1.11.11 Structure Interrupt control register
Interrupt control register
Interrupt control register (IE2) [Address 00FF Name Function
reset
Interrupt disabled INT0 interrupt enable Interrupt enabled INT1 interrupt enable Interrupt disabled Interrupt enabled Interrupt disabled CNTR CNTR interrupt enable Interrupt enabled Nothing allocated these bits. There write disabled bits undefined reading.
Fig. 1.11.12 Structure Interrupt control register
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1.12 Timers
1.12 Timers
7470/7471/7477/7478 group four 8-bit timers (Timer Timer Timer Timer with 8bit timer latch. division ratio timer 1/(n+1) when contents timer latch (n:0 255). timer, following modes selected software setting. Timer mode Event counter mode Pulse output mode External pulse width measurement mode mode
Table 1.12.1 shows modes each timer Figure 1.12.1 shows timer block diagram.
Table 1.12.1 Modes each timer Mode Timer Timer Timer Timer Timer Timer mode Event counter mode Pulse output mode External pulse width measurement mode
mode
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1.12 Timers
XCIN T12M2 T12M Port latch P12/T0 T12M1 TM20 T12M3
Data
Timer latch Timer
P32/CNTR0
Timer interrupt request
Timer latch
T12M6, T12M T12M5 1/16 T34M T34M T34M P33/CNTR TM26 T12M
Timer
Timer interrupt request
Timer latch Timer
Timer interrupt request
T34M T34M
Timer latch Timer
Timer interrupt request
Port latch P13/T1 P33/CNTR
T34M6 T34M3
T34M7
TM21
P32/CNTR P31/INT1 P30/INT0
Notes 7470/7477 group provided with XCIN pin. number (ex. described right side register represents number register.
Fig. 1.12.1 Timer block diagram
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1.12 Timers
1.12.1 Operation description write operation, timer latch specified same time when timer specified. timer n16, timer latch also 16). After timer starts count, timer value counted down (n-1)16 (n-2)16 each rise count source. next rise count source after 16," (n-1)16 resulting from decrementing from timer latch value (reloaded) timer then timer continues count. When overflow occurs, interrupt request "1." Note: When interrupt accepted, interrupt request changes from "0." clearned cannot software. Figure 1.12.2 shows timer count timing.
Count operation stop Count stop
Count start
Writing timer Timer count source
Reload
Value timer
!!16
(n-1)16 (n-2)16 (n-3)16
FF16 (n-1)16
Read value timer
(!!+1)16
(n-1)16 (n-2)16 (n-3)16
FF16 (n-1)16
Timer interrupt request
Fig. 1.12.2 Timer count timing
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1.12.2 Description modes Timer mode operations timer modes explained below. Start count operation When count stop cleared "0," count operation starts. When there count source input, contents timer decremented Note: Because count stop immediately after reset release, count operation automatically started after reset release. Reload operation When timer overflows, value resulting from decrementing from contents timer latch transferred (reloaded) timer. Interrupt operation Timer interrupt When timer overflows, interrupt request occurs, that interrupt request "1." acceptance interrupt controlled interrupt enable each timer. Stop count operation When counter stop software, count operation stops. (The count operation continues until count stop "1.") Figure 1.12.3 shows example timer mode operation.
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1.12 Timers
Count period Count period T(s) count source frequency (the timer initial value
Timer mode operation example
Overflow Reload Timer initial value
Timer count stop Timer count source written written
Count stop Count restart
Value timer
(n-1)16
Down count
FF16
Timer interrupt request Timer interrupt enable
Time
Clearing writing timer interrupt request bit.
Clearing accepting timer interrupt request when timer interrupt enable "1."
Fig. 1.12.3 Example timer mode operation
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1.12 Timers
[Setting method] value used according count source setting timers. count operation timer stopped. Refer "Table 1.12.2 Setting count stop." Table 1.12.2 Setting count stop Setting item Timer mode register (T12M: Address 00F816 Timer Timer Timer Timer Timer
Timer mode register (T34M: Address 00F9
Count source selecting Select count source according count source setting timers shown Table 1.12.3 Table 1.12.6. Note that selectable count sources different among timers. Because 7470/7477 group provided with XCIN pin, select f(XCIN count source.
Table 1.12.3 Setting timer count source Setting item mode register Timer mode register Count source (CM: Address 00FB16) (T12M: Address 00F8 selected f(XIN)/16 f(XCIN) (Note) f(XCIN)/16 External clock input from CNTR0 pin. Note: When f(XCIN selected timer count source, f(XIN f(XCIN) selected system clock.
Table 1.12.4 Setting timer count source Setting item mode register Count source (CM: Address 00FB selected f(XIN)/16 f(XIN)/64 f(XIN)/128 f(XIN)/256 f(XCIN)/16 f(XCIN)/64 f(XCIN)/128 f(XCIN)/256 Timer overflow signal
Timer mode register (T12M: Address 00F816
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1.12 Timers
Table 1.12.5 Setting Timer count source Setting item mode register Timer mode register Timer mode register Count source (CM: Address 00FB16) (TM2: Address 00FA (T34M: Address 00F9 selected f(XIN )/16 CIN) (Note) f(XCIN )/16 Timer overflow signal Timer overflow signal External clock input from CNTR1 Note: When f(XCIN selected timer count source, f(XIN f(XCIN selected system clock.
Table 1.12.6 Setting Timer count source Setting item mode register Timer mode register Timer mode register Count source (CM: Address 00FB16) (TM2: Address 00FA (T34M: Address 00F9 selected f(XIN)/16 f(XCIN )/16 Timer overflow signal Timer overflow signal (Note) (Note) Timer overflow signal External clock input from CNTR1 Note: Timer overflow signal selected Timer count source [b5,b4] [1,0], Timer count source becomes Timer overflow signal regardless Timer mode register
count value timer. Refer "Table 1.12.7 Address allocation timer."
Table 1.12.7 Address allocation timer Timer Address Timer 1(T1) 00F016 Timer 2(T2) 00F116 Timer 3(T3) 00F216 Timer 4(T4) 00F316
When value according count start setting shown Table 1.12.8, timer starts count. Table 1.12.8 Count start setting Setting item Timer mode register (T12M: Address 00F8 Timer Timer Timer Timer Timer
Timer mode register (T34M: Address 00F916)
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1.12 Timers
Event counter mode event counter mode, same operations those timer mode performed, with exception that signal input from CNTR0 becomes count source Timer signal input from CNTR becomes count source Timer Timer operation event counter mode described below. Start count operation After count stop cleared "0," count operation starts. Each time count source input, contents timer decremented active edge count source, rise fall selected edge polarity selection register (address 00D4 Note: Because count stop immediately after reset release, count operation automatically started after reset release count source CNTR input (operates timer mode). Reload operation When timer overflows, value resulting from decrementing from contents timer latch transferred (reloaded) timer. Interrupt operation Timer interrupt When timer overflows, interrupt request occurs, that interrupt request "1." acceptance interrupt controlled interrupt enable each timer. CNTR interrupt interrupt request generated from edge count source input from CNTR CNTR pin, that interrupt request "1." acceptance interrupt controlled interrupt enable each timer. edge polarity selection register selects active edge count source CNTR0 CNTR interrupt. Stop count operation When counter stop software, count operation stops. (The count operation continues until count stop bit.) Figure 1.12.4 shows example event counter mode operation.
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1.12 Timers
Count period Count period T(s) count source frequency (the timer initial value
Event counter mode operation example
Overflow Reload Timer initial value
Timer count stop written written
Count source (CNTR0 pin) Count stop
Down count Value timer
Count restart
(n-1)16
FF16
Time
CNTR edge selection
this example, CNTR interrupt request occurs rising edge count source. this example, each CNTR interrupt request does occur during executing CNTR interrupt processing routine.
CNTR interrupt request CNTR interrupt enable Timer interrupt request Timer interrupt enable Clearing writing Timer CNTR interrupt request bits. Clearing accepting Timer CNTR interrupt requests when timer CNTR interrupt enable bits "1."
Fig. 1.12.4 Example event counter mode operation
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1.12 Timers
[Setting method] count operation timer used stopped. Refer "Table 1.12.2 Setting count stop." Select count source according event counter mode setting shown Table1.12.9. count value timer. Refer "Table 1.12.7 Address allocation timer." Start count operation timer used. Refer "Table 1.12.8 Count start setting." Table. 1.12.9 Event counter mode setting Timer Edge polarity selection register Timer mode register Timer mode register Count (EG: Address 00D4 (T12M: Address 00F816) (T34M: Address 00F916 source used Timer CNTR Select (Note) Timer Select CNTR1 Timer (Note) Note: falling edge input, when inverted, becomes count source). rising edge input itself becomes count source). Pulse output mode pulse output mode mode resulting from adding pulse output operation timer mode operation. this mode, pulse whose polarity inverted each overflow output from (Timer overflow signal/2) (Timer overflow signal/2) pin. operations pulse output mode described below. Start count operation After count stop "0," count operation starts. Each time count source input, contents timer decremented Note: Because count stop immediately after reset release, count operation automatically started immediately after reset release pulse output. Reload operation When timer overflows, value resulting from decrementing from contents timer latch transferred (reloaded) timer. Pulse output pulse whose polarity inverted each overflow output from pin. selected level start pulse output each division flip-flop. pulse output started from moment when output selected Timer mode register Timer mode register. Interrupt operation Timer interrupt When timer overflows, interrupt request occurs, that interrupt request set. acceptance interrupt controlled interrupt enable each timer. Stop count operation When counter stop software, count operation stops. (The count operation continues until count stop bit.) Figure 1.12.5 shows example pulse output mode operation.
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1.12 Timers
Count period Count period T(s) count source frequency (the timer initial value
Pulse output mode operation example
Overflow Reload Timer initial value
Timer count stop Timer count source Writing Writing
Count stop Count restart
(n-1)16
Value timer
Down count
FF16
output selected
Time
Setting output port
Initial value
Timer register
Timer interrupt request Timer interrupt enable
Clearing writing Timer interrupt request bit. Clearing accepting Timer interrupt request when Timer interrupt enable "1."
Fig. 1.12.5 Example pulse output mode operation
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[Setting method] count operation timer used stopped. Refer "Table 1.12.2 Setting count stop." pulse output mode according pulse output mode initial value setting shown Table 1.12.10. However, timer register after setting timer mode register
Table 1.12.10 Pulse output mode initial value setting Setting item Timer mode register (TM2: Address 00FA Timer used Timer Timer Note: initial value becomes "0." initial value becomes "1."
Timer mode register (TF: Address 00F7 Select (Note) Select (Note)
pulse output mode according pulse output mode setting shown Table 1.12.11. output port output port used common with respectively. Accordingly, port direction register output mode. Table 1.12.11 Pulse output mode setting Timer mode register Timer Output (T12M: Address 00F816 Timer Timer overflow signal Timer Timer overflow signal count value Timer output) Timer output). When value according count start setting shown Table 1.12.8, timer starts count. Note: When resetting value Timer register, sure observe setting methods above items
Timer mode register (T34M: Address 00F916
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External pulse width measurement mode external pulse width measurement mode used measure pulse width ("H" "L") input from CNTR0 CNTR pin. operations external pulse width measuring mod

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