Lattice Semiconductor, through advanced processing design techniques,

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Lattice Semiconductor, through advanced processing design techniques,

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E2CMOS Technology
Lattice Semiconductor, through advanced processing design techniques, able offer highest performance PLDs (Programmable Logic Devices) industry. addition, Lattice devices in-system programmable, allowing customers utilize latest device packages overall design flexibility. Lattice, first E2CMOS® company, continued successfully produce devices based E2CMOS technology. basic operation this technology described below. tions process technology. incorporating both grounded pumped substrate techniques from NMOS technology with power CMOS devices, Lattice's E2CMOS technology maintains high performance while meeting high voltage requirements programming. addition combining techniques both NMOS CMOS, Lattice's E2CMOS technology incorporates ultra-clean, ultra-thin tunneling oxide. requirements placed these oxides will much more apparent after programming characteristics cell examined.
Single Cell Programming
E2CMOS cell programmed placing high voltage across thin tunnel dielectric. resulting tunneling current will tunnel electrons onto floating gate turning sense transistor with different applied potential, tunnel electrons floating gate, turning sense transistor. Once charge been placed floating gate, actual floating gate potential modulated voltage control gate through capacitive coupling. this capacitive coupling that used generate high voltage across tunnel dielectric beginning programming pulse. During programming cycle, cell first erased into `1', non-conducting state then selectively written `0', conducting state write cycle. This prevents sense device from conducting current during write operation when voltage applied drain device. Therefore, programming characteristics will explored first examining cell during erase.
Basic Theory Operation
E2CMOS cell built around transistor with floating gate which externally charged discharged small programming current. floating gate charged positive potential removing electrons from floating gate, cell transistor turned storing binary cell. floating gate charged negative potential placing electrons floating gate, transistor kept non-conducting state, which writes binary into cell. addition floating gate sense device, additional select transistor, pass gate, added series with cell isolate from array during read write operations. addition conventional line word line, E2CMOS cell also additional line matrix control gate (MCG) which controls potential floating gate. cell programmed applying programming pulse either matrix control gate line cell which been selected applied high voltage word line. Programming takes place when electrons tunnel through thin tunneling dielectric shown schematic small notch floating gate over drain sense device. Before describing detailed operation E2CMOS cell, requirements trade-offs process technology will reviewed.
Erase Cycle Programming
During erase cycle, high voltage applied control gate cell programmed, shown Figure current through tunnel oxide neglected, floating gate will simply track applied voltage following relationship capacitive divider, where coupling ratio cell, typically between 0.8. erase pulse, floating gate again couples negatively same amount, back initial floating gate voltage Vfg(0).
E2CMOS Process Technology
Lattice's E2CMOS technology based upon highly successful combination CMOS some devices NMOS technologies. requirements both on-chip high voltage high speed devices severe restric-
techrel_04
November 1999
E2CMOS Technology
Figure Erase Cycle Schematic However, instead current flowing through tunnel oxide, coupling ratio keeps floating gate potential, which forces high negative voltage appear across tunnel oxide. This high voltage causes tunneling current flow which will charge floating gate during write pulse write pulse, floating gate will potential that higher than initial floating gate voltage amount that floating gate charged during pulse. This positive voltage sufficient turn sense transistor during read operation. magnitude control gate voltage which required couple this positive floating gate voltage down threshold sense device actually turn defined programmed threshold VtLow.
Line Pass Transistor Word Line Substrate
Control Gate Sense Transistor Cell Ground
1Floating
Reading Cell
After erase cycle, charge floating gate left sense transistor off, non-conducting state. erase cycle followed write cycle, then floating gate charge leaves sense device conducting state. Therefore, data cell read simply sensing cell current when biased with control gate centered between states. This shown schematically Figure line control gate voltages selected minimize potential across tunnel dielectric during read order maximize retention floating gate charge. actual magnitude programmed thresholds, thus margins cell, controlled programming voltage, physical cell layout, tunnel oxide electrical characteristics. electrical properties tunnel oxide will examined since they critical determining both programming properties reliability E2CMOS cell. Figure Cell Read Cycle Schematic
Icell Line Pass Transistor Word Line +5.0 selected) Vbit Volt
gate voltage; 2Control gate voltage; 3Initial floating gate
voltage
However, high voltage applied across tunnel dielectric causes tunneling current flow, which will discharge floating gate during erase pulse. erase pulse, floating gate will potential that lower than initial floating gate voltage amount that floating gate decayed during pulse. This negative voltage sufficient turn sense transistor during read operation. magnitude control gate voltage which required couple this negative floating gate voltage threshold sense device actually turn after erase pulse defined programmed high threshold VtHigh.
Write Cycle Programming
During write cycle, high voltage applied line cell programmed. current through tunnel oxide again neglected, floating gate will track applied drain voltage following relationship capacitive divider: drain
1Drain
voltage applied during write
drain coupling ratio cell typically much lower than coupling ratio control gate, ranging between 0.2. erase case, floating gate would again couple negatively this same amount, back initial floating gate voltage Vfg(0) write pulse. Also note that pass transistor have voltage drop across lowering voltage drain below applied programming voltage Vpp.
Control Gate Volts Sense Transistor
Cell Ground
E2CMOS Technology
Tunnel Oxide Electrical Characteristics
E2CMOS cell programmed placing high voltage across thin tunnel dielectric. tunnel oxide sufficiently thin, typically with thickness between Angstroms, allowing electrons tunnel through dielectric program cell. exact nature tunneling mechanism important because addition determining amount voltage required sufficient current through oxide program cell. tunnel characteristic also must very strong function voltage prevent charge from leaking floating gate during voltage, normal read operation. addition electrical current voltage characteristics, thin tunneling dielectrics must also characterized amount charge that pass through oxide without altering electrical properties. Electron traps located oxide will capture some electrons passing through dielectric. this trapped charge builds oxide, electrical properties change, eventually oxide wears ruptures. Thus, addition controlling erase write characteristics E2CMOS cell, tunnel oxide, oxide quality, play major role reliability technology. higher negative voltage required same current positive voltage case because additional voltage drop that occurs across depletion region formed silicon negative applied voltage. tunnel oxide approximately Angstroms thickness, maximum voltage developed during programming roughly volts, field strength This very high applied field stress, needed tunneling process requires very high quality oxides very clean processing conditions. Optimizing thickness tunneling dielectric trading between programming characteristics oxide reliability requirement E2CMOS technology. characteristic very strong function oxide thickness follows relationship FowlerNordheim tunneling equation, where Fowler-Nordheim coefficients.
Area
This equation rewritten terms field across oxide below, which independent oxide thickness.
Area
Characteristics Thin Tunnel Dielectrics
typical characteristic thin tunnel oxide shown Figure Since current must flow through this oxide both directions, characteristic oxide shown both positive negative polarities. Note that Figure Tunnel Oxide Characteristics
Charge-to-Breakdown Thin Tunnel Oxides
characteristic shown previous section measured sufficiently current densities such that charge trapping occurred during measurements. however, large amount charge passed through oxide, trapped charge oxide will alter electrical characteristic. increase voltage required same tunneling current after large amount charge passes through oxide will reduce amount charge transferred into cell during programming cycle therefore reduce cell programming margins with continued cycling. magnitude charge required shift characteristic depends quality number traps oxide. addition this shift electrical properties tunnel dielectric, defects oxide, whose properties change charge passes through oxide, will actually cause oxide rupture after finite amount charge passed through dielectric. maximum charge that passed through oxide prior oxide breakdown, oxide fluence expressed Coulombs/cm2, determined passing current
Positive
Igate (Amps)
Negative
Vgate (Volts)
E2CMOS Technology
through tunnel dielectric until ruptures. This physical limitation current that passed through tunnel oxide places limit number programming cycles that performed device. This cycling limit, endurance, dependent quality tunnel dielectric it's associated defect density well exact programming stress oxide. Lattice's technology maximizes endurance devices through careful control requirements oxide well optimizing quality dielectric.
Summary
Although exact specifications E2CMOS process easily become quite involved, general functionally described. E2CMOS technology proven provide invaluable flexibility system designers while providing cost effective solution manufacturing companies.

Lattice Semiconductor, through advanced processing design techniques,

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