EXTERNAL LEAD DESIGNS shape leads leaded surface-mount packages,

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Vantis provides programmable logic devices (PLDs) wide range packages. These packages provide benefits such high power dissipation capability, small footprint, high I/O. This section provides details about packages that Vantis supplies.
EXTERNAL LEAD DESIGNS
shape leads leaded surface-mount packages, which includes package, formed either gull-wing J-bend shape. Both lead shapes offer advantage being flexible, which allows them absorb thermal expansion mismatches between package board.
Plastic Package Design Leaded Chip Carrier (PLCC) Quad Flat Pack (PQFP) Thin Quad Flat Pack(TQFP) Ball Grid Array (BGA) Plastic Dual-In-Line (PDIP) Small Outline Plastic (SOIC) Leadcounts 20-84 leads 100-240 leads 44-176 leads 256-352 balls 20-28 leads 20-24 leads Lead Design/Direction J-Bend/4 sides Gull-wing/4 sides Gull-wing/4 sides Solder Balls/Array Through-hole Gull-wings/2 sides
Gull-Wing Lead Design Gull-wing leads similar dual-in-line, through-hole leads except that leads bent tips rest flat board surface. This provides built-in standoff between package board, enabling thorough board cleaning easy-to-inspect solder joints.
J-Bend Lead Design Like gull-wing design, J-bend leaded packages mounted directly board, thus offering built-in standoff advantages inherent this. strong, inspectable bond easily attainable provided solder lands include extensions from under package. J-bend design also allows easy socketing, which facilitates device testing programming.
Publication# 21552 Amendment/0
Rev: Issue Date: November 1998
Package Leads
Solder Fillet
Solder Land Printed Circuit Board
21552B-001
Figure J-Bend Left) Gull-Wing Lead Formations Right) Allow Components Mounted onto Surface Circuit Board
PACKAGE MATERIALS
materials used Vantis' plastic packages flammability data provided this section.
Table Flammability Ratings Package Type Size
Package (PL) (PL) Plastic Leaded Chip Carriers (PL, PLH) (PL) (PL) (PL) (PLH) (PQR) Metric Plastic Quad Flat Pack (PQR) (PQR) (PQR) (PQR) Thermally Enhanced Metric Plastic Quad Flat Pack (heat spreader (PRH), heat sink (PQE)) Thin Plastic Quad Flat Pack (1.0 thick (PQT); thick (PQL) TQFP (PQE) (PRH) (PQE) (PQE) (PQT) (PQL) (PQL) (PQL) (PQL) (BGD) Plastic Ball Grid Array (BGD) Plastic Dual-In-Line (PD3) (Note (PD3) (Note Small Outline Plastic substrate: 94V-O glob top: 94HB Leadcount Rating Oxygen Index1 Resin Weight Unit (grams) <0.1 <0.1 <0.1 <0.1 <0.1 0.07 (Note 0.12 (Note <0.1 <0.1 Compound Weight Unit (grams) 3.97 0.26 (Note 0.45 (Note
Notes: mold compound tested according ASStandard D2863-77,:Standard Method Measuring Oxygen Concentration Support Candlel-Like Combustion Plastics (Oxygen Index)." flammability rating determined Underwriters Laboratories (UL) Standard "Test Flammability Plastic Materials Parts Devices Applications. Refers weight glob-top encapsulation. (300-mil) designates PDIP design which package size what standard that lead count.
Table Package
Package Type Leadcount Package Part
Materials
Material epoxy novolac silica filler chlorine Percentage Composition2 13.0%-30.5% 69.5%-87.0% 7-80 0.0%-0.9% weight 0%-1.8% 5-40 0-10 20%-30% 80%-70% 5-50 5-50 5-20 99.99% 96.2%-99.9% 3.0% 0.005%-2.35% 0.65% 0.15% 0.12% 0.0%-0.15% traces, depending leadframe supplier 85%, +5%, -0%/15%,
Plastic Surface Mount Packages (excluding Ball Grid Array Packages)
Package body
bromine antimony trioxide sodium potassium epoxy silver filler
attach adhesive Package Types Lead Counts
sodium chlorine potassium
Die-to-package interconnections
bond wire
gold copper nickel iron silicon
Leadframe
copper
magnesium zinc zirconium phosphorous, aluminum, manganese
Lead plating Notes: Excluding
tin/lead
Ranges provided some cases, cover differences materials supplier. Contact your local Vantis sales representative more product specific information.
Table Package Materials
Package Type Leadcount Ball Grid Array Packages substrate Package body circuitry solder mask organic resin glass fibers copper (Note resin inorganic fillers additives Plastic Package Versions attach adhesive Die-to-package interconnections Package-to-board outerconnections Glob encapsulation Heat spreader Notes: Excluding Ranges provided some cases cover differences materials supplier. Contact your local Vantis sales representative more product specific information. internal leads electroplated with nickel, copper, gold. These persentages vary depending specific package. Contact your local Vantis sales represenative should need product specific information. bond wire solder balls epoxy silver filler gold tin, lead epoxy resin silica filler copper iron 40%-60% 40%-60% 99%-100% 40%-60% 35%-55% 1%-10% 20%-30% 70%-80% 99.99% 63%, (eutectic) 20%-40% 60%-80% 96%-99% 0%-2.4% Package Part Material Percentage Composition
Table Materials Detectable Vantis' Plastic Components
4-Aminodiphenyl salts Ammonium Salts Arsenic Asbestos Benzene Brominated Diphenyl Oxides Cadmium Cadmium Compounds Decabromodiphenyl Ether 4-Diaminophenyl Methane Epichlorhydrine Ethylene Glycol ethers Fluorine Formaldehyde Halogenated Aliphatic Hydrocarbons Hydrazine 2-Naphthylamine salts Nickel Tetracarbonyl N-Dimethylformamide N-Dimethylacetamide N-Nitrosoamines Mercury Mercury Compounds Ozone Depleting Compounds Octabromodiphenyl Ether Oils Greases Palladium Phthalate Halogenated Aliphatic Hydrocarbons Polyhalogenated Bi/Triphenyl Ethers Polyhalogenated Dibenzofurans/Dioxins Polychlorinated Naphthalenes Polycyclic Compounds Selenium Tetrabromobenzylimidazole Tetrabromobisphenol Tetrabromoethylene Toluene Triethylamine Tris 3-Dibromopropyl) Phosphate Tris (aziridinyl) Phosphin Oxide Vinyl Chloride Monomer Xylene
Thermally Enhanced Plastic Package Designs addition standard package designs, Vantis' PLCC PQFP package families include highperformance variations devices having greater power faster speed. also evaluating high-performance designs TQFP package families. high-performance package designs include variations: which heat spreader embedded package, other entails assembling into package heat sink which visible topside package. Heat Spreader Design This design includes heat sink that attached padless leadframe using B-stage adhesive. heat sink, referred this design heat spreader because serves attach pad, fills narrow between where die-attach would normally leads begin. This provides more efficient means heat transferal since heat from device longer pass over escape leadframe. Also thermally advantageous, thin strip insulating tape B-stage epoxy allows heat sink quite close leadframe without actually touching (since would cause electrical short. heat sink also serves fixed potential plane that voltage level will vary much from voltage back die. Because heat sink underneath die, separated from only epoxy 0.003-inch thick insulating tape, closer input/output, power, ground leads than standard PLCC package which closest ground circuit board, 0.090 inch below leads). This significantly lowers lead inductance which keeps noise level down. Comparative analysis package performance using same device standard versus highperformance PLCC package have shown latter outperform standard package areas lead inductance, thermal impedance (ja), speed, yields.
Standard PLCC Package Design
21552B-003
High Performance PLCC Package Design
21552B-004
Figure High-Performance PLCC Package Includes Heat Spreader Within Package-a Feature Present Standard PLCC Package Design
Exposed Heat Sink Design very high-power devices, necessary that heat sink conduct heat surface package. such devices, much thicker heat sink used span entire encapsulated portion leadframe. This design achieved either cavity-down version (see Figure which heat sink visible package, cavity-up version,
which heat sink exposed package bottom (Figure This style heat sink sometimes referred heat slug, since metal comes contact with chip itself opposed heat sink that attached exterior package body). Thermal Performance Improvement improvement thermal performance for, say, 28-mm body PQFP, approximately percent heat spreader design percent exposed heat sink version. Contact your Vantis sales representative should need additional information about Vantis' highperformance plastic package designs.
Mold Compound Attach Adhesive Gold Wire
Leadframe
Heat Slug
Polymide
Nickel Plated
Black Oxide
21552B-005
Figure Heat Sink Assembled Thermally Enhanced PQFP (Known Package) Visible Bottom Side Package
PLASTIC LEADED CHIP CARRIER (PLCC) PACKAGES
PLCC package design attractive alternative higher leadcount plastic DIPs because accommodate larger sizes offer advantages SMT. Above leads, PLCC configuration lead-pitch impractical given availability lower profile, high leadcount packages, such finer pitch PQFPs. PLCC package construction consists device attached leadframe, circuitry which wire bonded lead fingers. plastic epoxy material injection-molded encapsulate device/leadframe configuration. quad-directional leads trimmed formed J-bend formation. 50-mil lead-pitch PLCC package half conventional lead spacing DIP. This, coupled with PLCC leads being located four sides package, greatly reduce footprint. comparison package dimensions shown Table
Table PLCC (PL) Package Size Overview
Leadcount Package Body Area Inches 0.125 0.205 0.426 0.908 1.33 0.05 Lead Pitch Inches Package Weight (Grams) 0.65 1.07 2.22 4.62 7.45
Note: Vantis' internal abbreviation PLCC package.
21552B-006
Figure Square Packages (PL)
Vantis Package Type Leadcount (JEDEC Drawing Number) (MS-018(A)AA) Dimension Codes 0.165 0.090 0.062 0.385 0.350 0.290 0.009 0.180 0.120 0.083 0.395 0.356 0.330 0.015 0.165 0.090 0.062 0.485 0.450 0.390 0.009 (MS-018(A)AB) 0.180 0.120 0.083 0.495 0.456 0.430 0.015 0.165 0.090 0.062 0.685 0.650 0.590 0.009 (MS-018(A)AC) 0.180 0.120 0.083 0.695 0.656 0.630 0.015 0.165 0.090 0.062 0.985 0.950 0.890 0.007 (MO-047(B)AE) 0.180 0.130 0.083 0.995 0.956 0.930 0.013 084, PLH084 (MO-047(B)AF) 0.165 0.090 0.062 1.185 1.150 1.090 0.007 0.180 0.130 0.083 1.195 1.156 1.130 0.013
0.200
0.300
0.500
0.800
1.000
Notes: dimensions inches. Dimensions measured from outermost point. Dimensions "D1" "E1" include corner mold flash. Allowable corner mold flash 0.010 inch. Dimensions measured from points contact base plane. Lead spacing measured from center-line center-line shall within ±0.005 inch. J-bend lead tips should located inside "pockets." Lead coplanarity shall within 0.004 inch measured from seating plane. Lead tweeze shall within 0.0045 inch each side measured from vertical flat plane. lead pocket rectangular shown) oval. corner lead pockets connected, then 0.005-inch minimum lead spacing required. Vantis' internal abbreviation PLCC. refers that been thermally enhanced with embedded heat spreader.
PLASTIC QUAD FLAT PACK (PQFP) PACKAGES
PQFP packages were developed primarily high-leadcount applications. finer lead-pitch PQFP enables this design accommodate higher leadcount devices than desirable PDIP, PLCC, SOIC packages. benefits PQFP package configuration were realized within industry, design extended lower leadcounts. PQFP package construction consists device attached leadframe, circuitry which wire bonded lead fingers. plastic epoxy material injection-molded encapsulate device/leadframe configuration. quad-directional leads trimmed formed gull-wing formation. Vantis' PQFP package family includes wide range leadcount variations (from 240). Some packages thermally enhanced with either heat spreader, embedded package body; exposed heat sink.
Table PQFP (PQR)1 Package Size Overview
Leadcount (PQR) (PQR) (PQR) (PQE) (PQR, PRH) (PQE) (PQE) Package Body Area Inches SQ.) 0.434 (280.0) 1.215 (784.0) 1.215 (784.0) 1.215 (784.0) 1.215 (784.0) 1.588 (1024.0) 0.50 0.65 Lead Pitch (mm) 0.65 Package Weight (Grams) 1.66 5.21, 5.34 5.30 5.37 9.53, 9.68 10.87 15.07
Note: (cavity Vantis' internal abbreviations metric PQFPs. Thermally ehanced versions denoted (cavity with heat spreaders) (cavity with exposed heat sink).
21552B-007
Figure Rectangular Metric, Cavity-Up Packages (PQR)
Notes: dimensions millimeters, dimensions tolerances conform ANSI Y14.5M-1982. Datum plane located mold parting line coincident with bottom lead where lead exits plastic body. Dimensions include mold protrusion. Allowable mold protrusion 0.25 side. (Also Note Dimension does include dambar protrusion. Dimensions include mold mismatch determined datum plane -A-. Dimensions measured from both innermost outermost points. Deviation from lead-tip true position shall within ±0.076 packages having lead pitch >0.5 within ±0.04 when pitch Lead coplanarity shall within 0.10 devices having lead pitch 0.65-0.80 0.076 when lead pitch 0.50 half span (center package lead tip) shall within ±0.0085. 1.03 Vantis' internal abbreviation metric PQFP.
Vantis Package Type Leadcount (MO-108(B)CC-1) Dimension Codes (Note (Note (Note (Note (Note (Note Lead Lead Lead Lead 0.73 23.00 19.90 18.85 0.13 0.10 0.25 2.70 0.22 0.15 17.00 13.90 12.35 0.65 BASIC 23.40 20.10 3.35 2.90 0.38 0.23 17.40 14.10
Plastic Quad Flat Pack (PQFP)
21552B-008
Figure 160-Lead Square Metric, Cavity-Up Package with Heat Sink (PQE)
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes 0.73 1.60 0.08 0.08 PQE160 (MS-022(A)/DD-2) 0.25 3.25 0.22 0.11 30.80 27.90 25.35 0.65 BASIC 1.03 4.00 0.45 3.45 0.38 0.17 31.60 28.10
Notes: dimensions millimeters, dimensions tolerances conform ANSI Y14.5M-1982. Datum plane located mold parting line coincident with bottom lead where lead exits plastic body. Dimensions include mold protrusion. Allowable mold protrusion 0.25 side. (See also Note Dimension does include dambar protrusion. Dimensions include mold mismatch determined datum plane -A-. Dimensions measured from both outermost points. pin-one inside ejector mark separate. heatsink center line aligned package body's center line tolerance ±0.30 half span (center package lead tip) shall within 15.30 0.165 lead distortion (bent leads, etc.) shall cause deviation from lead's true position greater than ±0.04 maximum dimension. Lead coplanarity with respect seating plan shall exceed 0.10 Vantis' internal abbreviation cavity-up, metric PQFP which been thermally enhanced with exposed heat sink.
Plastic Quad Flat Pack (PQFP)
(see table dimensions)
21552B-007
Figure Plastic Quad Flat Pack (PQFP)
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes (Note (Note (Note (Note Lead Lead Lead Lead 0.73 0.25 3.20 0.22 0.13 31.00 27.90 3.95 3.60 0.38 0.23 31.40 28.10 PQR160 0.25 3.20 0.22 0.13 31.00 27.90 3.95 3.60 0.38 0.23 31.40 28.10 PQR, 0.25 3.20 0.18 0.13 30.40 27.90 3.95 3.60 0.30 0.20 30.80 28.10 (MO-108(B)DC-1) (MO-108(B)DD-1) (MO-143(B)FA-1)
Notes: dimensions millimeters, dimensions tolerances conform ANSI Y14.5M-1982. Datum plane located mold parting line coincident with bottom lead where lead exits plastic body. Dimensions include mold protrusion. Allowable mold protrusion 0.25 side. (Also Note Dimension does include dambar protrusion. Dimensions include mold mismatch determined datum plane -A-. Dimensions measured from both innermost outermost points. Deviation from lead-tip true position shall within ±0.08 packages having lead pitch >0.5 within ±0.04 when pitch Lead coplanarity shall within 0.10 devices having lead pitch 0.65-0.80 0.08 when lead pitch 0.50 half span (center package lead shall within ±0.0085. (cavity Vantis' internal abbreviation metric PQFPs. Thermally-enhanced PQFPs denoted those with heat spreaders embedded them (PRH cavity up).
22.75 0.65 BASIC 0.13 0.10 1.03
25.35 0.65 BASIC 0.13 0.10 0.73 1.03
25.50 0.50 BASIC 0.08 0.08 0.50 0.75
Plastic Quad Flat Pack (PQFP)
21552B-010
Figure 208-Lead Metric Cavity-Up Package with Heat Sink (PQE)
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes 0.50 1.30 0.08 0.08 PQE208 (MO-143(B)FA-1) 0.25 3.29 0.17 0.10 30.40 27.90 25.50 0.50 BASIC 0.75 3.70 0.42 3.45 0.27 0.20 30.80 28.10
Notes: dimensions millimeters, dimensions tolerances conform ANSI Y14.5M-1982. Datum plane located mold parting line coincident with bottom lead where lead exits plastic body. Dimensions include mold protrusion. Allowable mold protrusion 0.25 side. (See also Note Dimension does include dambar protrusion. Dimensions include mold mismatch determined datum plane -A-. Dimensions measured from both outermost points. pin-one inside ejector mark separate. heatsink center line aligned package body's center line tolerance ±0.30 half span (center package lead tip) shall within 15.30 0.165 lead distortion (bent leads, etc.) shall cause deviation from lead's true position greater than ±0.04 maximum dimension. Lead coplanarity with respect seating plan shall exceed 0.08 Vantis' internal abbreviation cavity-up, metric PQFP that been thermally enhanced with exposed heat sink.
Plastic Quad Flat Pack (PQFP)
3.55 4.10
3.30 3.50
21552B-011
Figure 240-Lead Metric Cavity-Up Package with Heat Sink (PQE)
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes 0.45 1.30 0.08 0.08 PQE240 (MO-143(B)/GA) 0.25 0.17 0.10 34.35 31.90 29.50 0.50 BASIC 0.75 0.45 0.27 0.20 34.85 32.10
Notes: dimensions millimeters, dimensions tolerances conform ANSI Y14.5M-1982. Datum plane located mold parting line coincident with bottom lead where lead exits plastic body. Dimensions include mold protrusion. Allowable mold protrusion 0.25 side. (See also Note Dimension does include dambar protrusion. Dimensions include mold mismatch determined datum plane -A-. Dimensions measured from both outermost points. pin-one inside ejector mark separate. heatsink center line aligned package body's center line tolerance ±0.30 half span (center package lead tip) shall within 15.30 0.165 lead distortion (bent leads, etc.) shall cause deviation from lead's true position greater than ±0.04 maximum dimension. Lead coplanarity with respect seating plan shall exceed 0.08mm. Vantis' internal abbreviation cavity-up, metric PQFP that been thermally enhanced with exposed heat sink.
Plastic Quad Flat Pack (PQFP)
THIN QUAD FLAT PACK (TQFP) PACKAGES
TQFP package same basic package design PQFP except package thinner, dimensions governing solder land pattern different. thickness package body versus 3.5-mm thickness standard PQFP. This possible because back ground down 0.34-mm thickness. major applications TQFP packages handheld products, small disk drives, doublesided boards, PCMCIA cards. Vantis' family TQFP packages includes cavity-up versions (denoted internally PQL) from leads.
Table TQFP1 Package Size Overview
Package Body Area Inches sq.) 0.155 (100) 0.076 (49) 0.304 (196) 0.62 (400) 0.893 (576) Lead Pitch Inches (mm) 0.03 (0.80) 0.02 (0.5) 0.02 (0.50) 0.02 (0.50) 0.02 (0.50) Package Body Thickness Inches (mm) 0.04 (1.00) 0.055 (1.4) 0.055 (1.40) 0.055 (1.40) 0.055 (1.40) Package Weight (Grams) 0.232 0.17 0.63 1.32 1.82
Leadcount (PQT) (PQL) (PQL) (PQL) (PQL)
Note: Vantis' internal abbreviation TQFPs having package body thickness denotes TQFPs with package body thickness
21552B-012
Figure Thin Plastic Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes 0.30 0.30 PQT044 (MS-026(A)ACB) 0.05 0.95 11.80 9.80 0.45 0.80 BASIC 0.45 0.40 0.10 0.20 0.20 0.17 0.17 1.20 0.15 1.05 12.20 10.20 0.75 PQL048 (MO-136(B)AE) 0.05 1.35 1.60 0.15 1.45 PQL100 (MS-026(A)BED) 0.05 1.35 15.80 13.80 0.45 0.50 BASIC 0.17 0.16 0.27 0.23 0.08 0.08 0.20 0.27 0.23 0.08 0.08 0.20 0.17 0.17 1.60 0.15 1.45 16.20 14.20 0.75 PQL144 (MS-026(A)BFB) 0.05 1.35 21.80 19.80 0.45 0.50 BASIC 0.27 0.23 0.08 0.08 0.20 0.17 0.17 1.60 0.15 1.45 22.20 20.20 0.75 PQL176 (note (MS-026(A)BGA) 0.05 1.35 25.80 23.80 0.45 0.50 BASIC 0.27 0.23 0.08 0.08 0.20 1.60 0.15 1.45 26.20 24.20 0.75
9.00 BASIC 7.00 BASIC 0.45 0.50 BASIC 0.75
Notes: dimensions millimeters, dimensions tolerances conform ANSI Y14.5M-1982. Datum plane located mold parting line coincident with bottom lead where lead exits plastic body. Dimensions include mold protrusion. Allowable mold protrusion 0.254 side. (See also Note Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08 total excess dimension maximum material condition. dambar cannot located lower radius foot. Dimensions include mold mismatch determined datum plane -H-. Dimensions measured from both innermost outermost points. Deviation from lead-tip true position shall within ±0.076 packages having lead pitch >0.5 within ±0.04 when pitch Lead coplanarity shall within 0.10 devices having lead pitch 0.65-0.80 0.08 when lead pitch 0.50 half span (center package lead tip) shall within ±0.16 total number terminals. package smaller than bottom package 0.15 Vantis' internal abbreviation 1.0-mm thick TQFP. designates 1.4-mm thick TQFP.
Thin Quad Flat Pack (TQFP)
BALL GRID ARRAY (BGA) PACKAGES
package relatively package design which gaining popularity attractive package solution Programmable Logic FPGA devices. offers high-density package with smaller form/fit factor than comparable leadcount quad flat pack package. More importantly, designed with solder balls instead leads, which more durable loosely pitched than fragile package leads comparable surface-mount component. This results higher board yields. Package Design package consists thin Printed Circuit Board (PCB) made epoxy laminate, doublesided, overlaid with copper over which metallized wire bond pads fabricated. wirebond pads extend outward plated through-hole vias located around board's periphery. These vias provide electrical continuity from board other side where copper traces from holes matrix solder bumps. bumps soldered onto land pattern circuit board end-use application. solder mask photo defined backside package contain flow solder during board assembly. attached using standard epoxy attach method. Gold ball bonding used connect pads wire bond pads, encapsulated with epoxy encapsulation material protect
Table Package Size Overview
Ball Count (BGD) (Note (BGD) (Note Package Body Area Inches sq.) 1.13 (729.0) 1.90 (1225.0) Ball Pitch Inches (mm) 0.05 (1.27) Package Weight (Grams) 4.23 6.99
Note: Vantis' internal abbreviation wirebonded, cavity-down, ball grid array, thermally enhanced with heat slug
Attach Adhesive
Copper Heatspreader Copper Ring Substrate
Wires
Encapsulant
Solder Balls
Mounting Surface
Resin (Part Substrate)
Figure Cross-section
21552B-029
Ball Grid Array
21552B-013
Figure 256-Ball Cavity-Down Package (BGD)
Vantis Package Type Leadcount (JEDEC Drawing Number) BGD256 (MO-151(B)/BAL-2)1 Dimension Codes (Note (Note 0.60 14.8 0.635 BASIC 1.10 0.50 0.60 0.15 27.00 BASIC 24.13 BASIC 1.27 BASIC 0.90 15.2 1.65 0.70 0.95 0.45 Note overall thickness ball height body thickness seating plane clearance body size ball footprint ball matrix size total ball count number rows deep ball pitch ball diameter encapsulation area solder ball placement
Note: Vantis' internal abbreviation wirebonded, plastic, cavity-down ball grid array that been thermally enhanced with heat sink.
Ball Grid Array
Geometric Tolerances Notes: dimensions millimeters. Dimensioning tolerancing conform ASME Y14.5M-1994. Dimension measured maximum solder ball diameter plane parallel datum Datum seating plane defined spherical crowns solder balls. corner I.D. marked with ink. Refers number peripheral rows columns. Refers height from encapsulation seating plane. measured with respect datums defines position solder balls nearest package centerlines. When there number solder balls outer 0.000; when there even number solder balls outer value =e/2. 0.15 0.15 coplanarity parallelism
Ball Grid Array
21552B-014
Figure 352-Ball Cavity-Down Package (BGD)
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes (Note (Note 0.60 20.4 0.635 BASIC BGD352 (MO-151(B)/BAR-2) 1.10 0.50 0.60 0.15 35.00 BASIC 31.75 BASIC 1.27 BASIC 0.90 21.2 1.65 0.70 0.95 0.45 Note overall thickness ball height body thickness seating plane clearance body size ball footprint ball matrix size total ball count number rows deep ball pitch ball diameter encapsulation area solder ball placement
Ball Grid Array
Geometric Tolerances Notes: dimensions millimeters. Dimensioning tolerancing conform ASME Y14.5M-1994. Dimension measured maximum solder ball diameter plane parallel datum Datum seating plane defined spherical crowns solder balls. corner I.D. marked ink. Refers number peripheral rows columns. Refers height from encapsulation seating plane. measured with respect datums defines position solder balls nearest package centerlines. When there number solder balls outer 0.000; when there even number solder balls outer value =e/2. Vantis' internal package abbreviation wirebonded, plastic, cavity-up package. 0.15 0.15 coplanarity parallelism
Ball Grid Array
PLASTIC DUAL-IN-LINE PACKAGES (PDIP)
Plastic Dual-In-Line package (PDIP) construction consists device attached leadframe, circuitry which wire bonded lead fingers. plastic epoxy material injection-molded encapsulate device/leadframe configuration. leads trimmed formed through-hole lead design, with lead extensions along long ends rectangular package.
Table PDIP (PD) Package Size Overview
Package Body Area Inches 0.267 0.69 0.32 0.81 0.10 Lead Pitch Inches Package Weight (Grams) 1.39 3.55 1.60 4.20
Leadcount (PD3 (Note
Note: (300 mil) designate PDIP designs which package size what standard that lead count.
VIEW
VIEW
SIDE VIEW
21552B-015
Figure Plastic Dual-In-Line (PDIP)
PDIP
Vantis Package Type Leadcount (JEDEC Drawing Number) Dimension Codes (MS-001(D)AD) 0.140 0.014 0.045 0.008 1.010 0.240 0.300 0.090 0.120 0.015 0.005 0.330
(MS-011(B)AA) 0.140 0.014 0.045 0.008 1.240 0.520 0.600 0.120 0.090 0.015 0.005 0.630
PD3024 (MS-011(B)AA) 0.140 0.014 0.045 0.008 1.150 0.240 0.300 0.120 0.090 0.015 0.005 0.330
(MS-011(B)AB) 0.140 0.014 0.45 0.008 1.440 0.530 0.600 0.090 0.120 0.015 0.005 0.630
PD3028 (288 body) (MO-095(A)AH) 0.140 0.014 0.45 0.008 1.345 0.275 0.300 0.090 0.120 0.015 0.005 0.330
0.200 0.022 0.065 0.015 1.040 0.280 0.325 0.110 0.160 0.060 0.430
0.225 0.022 0.065 0.015 1.280 0.580 0.625 0.160 0.110 0.060 0.700
0.200 0.022 0.065 0.015 1.270 0.280 0.325 0.160 0.110 0.060 0.430
0.225 0.022 0.65 0.015 1.480 0.580 0.625 0.110 0.160 0.060 0.700
0.180 0.022 0.60 0.015 1.385 0.295 0.325 0.110 0.150 0.060 0.430
Notes: dimensions inches. notch, tab, identification mark shall located adjacent device one. Lead thickness increases maximum 0.003 inch when solder lead finish applied. These dimensions include mold flash protrusion. This dimension measured from outside leads 0.015 inch below plane package exit, defined lead. This dimension measured from seating plane base plane. This dimension measured from seating plane from lowest point lead shoulder width that measures 0.040 inch) lead tip. difference between these dimensions should exceed When standoff radii, seating plane location defined where lead width equals 0.040 inch. Vantis' internal designator plastic dual-in-line package.
PDIP
SMALL OUTLINE (SOIC) PLASTIC PACKAGES
SOIC package surface-mount alternative leadcount devices. design similar conventional Dual-In-Line (DIP) package-an attractive feature circuit designers already familiar with DIPs memory boards. Like plastic DIPs, SOIC package consists device attached leadframe, circuitry which wire bonded lead fingers. plastic epoxy material injectionmolded encapsulate device/leadframe configuration. leads extending from long sides rectangular package body trimmed formed gull-wing formation. 50-mil lead pitch SOIC packages allows considerable reduction package size over comparable DIPs, shown table right. only SOIC packages smaller, they lighter, too. This makes them ideal foil/film mounting virtually automated board assembly operations.
Table SOIC (SO)1 Package Size Overview
Package Body Area Inches sq.) 0.149 (96.13) 0.180 (115.51)
Leadcount
Lead Pitch Inches (mm) 0.05 (1.27)
Package Weight (Grams) 0.51 0.62
Note: Vantis' internal abbreviation SOIC package.
21552B-017
Figure JEDEC English
Small Outline (SOIC) Plastic
Vantis Package Type Leadcount Dimension Codes Notes: dimensions inches. identification mark shall located adjacent device one. Dimension measured center line leads. Dimensions increase 0.003 inch maximum leads when solder lead finish applied. Dimension does include dambar protrusion. Allowable protrusion 0.004 inch. Dimensions "A1" measured from base plane contact, which made when packaged allowed rest freely flat, horizontal surface. Lead coplanarity shall within 0.004 inch measured from seating plane. Vantis' internal abbreviation SOIC package. 0.2914 0.3940 0.0926 0.0040 0.0138 0.0091 0.4961 0.050 BASIC 0.2992 0.4190 0.2914 0.3940 0.1043 0.0118 0.0192 0.0125 0.5118 0.0926 0.0040 0.0138 0.0091 0.5985 0.050 BASIC 0.2992 0.4190 0.1043 0.0118 0.0192 0.0125 0.6141
Small Outline (SOIC) Plastic
PACKAGE DESIGN ADVANTAGES
package design offers many advantages over other high leadcount packages. Board Real Estate Savings Because small package size, offers significant savings board real estate, occupying about percent space comparable requires. lower profile, too, about third thick plastic quad flat pack (PQFP) package. Electrical Performance offers superior electrical performance because shorter wirebond lengths help reduce inductance. Comparing 169-ball 160-Pin PQFP, shows percent reduction signal capacitance percent reduction signal time delay. Thermal Performance Studies have been conducted that show that thermally outshines comparable PQFP when fabricated with "thermal vias" (i.e., through-hole vias) underneath pad. These vias allow heat generated device flow board, which would improve thermal performance provided board conducting plane built into more accurately ascertain thermal performance BGA, specific end-use application environment needs considered. Board Assembly Advantages pitch solder balls more manageable during board assembly, than typical 0.5-mm pitch high leadcount Quad Flat Packs (QFPs). BGAs handled with same pick-and-place equipment that used conventional surface-mount devices, including solder reflow methods. During reflow assembly, wetting action solder balls tends pull them into alignment that placement component solder land does need nearly precise with QFP. alignment much mils-more forgiving than mils (0.076 required fine lead-pitch QFPs. Post Assembly Inspections Once mounted board, there challenge inspect ball joints. Thus far, x-ray techniques appear most viable solution, although these systems quite expensive. Once component mounted, removed component remounted; however, there currently process reworking removed component reuse. Vantis' Development Plans Vantis currently shipping packages with body sizes 1.27 ball pitch. Vantis will continue develop other enhanced packages with smaller ball pitches, better thermal performance higher ball counts with smaller body sizes future products.
Package Design
THERMAL CHARACTERIZATION PACKAGES
With increased density complexity CMOS VLSI semiconductor devices, need accurately evaluate thermal properties packaged Integrated Circuits (ICs) fundamental understanding prediction device reliability performance. Failure rates inseparably tied operating temperature device, they increase exponentially temperature device junction rises. Therefore, important that junction temperature every system controlled attain high reliability long operating life. Likewise, understanding thermal properties each component system important addressing overall thermal concerns system level given end-use application environment. Thermal performance data usually measured form thermal resistance thermal impedance characteristics (RJA, JA), used estimate junction temperature device operating given environment. certain amount caution should exercised, however, when using thermal data design evaluate systems because many factors influence thermal performance chip-package combination. These factors include such phenomenon ambient temperature, power dissipation chip, thermal conductivity Printed Circuit Board (PCB), proximity power dissipation neighboring devices, airflow through system. Therefore, important carefully evaluate analyze entire system environment before utilizing standard thermal data. Vantis reports data using JEDEC JESD51 specification format that user approximate effect application environment. following sections detail methodology techniques used Vantis evaluate thermal performance devices, with emphasis fundamental heat flow properties. methods comply with established standards, both government commercial, meet exceed military specifications testing reporting data. thermal data collected still air, moving air, isothermal case temperature, using measurement techniques that conformance with MIL-SPEC 883D, Method 1012.1 specifications. also adhere recently published improved standards thermal test method, environmental considerations, mounting surface specification. These were published Engineering Industries Association (EIA) Joint Electronic Devices Engineering Council (JEDEC), they documented JESD51 series. Vantis, committed providing current relevant thermal information every product manufacture. state-of-the thermal characterization facility, evaluate thermal performance Vantis product. Customers interested product-specific thermal data should contact Vantis sales representative. Terminology most common terminology used industry specifying thermal performance term related forms. These used describe thermal characteristics semiconductor devices various environments such natural forced convection. They also used when simulating infinite heat sink junction-to-case measurements. addition, term been recently defined meet needs users plastic surface-mount packages. Denoted this measurement will allow case temperature measurement during thermal test, which then relate case temperature free convection boundary condition junction temperature. parameter also helps validate junction temperature measurements calculations during thermal characterization.
Package Design
terminology commonly used specify thermal performance, mathematical constructs calculating thermal resistance parameters, provided following pages. Measurement Methods Vantis uses primary test methods evaluate thermal resistance packaged ICs: live device method thermal test method. both methods, utilize heat source that mounted within package. live device method, thermal test chip.
Package Design
Thermal Resistance Terminology
Thermal resistance from junction ambient: resistance from operating portion semiconductor device natural convection (still air) environment; °C/W. Thermal resistance from junction moving air: resistance from operating portion semiconductor device forced convection (moving gas) environment surrounding device; assumed unless stated otherwise; °C/W. Thermal resistance from junction case: resistance from operating portion semiconductor device outside surface package (case) closest chip mounting area when that same surface properly heat sunk minimize temperature variation across surface; °C/W. Thermal resistance from junction reference point: resistance from operating portion semiconductor device defined reference point within specified environment surrounding device; °C/W. Thermal resistance from junction environment: resistance from operating portion semiconductor device defined nonstandard environment surrounding device; °C/W. Thermal resistance from operating portion semiconductor device liquid environment surrounding device; °C/W. Thermal resistance from specified reference location case semiconductor device ambient environment surrounding device; °C/W.
JMA,
Thermal characterization parameter from device junction center
package surface; °C/W.
Junction temperature; Ambient temperature; Case temperature; Reference temperature; standard environment. Reference temperature; non-standard environment. Device power dissipation, steady state; Watts. Device current supply; Amperes. Device voltage supply; Volts. Device power dissipation watts (VCCx ICC). Kfactor; calibration constant determining relationship
Thermally Sensitive Device (TSD); °C/mV.
TSD= Thermally sensitive device: usually semiconductor junction which exhibits
linear relationship temperature over given temperature range with constant current applied; °C/mV. Note: alternative symbol RJR.
continued
Package Design
Sample Calculations: Thermal Resistance
calibration Thermally Sensitive Device (TSD): where:
High calibration temperature calibration temperature High voltage voltage
Note: This measurement made three more temperatures validate linearity TSD. calculating thermal resistance:
where: thermal resistance from junction some specified reference point for: 2.54 below side device under test (see Figure 8.1) JMA: directly upstream from device under test (see Figure 8.3). side package directly adjacent backside die.
calculating relationship between
calculating junction temperature:
where: temperature some specified reference point.
Thermal characterization parameter, calculation: where: TJSS TTSS
thermal resistance some specified reference point, oC/W.
TJSS TTSS
Thermal characterization parameter from surface package air. Device junction temperature steady-state power. package surface, steady-state power, measured thermocouple, infrared sensor, fluoroptic sensor.
Thermal characterization parameter, calculation: where: TTSS TASS
TTSS TASS
Thermal characterization parameter from surface package air. Package (top surface) temperature steady-state power. ambient temperature steady-state power.
calculating relationship between
Package Design
TYPICAL THERMAL RESISTANCE DATA
Table Typical Thermal Resistance Data (TA=25°C. These Parameters Tested.)
Package Style PL44 PL68 PL84 PLH84 PQE160 PQE208 PQE240 PQL48 PQL100 PQL144 PQL176 PQR100 PQR144 PQR160 PQR208 PQT44 PRH100 PRH144 PRH208 BGD256 BGD352 °C/W lfpm 11.5 29.5 14.5 12.2 °C/W lfpm 29.6 13.2 10.8 °C/W
Notes: thermal data generated according EIA/JEDEC specifications JESD51 series. measured packages were surface mounted 2S2P signal, internal plane) boards. only valid packages with direct thermal pathways surface package should only used calculate junction temperature heat sink applied.
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment. live device method provides weighted average values thermal resistance, account spots uneven temperature distributions die. thermal test method preferred, however, because enables power dissipation size easily controlled. following sections provide details these methods calibration process that required.
Package Design
CALIBRATION THERMALLY SENSITIVE DEVICE
When utilizing either live device method thermal test method, Thermally Sensitive Device (TSD) must first calibrated determine characteristics (i.e., change temperature over change voltage). (The appropriate each test method defined sections that follow.) calibration factor (KF) used relate forward voltage temperature, thereby allowing thermal resistance computed using algorithm provided under "Sample Calculations." devices under test calibrated over temperature range interest either convection type oven temperature controlled fluid bath. Live Device Method When measuring thermal characteristics live semiconductor device, device must first biased provide typical power dissipation that device type. Also, must located enable junction temperature measured monitored. most commonly used either substrate isolation diodes input protection diode. Substrate diodes preferred because using input diode temperature sensing only gives temperature information small region die. Substrate isolation diodes, other hand, provide array intrinsic parasitic diodes inherent many semiconductor processes. implement electrical test method live device, device must first forward biased normal operation allowed dissipate power. Then must reverse biased and, specified intervals (usually within from time power removed), must measured determine junction temperature. This also referred voltage-drop method pulse method. parameter actually measured forward voltage drop semiconductor junction. substrate isolation diodes also electrically parallel, junction temperature recorded weighted average hottest junction die, providing typical worst case values. Unfortunately, increasing complexity silicon, live device method less popular widely used high pin-count products. Biasing with correct vectors signals while switching from forward- reverse-bias modes becoming more difficult, some cases impossible. Thermal Test Method When using thermal test method, specially designed thermal test assembled into package. This test contains resistive element power dissipation. Semiconductor junctions (i.e., diodes) used enable temperatures various locations measured. This method used primarily evaluate thermal resistances packages, generically, given range sizes appropriate module size thermal test (usually mils2). These modules arrayed produce larger sizes increments unit module (i.e., mils2, mils2, etc.). thermal test method limited, however, that assumes evenly distributed power dissipation across surface die. This typically produces near-ideal heat source lower thermal resistance results. Therefore, size temperature distribution actual (production) device should taken account when making these types measurements. temperature distribution production device determined noncontact thermometry methods such liquid crystal thermography infrared thermometry. temperature distribution, assuming typical operating conditions, then computed based
Package Design
evidence spots resulting temperature distribution across die. Based this analysis, thermal properties production device correlated with those obtained with thermal test die.
MEASUREMENT ENVIRONMENTS
When using thermal performance data semiconductor devices, extremely important consider effects environment measured modeled values. simulate environments devices will encounter end-use applications, thermal measurements taken still moving environments case package body) environment, explained following sections. Natural Convection (Still-Air) Environment Natural convection measurements (JA) performed chamber which encloses cubic-foot volume still air. diagram still-air chamber shown Figures test board near device under test mounted horizontally vertically, requested) chamber, reference temperatures both inside outside chamber monitored. device allowed come steady state thermal condition both before after heating power applied. Forced Convection (Moving-Air) Environment. Forced convection (JMA)measurements performed laboratory wind tunnel, diagram which shown Figure test boards mounted vertically horizontally, depending requirement. speeds 1200 linear feet minute (lfpm) attainable tunnel. speed monitored using hot-wire anemometer, which mounted stage near device. Case Environment When taking case (JC) measurements, separate apparatus required hermetic versus plastic packages.
21552B-019
Figure Side View Natural Convection Fixture, Which Used Still-Air Tests
Package Design
MOUNTING HOLE THERMOCOUPLE THERMOCOUPLE SUPPORT TUBE 6.75 (17.145)
EDGE CONNECTOR MOUNTING HOLE (2X)
UNITS: INCHES (CENTIMETERS)
21552B-020
Figure Isometric View Natural Convection Fixture
hermetic packages, thermoelectric device cold plate used keep case temperature constant during measurement process. package placed against cold plate held position with adjustable clamp. thin layer thermal grease used thermally contact package test fixture. thermocouple mounted into test fixture that comes contact with package body allow case temperature measurements. Fixtures junction-tocase measurements customized each package style. plastic packages, temperature-controlled fluid bath containing deionized water used. Fluid forced onto package body from both sides from nozzles shown Figure high heat transfer capabilities this method, assume reference temperature that liquid. This measurement relatively technique that essentially provides same boundary conditions cold plate method does hermetic packages. But, caution should used when attempting calculate junction temperature from values plastic packages end-use environments (see following section JT).
Package Design
Hot-Wire Annomometer Probe Station Test Stage
Access Windows
21552B-021
Figure Forced Convection Chamber, Which Used Conduct Moving-Air Tests
nozzle outlet plane fluid number nozzles fluid nozzle diameter pitch between nozzles nozzle-to-package distance
test board
device under test (PQFP)
21552B-022
Figure Nozzle Impingement, Which Used Taking Case Measurements Plastic Package
THERMAL CHARACTERIZATION PARAMETER (JT)
parameter gained popularity misconceptions arising from using value calculate junction temperatures plastic packaged devices end-use environments. This parameter proportional temperature difference between center package junction temperature, relative power dissipation. useful parameter verifying device temperatures end-use environment. sample calculations page provide examples calculations using this parameter.
Package Design
THERMAL TEST BOARDS
Before measuring thermal characteristics semiconductor device, component assembled onto test board using industry-standard techniques. test boards Vantis uses this standardized conform with JEDEDC specification JESD51_3. types test boards commonly used: low-effective high-effective thermal conductivity test boards. Low-Effective Thermal Conductivity Test Boards Low-effective thermal conductivity test boards designed simulate worst-case board mounting. These boards have internal planes minimum trace routing. High-Effective Thermal Conductivity Test Boards High-effective thermal conductivity test boards fabricated have evenly spaced internal planes. These boards more closely reflect applications which ground power planes used PCB. both board types, used board material, small gauge wire used connect device test interface. board dimensions 76.2 wide 114.3 long packages having body sizes package bodies board size 101.6 wide 114.3 long.
76.2
76.2
114.3
114.3
2.54
7.981
2.54
7.981
1.981 1.981 3.962 74.17
9.525
1.981 1.981 3.962 74.17
9.525
21552B-023
21552B-023
Figure Thermal Test Board Design Packages Having Body Sizes Less Than
Figure Thermal Test Board Design Packages Having Body Sizes
(See Figures 21). standardizing board, environment testing normalized board size, allowing comparisons between package families package variations within family. These designs conform JESD specifications.
Package Design
PRODUCT CARRIERS PACKAGE TYPE
Packing methods devices have become increasingly important facilitate automated board assembly optimize packing density. This goal, along with protecting product reliability, drives design concepts behind some packing systems. Vantis offers several packing systems through-hole surface-mount products. table lists those systems that used standard. Vantis' packing system designs have kept pace with sophistication user needs product sensitivity. This section provides in-depth descriptions these designs.
Table Product Carriers Package Type Plastic Dual-In-Line Leadcount leadcounts lead Plastic Leaded Chip Carrier others Plastic Small Outline Shrink Plastic Small Outlines Plastic Quad Flat Pack Thin Plastic Quad Flat Pack Plastic Ball Grid Array Notes: Optional; upon request only Except 028-lead package, which available tape reel. These trays withstand temperatures -125 Device Carrier Tube Tube Tape Reel (Note Tube Tape (Note Tube leadcounts Tape Reel (Notes Tray (Note Tray (Note Packing Container Mini-Q pack 2k/4k pack reel 2k/4k Reel Mini-Q Reel pack tray pack tray
leadcounts configurations
Package Design
Tubes Tubes used unit carriers most lower leadcount packages. product carrier guide next page shows which package families shipped tubes standard. tubes made antistatically coated protect product from electrical mechanical damage. tubes designed accommodate packages that loaded with without unit carriers depending package style. Tube sizes standardized package type facilitate automated board assembly.
DEVICE LOADING
Devices loaded into tubes, with each device uniformly oriented (only product date code tube). variety end-plug designs, antistatic material, secure products tube ensure that there excessive movement product tube during shipping handling. This protects mechanical integrity package leads; also ensures unimpaired dispensing product manufacturing operations. When end-plug design plastic stopper pin, devices loaded oriented toward green stopper manufacturing. This section includes details about quantity devices tube each package style leadcount. Vantis encourages does require ordering shipping full tube quantities. Following quantity tables, dimension drawings tube sizes package type) shown, along with specific end-plug design used. Consult your Vantis sales representative additional information about tubes.
Table Q-Pack Tube Quantity Information
Package Plastic Leaded Chip Carriers Plastic Small Outline lead, square lead, square lead, square lead, square lead, square lead lead Leadcount Devices Tube Tubes (note (note (note Devices 1040 (note (note (note
Notes: tubes actually reflect quantity tubes pack bag, Q-Pack box. device count box, however, accurate because four bags parts box. tubes actually reflect quantity tubes pack bag, Q-Pack box. device count box, however, accurate because three bags parts box.
Tubes
Trays Trays used instead tubes protect higher leadcount packages from electrical mechanical damage during handling shipment. Trays also suitable product presentation board assembly equipment. trays uniformly sized, compliance with standard JEDEC outlines. much possible, Vantis procures trays that made percent recycled material. tray material either carbon-filled antistatically coated provide protection. Trays plastic packages withstand continuous operation temperatures 150°C. Packages placed trays that device oriented notched corner tray, enabling pick-and-place equipment setups compatible packages leadcount. shipment, stack trays secured with straps; five containing parts sixth serving cover. diagrams tables that follow show tray dimensions package quantities parts tray.
NOTCHED CORNER
21552B-026
Figure Five Trays Product Stacked Shipment, With Sixth Tray Serving Cover, Devices Uniformly Oriented Aligned With Notched Corner Tray
Trays
Table Tray Device Carriers: Full Tray Quantity Information Applicable Packages Tray Quantities
Package Plastic Quad Flat Pack PQR, PRH, PQR, PRH, Thin Plastic Quad Flat Pack Plastic Ball Grid Array Leadcount lead lead lead lead lead lead lead lead ball ball Device Tray (Note Trays Devices 1250
Note: cases, tray empty, serving cover.
Trays
Pack Protection Package cracking occur when moisture-sensitive product mounted directly onto board, versus socket mounted, using high temperature solder reflow process. moisture encapsulation material heats vaporizes, pressure creates result package cracking delamination. packing product keeps moisture level encapsulation material below critical level, providing with "solder-safe" packages. Product that packed first baked hours, depending product, then sealed under partial vacuum moisture barrier containing desiccant humidity indicator card. interior maintained safe relative humidity (RH) level 20%. Once product removed from bag, seal broken, product should board mounted within recommended out-of-bag time (assuming assumptions about end-use factory environment reasonably accurate). out-of-bag time factory environment assumptions listed pack caution label that applied outside every pack bag. out-of-bag time exceeded, humidity indicator card upon opening registers then product should baked hours before board mounting. tray which Vantis ships product withstand however, product tubes reels must either metal tubes baked hours Vantis determines moisture sensitivity product testing them JEDEC industrystandard A112-A/A113 process. Depending results, product classified under sensitivity levels, with Level being moisture sensitive, sensitivity rating product indicated pack caution label outside every pack bag. table lists current sensitivity levels Vantis products that packed.
Table Vantis Moisture Sensitive Products
Package Plastic Leaded Chip Carriers (PLCCs) Metric (Note Plastic Quad Flat Packs (PQFPs) Thin Plastic Quad Flat Packs (TQFPs) Small Outline (SO) Plastic Ball Grid Arrays (BGAs) Leadcount Lead lead lead others leadcounts lead ball counts JEDEC Level Out-Of-Bag Time year hours hours hours hours hours hours
Notes: Assumes end-use factory environment Includes PQFP packages denoted internally Vantis PQR, PRH, PQE.
Trays
Tape Reel: Full Reel Quantity Information Tape-and reel device carriers available selected packages, shown table below. This carrier designed protect product from mechanical electrical damage, suitable device presentation automatic pick-and-place equipment. tape-and-reel design consists pocketed carrier tape which loaded with device pocket. Each device oriented pocket that pin-one location complies with Engineering Industries Association Standard 481. protective cover tape heated-sealed over carrier tape keep devices pockets. carrier tape made conductive polystyrene, cover tape antistatic polyester-both which protect product from damage. Once loaded, tape wound onto antistatic plastic reel packing shipment. Each reel labeled with standard inventory label identifying contents. number device full reel provided table shown.
Package
Leadcount lead lead lead lead lead lead (PQT) lead (PQL) lead (PQL) lead (PQL) ball count ball count
Qty/Reel 1000 1000 1500 2000 1000
Plastic Leaded Chip Carrier (PL, PLH)
Plastic Small Outline (SO)
Thin Plastic Quad Flat Pack (PQL, PQT)
Plastic Ball Grid Array (BGD)
Notes: empty trailer pockets provided beginning reel facilitate feeding tape into automatic board assembly equipment. empty leader pockets provided reel.
Trays
CONTROLLING MOISTURE
designing packing materials packing methods, Vantis sensitive susceptibility some packages moisture-induced damage. risk this highest when plastic encapsulation materials used, plastic naturally permeable moisture. moisture package will increase decrease reach Relative Humidity (RH) surrounding environment. Therefore, controlling moisture level package body critical reducing risk moisture-induced damage. Such damage include delamination between plastic encapsulation material, which result open connections broken wirebonds. Package cracking also occur when components exposed high temperatures steep temperature gradients used reflow board assembly techniques. Moisture package rapidly heats vaporizes and, there sufficient steam moisture package having reached critical level, will fracture package escape. This phenomenon known "popcorn effect."
TESTING PRODUCTS MOISTURE SENSITIVITY
better understand classify moisture sensitivity products, Vantis adopted JEDEC test methods A112-A/A113A. These have been adopted industry standard process which determine moisture sensitivity components.
Testing Products Moisture Sensitivity
JEDEC A112-A/A113A Process Flows
JEDEC LEVEL
Electrical Test Visual Inspection Acoustic Microscope Inspection Temp Cycle cycles; -40oC-150oC) High Temp Storage hrs, 125oC) Moisture Soak (unbiased) (168 hrs; 85oC/85% Solder Reflow passes; Tmax 220oC 5oC) Qual Splits Flux Application Visual Inspection Acoustic Microscope Inspection Electrical Test Qual Splits HTOL (except Early Life) Temp Cycle (1000 cycles; -40oC 150oC) Biased Temp Humidity (85oC/85% Visual Inspection Acoustic Microscope Inspection Electrical Test
JEDEC LEVEL LEVEL LEVEL LEVEL LEVEL
flows same except moisture soak parameters (shown below).
(168 85oC/60% (192 30oC/60% 30oC/60% (48/72 30oC/60% 30oC/60%
JEDEC RECOMMENDED OUT-OF-BAG EXPOSURE TIME JEDEC Exposure Factory Level Time Environment unlimited year 30oC 30oC
Electrical Test Pass Moisture Sensitive Fail Test Level Flow
21552B-028
Testing Products Moisture Sensitivity
JEDEC Test Standard A112-A/A113A This test standard (shown page defines different moisture sensitivity levels, referred level level through level Each higher level denotes higher level sensitivity. Product that fails level flow then tested higher level until passes. Specific process steps each flow subject product conditions designed simulate environment end-use application. Subsequent electrical testing inspection steps determine device damaged during environmental stress steps. only difference between each A112-A/A113A flow parameters moisture soak step (also known preconditioning). These parameters designed allow component absorb much moisture given package size. purpose testing determine safe environmental conditions product exposure. Once determined that product moisture sensitive (i.e., fails level flow), Vantis packs product storage shipment. This done regardless type product carrier used (e.g., tubes, trays, reels, etc.). packing protects product from environmental moisture maintaining interior pack percent
PACKING PROCESS MATERIALS
first step pack process remove moisture buildup package baking finished product 15.5 hours, depending package type, While baking, product contained device trays (made material that withstand high temperature) aluminum trays tubes. Within hours after baking, product sealed pack under partial vacuum. sealed using impulse heat sealer seal time seconds; seal pressure psi; temperature range Included pack prescribed number humidity indicator cards desiccant pouches, depending quantity devices bag.
Packing Process Materials
GENERAL REFERENCES
"Thermal Characteristics," Method 1012.1, MIL-STD-883C, Test Methods Procedures Microelectronics, Department Defense, Washington, "Semiconductor Measurement Technology: Thermal Resistance Measurements," F.F. Oettinger D.L. Blackburn, NIST Special Publication 400-86, Department Commerce, Washington, Accepted Practices Making Microelectronic Device Thermal Characteristics Tests User's Guide," JEDEC Engineering Bulletin Electronic Industries Association, Washington, "Still-and Forced-Air Junction-To-Ambient Thermal Resistance Measurements Integrated Circuit Packages," SEMI G38-87 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Junction-To-Case Thermal Resistance Measurements Molded-Plastic Packages," SEMI G43-87 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Junction-to-Case Thermal Resistance Measurements Ceramic Packages," SEMI G30-88 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Unencapsulated Thermal Test Chip," SEMI G32-86 Guideline, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Thermal Test Board Standardization Measuring Junction-to-Ambient Thermal Resistance Semiconductor Packages," SEMI G42-88 Specification, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, "Thermal Transient Testing Attachment Evaluation Integrated Circuits," SEMI G46-88 Test Method, 1989 Book SEMI Standards, Vol. Packaging Division, SEMI, Inc. Mountain View, 10."Applying Electrical Test Method Thermal Characterization Integrated Circuits," B.S. Siegal, SAGE Enterprises, Mountain View, 1985. (Semitherm Conference Proceedings) 11."An Electrical Technique Measurement Integrated Circuit Thermal Resistance," TA7802, Siegal, SAGE Enterprises, Inc. Mountain View, 12."Junction-To-Case Thermal Resistance-Still Myth?," Dutta, National Semiconductor Corp., Santa Clara, Fourth Annual IEEE Semitherm Conference Proceedings 13."How Fast Blowing?: Design Characterization Laboratory Wind Tunnel" Hayward, J.D., Andel, Advanced Micro Devices, Sunnyvale, 14.Microelectronics Packaging Handbook, Tummala, Rymaszewski, Eugene 1989, Nostrand Reinhold 15.EIA/JEDEC JESD51, "Methodology Thermal Measurement Component Packages (Single Semiconductor Device)," Electronic Industries Association, 1995 16.EIA JEDEC JESD 51_1, "Integrated Circuit Thermal Measurement Method Electrical Test Method (Single Semiconductor Device)," Electronic Industries Association, 1995
Reference
17.EIA JEDEC JESD 51_2, "Integrated Circuit Thermal Test Method Environmental Conditions, Natural Convection (Still Air)," Electronic Industries Association, 1995 18.EIA/JEDEC JESD 51_3, "Low Effective Thermal Conductivity Test Board Leaded Surface Mount Packages," Electronic Industries Association, 1995
Reference

EXTERNAL LEAD DESIGNS shape leads leaded surface-mount packages,

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