PALCE610 Family CMOS High Performance Programmable Array Logic

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PALCE610 Family CMOS High Performance Programmable Array Logic

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COM'L: H-15/25
PALCE610 Family
CMOS High Performance Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
Lattice/Vantis Programmable Array Logic (PAL) architecture Electrically-erasable CMOS technology providing half power ICC) high speed 15-ns 25-ns Sixteen macrocells with configurable architecture Registered combinatorial operation Registers programmable J-K,
Lattice/Vantis
Asynchronous clocking product term bank register clocking from external pins Register preload testability Power-up reset initialization Space-saving 24-pin SKINNYDIP 28-pin PLCC packages Fully tested 100% programming yield high reliability Extensive third-party software programmer support through FusionPLD partners
GENERAL DESCRIPTION
PALCE610 general purpose device functionally fuse equivalent EP610. accommodate logic functions with inputs outputs. There macrocells that individually configured user's specifications. macrocells configured either registered combinatorial. registers configured J-K, flip-flops. PALCE610 uses familiar sum-of-products logic with programmable-AND fixed-OR structure. Eight product terms brought each macrocell provide logic implementations. PALCE610 manufactured using advanced CMOS technology providing power consumption. Moreover, high-speed device having worstcase Space-saving 24-pin SKINNYDIP 28-pin PLCC packages offered. This device quickly erased reprogrammed providing easy prototyping. Once device programmed security used provide protection from copying proprietary design.
BLOCK DIAGRAM
I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 CLK1
Programmable Array
CLK2
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
12950G-1
Amendment
2-374
Publication# 12950 Rev. Issue Date: February 1996
CONNECTION DIAGRAMS View SKINNYDIP
CLK1 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 CLK2
12950G-2
PLCC/LCC
CLK1 I/O9 I/O1
I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
I/O16 CLK2 I/O8
12950G-3
Note: marked orientation
DESIGNATIONS
Clock Ground Input Input/Output Connect Supply Voltage
PALCE610 Family
2-375
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable DEVICE NUMBER Gates POWER Half Power ICC) SPEED
OPERATING CONDITIONS Commercial (0°C +75°C) PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PALCE610H-15 PALCE610H-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations, check newly released combinations.
2-376
PALCE610H-15/25 (Com'l)
FUNCTIONAL DESCRIPTION
PALCE610 general purpose programmable logic device. independently-configurable macrocells. Each macrocell configured either combinatorial registered. registers J-K, type flip-flops. device dedicated input pins clock pins. Each clock controls macrocells. programming matrix implements programmable logic array which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input polarity. Unused input pins should tied ground. array uses electrically erasable technology. unprogrammed disconnected programmed connected. Product terms with bits unprogrammed assume logical-HIGH state product terms with both TRUE Complement bits programmed assume logical-LOW state. programmable functions PALCE610 automatically configured from user's design specifications, which number formats. design specification processed development software verify design create programming file. This file, once downloaded programmer, configures design according user's desired function.
asynchronous configuration, clock input controlled product term. output always enabled. configurations, feedback either from output pin. This allows configurations either outputs I/O. configurations, feedback only from therefore, configurations strictly outputs.
Flip-Flop
product terms available gate. input polarity controlled exclusive-OR gate. flip-flop, output level D-input level rising edge clock. Qn+1
Flip-Flop
product terms available gate. input polarity controlled exclusive-OR gate. register, output level toggles when input HIGH remains same when input LOW. Qn+1
Macrocell Configurations
PALCE610 macrocell configured either combinatorial registered. Both combinatorial registered configurations have output polarity control. register configured J-K, type flip-flop. Figure shows possible configurations. Each macrocell select clock either corresponding clock CLK/OE product term. clock selected, output enable controlled CLK/OE product term. CLK/OE product term selected, output always enabled.
Flip-Flop
product terms divided between inputs. product terms input product terms input, where range from Both inputs flip-flop have polarity control exclusive-OR gates. flip-flop operation shown below. Qn+1
Combinatorial
product terms available gate. output-enable function performed CLK/OE product term.
Registered Configurations
There flip-flop types available: S-R. registers configured synchronous asynchronous. synchronous configuration, clock controlled clock input pin. output enable controlled product term function.
PALCE610 Family
2-377
Combinatorial
Register
Register
Register
Register
12950G-4
Figure Macrocell Configurations 2-378 PALCE610 Family
Flip-Flop
product terms divided between inputs. product terms input product terms input, where range from Both inputs flip-flop have polarity control exclusive-OR gates. flip-flop operation shown below.
Allowed Qn+1
Security
After programming verification, PALCE610 design secured programming security bit. Once programmed, this defeats readback internal programmed pattern device programmer, securing proprietary designs from competitors. However, programming verification also defeated security bit. only erased conjunction with array during erase cycle. Preload affected security bit.
Technology
PALCE610 manufactured using advanced Electrically Erasable (EE) CMOS process. This technology uses cell replace fuse link bipolar parts, allows Lattice offer lower-power parts high complexity. addition, since cells erased reprogrammed, these devices 100% factory tested before being shipped customer. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clear switching.
Asynchronous Reset
flip-flops have asynchronous-reset product-term input. When product term true, flip-flop will reset logic LOW, regardless clock data inputs.
Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE610 depend whether they selected registered combinatorial. registered selected, output will LOW. combinatorial selected, output will function logic. rise must monotonic reset delay time 1000 maximum.
Programming Erasing
PALCE610 programmed standard logic programmers. also erased reset previously configured device back virgin state. Bulk erase automatically performed programming hardware. special erase operation required.
CMOS Compatibility
PALCE610 CMOS-compatible outputs. output voltage (VOH) 3.85 -2.0
Register Preload
register PALCE610 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
PALCE610 Family
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PALCE610 LOGIC DIAGRAM (PLCC) Pinouts
CLK1 INPUT
(27)
INPUT
Macrocell
OE/CLK
Macrocell
OE/CLK
(26)
NODE
NODE
Macrocell
OE/CLK
Macrocell
OE/CLK
(25)
NODE
NODE
Macrocell
OE/CLK
Macrocell
OE/CLK
(24)
NODE
NODE
Macrocell
NODE OE/CLK
Macrocell
OE/CLK
(23)
NODE
Macrocell
OE/CLK
Macrocell
OE/CLK
(22)
NODE
NODE
Macrocell
OE/CLK
Macrocell
OE/CLK
(21)
NODE
NODE
(10)
Macrocell
OE/CLK
Macrocell
OE/CLK
(20)
NODE
NODE
(12)
Macrocell
OE/CLK
Macrocell
OE/CLK
(18)
NODE
NODE
INPUT
(13)
(17)
INPUT CLK2
(14,
(16)
12950G-5
2-380
PALCE610 Family
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (Note
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -4.0 -2.0 -150 3.84 0.45 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
PALCE610H-15/25 (Com'l)
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CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT +25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol fMAX Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output Clock Width Maximum Frequency (Note HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 76.1 83.3 61.6 83.3 28.6 29.4 Unit
tARW tARR tCOA tWLA tWHA fMAXA
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Setup Time from Input Feedback Clock (Note Hold Time (Note Clock Output (Note Clock Width Maximum Frequency (Notes (Note HIGH (Note External Feedback 1/(tSA tCOA) Internal Feedback (fCNT) Feedback 1/(tWLA tWHA)
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. These parameters measured using asynchronous product-term clock. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
2-382
PALCE610H-15/25 (Com'l)
SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
12950G-6
Clock Registered Output
12950G-7
Combinatorial Output
Registered Output
Input Clock
12950G-8
0.5V 0.5V
12950G-9
Output
Clock Width
Input Output Disable/Enable
Input Feedback tWHA Product-Term Clock tWLA
12950G-10
tCOA
Product-Term Clock Registered Output
12950G-11
Clock Width Using Product-Term Clock
Registered Output Using Product-Term Clock
Input Asserting Asynchronous Reset
tARW
Registered Output
tARR
Clock Asynchronous Reset
12950G-12
Notes:
Input pulse amplitude Input rise fall times ns-5 typical.
PALCE610 Family
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SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
12950G-13
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
2-384
PALCE610 Family
ENDURANCE
Symbol Parameter Description Pattern Data Retention Time Test Conditions Storage Temperature Operating Temperature Reprogramming Cycles Normal Programming Conditions Unit Years Years Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Program/Verify Protection Circuitry
Typical Input
Preload Circuitry
Feedback Input
Typical Output
12950G-14
PALCE610 Family
2-385
Power-Up Reset
power-up reset feature ensures that flip-flops will reset after device been powered This feature valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide range ways rise
Parameter Symbol
steady state, conditions required insure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
Parameter Description Power-up Reset Time Input Feedback Setup Time Clock Width
1000
Unit
Switching Characteristics
Power
Registered Output
Clock
12950G-15
Power-Up Reset Waveform
2-386
PALCE610 Family
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE610 Family
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PALCE610 Family CMOS High Performance Programmable Array Logic

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