PALCE29M16H-25 24-Pin CMOS Programmable Array Logic DISTINCT

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PALCE29M16H-25 24-Pin CMOS Programmable Array Logic DISTINCT

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COM'L: H-25
PALCE29M16H-25
24-Pin CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
High-performance semicustom logic
Lattice/Vantis
Register/Latch Preload permits full logic
replacement; Electrically Erasable (EE) technology allows reprogrammability
bidirectional user-programmable logic
verification
High speed (tPD fMAX fMAX
internal MHz)
Full-function testing factory
macrocells Combinatorial/Registered/ Latched operation
Output Enable controlled product
high programming functional yields high reliability
24-Pin SKINNYDIP 28-pin plastic
terms
Varied product term distribution increased
leaded chip carrier packages
Extensive third-party software programmer
design flexibility
Programmable clock selection with clocks/
support through FusionPLD partners
latch enables (LEs) LOW/HIGH clock/LE polarity
GENERAL DESCRIPTION
PALCE29M16 high-speed, CMOS Programmable Array Logic (PAL) device designed general logic replacement CMOS digital systems. offers high speed, power consumption, high programming yield, fast programming excellent reliability. devices combine flexibility custom logic with off-the-shelf availability standard products, providing major advantages over other semicustom solutions such gate arrays standard cells, including reduced development time up-front development cost.
BLOCK DIAGRAM
CLK/LE I/CLK/LE I/OF7 I/OF6 I/O7 I/O4 I/OF5 I/OF4
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Programmable Array
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
Logic Macrocell
I/OE
I/OF0
I/OF1
I/O0
I/OF
I/OF3
08740G-1
Publication# 08740 Rev. Issue Date: June 1993 Amendment
2-327
GENERAL DESCRIPTION (continued)
PALCE29M16 uses familiar sum-of-products (AND-OR) structure, allowing users customize logic functions programming device specific applications. provides array inputs outputs. incorporates unique input/output logic macrocell which provides flexible input/output structure polarity, flexible feedback selection, multiple Output Enable choices, programmable clocking scheme. macrocells individually programmed combinatorial, registered, latched with active-HIGH active-LOW polarity. flexibility logic macrocells permits system designer tailor device particular application requirements. Increased logic power been built into PALCE29M16 providing varied number logic product terms output. Eight outputs have product
terms each, four outputs have product terms each, other four outputs have product terms each. This varied product-term distribution allows complex functions implemented single device. Each output dynamically controlled common Output Enable Output Enable product terms bank four outputs. Each output also permanently enabled disabled. System operation been enhanced addition common asynchronous-Preset Reset product terms power-up Reset feature. PALCE29M16 also incorporates Preload Observability functions which permit full logic verification design. PALCE29M16 offered space-saving 300-mil SKINNYDIP package well plastic leaded chip carrier package.
CONNECTION DIAGRAMS View SKINNYDIP
I/OF0 CLK/LE I/OF0 I/OF1 I/O0 I/O1 I/O2 I/O3 I/OF2 I/OF3 I/OE I/OF7 I/OF6 I/O7 I/O6 I/O5 I/O4 I/OF5 I/OF4 I/CLK/LE
08740G-2
PLCC
CLK/LE I/OF7
I/OF6 I/O7 I/O6 I/O5 I/O4 I/OF5
I/OF1 I/O0 I/O1 I/O2 I/O3 I/OF2
I/OF3 I/OE
I/CLK/LE
Note: marked orientation.
I/OF4
08740G-3
DESIGNATIONS
CLK/LE I/CLK/LE I/OF Clock/Latch Enable Ground Input Input Clock/Latch Enable Input/Output Input/Output with Dual Feedback Connection Supply Voltage
2-328
PALCE29M16H-25
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Advanced Macrocell NUMBER FLIP-FLOPS POWER Half Power (100 SPEED PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028) OPTIONAL PROCESSING Blank Standard processing PROGRAMMING REVISION First Revision (Requires current programming Algorithm) TEMPERATURE RANGE Commercial (0°C +75°C)
Valid Combinations PALCE29M16H-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
PALCE29M16H-25 (Com'l)
2-329
FUNCTIONAL DESCRIPTION Inputs
PALCE29M16 inputs drive each product term inputs with both TRUE complement versions available array) shown block diagram Figure these inputs, dedicated inputs, from logic macrocells with feedbacks, from other logic macrocells with single feedback, I/OE input I/CLK/LE input. Initially AND-array gates disconnected from inputs. This condition represents logical TRUE array. selectively programming cells, array connected either TRUE input complement input. When both TRUE complement inputs connected, logical FALSE results output gate.
connected fixed-OR plane. Product terms allocated gates varied distribution across device ranging from wide, with average logic product terms output. increased number product terms output allows more complex functions implemented single device. This flexibility aids implementing functions such counters, exclusive-OR functions, complex state machines, where different states require different numbers product terms. Common asynchronous-Preset Reset product terms connected Registered Latched I/Os. When asynchronous-Preset product term asserted (HIGH) registers latches will immediately loaded with HIGH, independent clock. When asynchronous-Reset product term asserted (HIGH) registers latches will immediately loaded with LOW, independent clock. actual output state will depend macrocell polarity selection. latches must latched mode (not transparent mode) Reset, Preset, Preload, power-up Reset modes meaningful.
Product Terms
degree programmability complexity device determined number connections that form programmable-AND gates. Each programmable-AND gate called product term. PALCE29M16 product terms; these product terms provide logic capability architectural control product terms. Among control product terms, common AsynchronousPreset Reset, Observability, Preload. other eight common Output Enable product terms. Output Enable each bank four macrocells programmed controlled common Output Enable AND/XOR product terms. also permanently enabled permanently disabled. Each product term PALCE29M16 consists 58-input gate. outputs these gates
Input/Output Logic Macrocells
logic macrocell allows user flexibility defining architecture each input output individual basis. also provides capability using associated either input output. PALCE29M16 macrocells, each pin. Each macrocell programmed combinatorial, registered latched operation (see Figure Combinatorial output desired when device used replace combinatorial glue logic. Registers Latches used synchronous logic applications.
Common I/OE Banks Macrocells Common Asynchronous Preset CLK/LE I/CLK/LE Common Asynchronous Reset Array Preset CLK/LE Reset
I/OX
08740G-4
Figure PALCE29M16 Macrocell (Single Feedback) 2-330 PALCE29M16H-25
output polarity each macrocell each three modes operation user-selectable, allowing complete flexibility macrocell configuration. Eight macrocells (I/OF0-I/OF7) have independent feedback paths array (see Figure 2b). first dedicated feedback array combinatorial input. second path consists direct register/latch feedback array. used dedicated input using first feedback path, register/latch feedback path still available array. This path provides capability using register/latch buried state register/latch. other eight macrocells have single feedback path array. This feedback user-selectable either register/latch feedback (see Figure 2a). Each macrocell provide true input/output capability. user select each macrocell register/latch driven either signal generated AND-OR array pin. When selected input, feedback path provides register/latch input array. When used input, each macrocell also user-programmable registered, latched, combinatorial input. PALCE29M16H dedicated CLK/LE I/CLK/LE pin. macrocells have programmable switch choose between these pins clock latch enable signal. These signals clock signals macrocells configured registers latch enable signals macrocells configured latches. polarity these CLK/LE signals also individually programmable. Thus different registers latches driven different clocks clock phases. Output-Enable mode each macrocells selected user. configured output (permanently enabled) input (permanently disabled). also configured
dynamic controlled Output Enable AND-XOR product terms which available each bank four Logic Macrocells.
Logic Macrocell Configuration
unique macrocell offers major benefits through versatile, programmable input/output cell structure, multiple clock choices, flexible Output Enable feedback selection. Eight macrocells with single feedback contain cells, while other eight macrocells contain cells programming input/ output functions (see Table cell controls whether macrocell will combinatorial registered/latched. controls output polarity (active-HIGH active-LOW). determines whether storage element register latch. allows macrocell input register/latch output register/latch. selects direction data path through register/latch. connected usual AND-OR array output, register/latch output connected pin. connected pin, register/latch becomes input register/latch array using feedback data path. Programmable cells allow user select four CLK/LE signals each macrocell. used control Output Enable controlled, two-product-term-controlled, permanently enabled permanently disabled. controls feedback multiplexer macrocells with single feedback path only. Using programmable cells S0-S8 various input output configurations selected. Some possible configuration options shown Figure unprogrammed state (charged, disconnected), architectural cell said have value "1"; programmed state (discharged, connected GND), architectural cell said have value "0."
CLK/LE Reset
Common I/OE Banks Macrocells Common Asynchronous Preset CLK/LE I/CLK/LE Common Asynchronous Reset Array Array Preset
I/OFX
08740G-5
Figure PALCE29M16 Macrocell (Dual Feedback) PALCE29M16H-25 2-331
Table PALCE29M16 Logic Macrocell Architecture Selections
Cell Output Cell Input Cell Storage Element Register Latch
Output Type Combinatorial Register/Latch
Output Polarity Active Active HIGH
Feedback* Register/Latch
*Applies macrocells with single feedback only.
Table PALCE29M16 Logic Macrocell Clock Polarity Output Enable Selections
Clock Edge/Latch Enable Level CLK/LE positive-going edge, active-LOW CLK/LE negative-going edge, active-HIGH I/CLK/LE positive-going edge, active-LOW I/CLK/LE negative-going edge, active-HIGH
Output Buffer Control Pin-Controlled Three-State Enable PT-Controlled Three-State Enable Permanently Enabled (Output only) Permanently Disabled (Input only)
Notes: Erased State (charged disconnected). Programmed State (discharged connected). *Active-LOW means that data stored when HIGH, latch transparent when LOW. Active-HIGH means opposite.
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PALCE29M16H-25
SOME POSSIBLE CONFIGURATIONS INPUT/OUTPUT LOGIC MACROCELL
(For other useful configurations, please refer macrocell diagrams Figure macrocell architecture cells independently programmable).
08740G-6 08740G-7
Output Registered/Active
Output Combinatorial/Active
08740G-8 08740G-9
Output Registered/Active High
Output Combinatorial/Active High
Figure Dual Feedback Macrocells
08740G-10
08740G-11
Output Registered/Active Low, Feedback
Output Combinatorial/Active Low, Feedback
08740G-12
08740G-13
Output Latched/Active High, Feedback
Output Combinatorial/Active High, Feedback
Figure Single Feedback Macrocells PALCE29M16H-25 2-333
POSSIBLE CONFIGURATIONS INPUT/OUTPUT LOGIC MACROCELL
08740G-14
08740G-15
Output Registered/Active Low, Register Feedback
Output Combinatorial/Active Low, Register Feedback
08740G-16
08740G-17
Output Latched/Active Low, Latched Feedback
Output Combinatorial/Active Low, Latched Feedback
Figure Single Feedback Macrocells (continued)
(For Single Feedback Only) Register Latch
Programmable-AND Array
08740G-18
Input Registered/Latched Figure Macrocells
2-334
PALCE29M16H-25
Power-Up Reset
flip-flops power logic predictable system initialization. outputs PALCE29M16 depend whether they selected registered combinatorial. registered selected, output will programmed active HIGH programmed active HIGH. combinatorial selected, output will function logic.
each logic macrocells. This unique feature allows easy debugging tracing buried state machines. addition, capability supervoltage observability also provided.
Security Cell
security cell provided each device prevent unauthorized copying user's proprietary logic design. Once programmed, security cell disables programming, verification, preload, observability modes. only erase protection cell erasing entire array architecture cells, which case proprietary design copied. (This cell should programmed only after rest device been completely programmed verified.)
Preload
simplify testing, PALCE29M16 designed with preload circuitry that provides easy method testing logical functionality. Both product-term-controlled supervoltage-enabled preload modes available. TTL-level preload product term useful during debugging, where supervoltages available. Preload allows arbitrary state value loaded into registers/latches device. typical functional-test sequence would verify possible state transitions device being tested. This requires ability state registers into arbitrary "present state" value device's inputs into arbitrary "present input" value. Once this done, state machine clocked into state, "next state," which checked validate transition from "present state." this transition checked. Since preload provide capability directly desired arbitrary state, test sequences greatly shortened. Also, possible states tested, thus greatly reducing test time development costs guaranteeing proper in-system operation.
Programming Erasing
PALCE29M16 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erasure operation required.
Quality Testability
PALCE29M16 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device yield highest programming yield post-programming functional yield industry.
Technology
high-speed PALCE29M16 fabricated with advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong inputclamp diodes, output slew-rate control, grounded substrate clean switching.
Observability
output register/latch observability product term, when asserted, suppresses combinatorial output data from appearing allows observation contents register/latch output
PALCE29M16H-25
2-335
LOGIC DIAGRAM (PLCC) Pinouts
CLK/LE
I/OF0
INPUT/ OUTPUT MACRO
OBSERVE PRODUCT TERM
23(27) 22(26) I/OF7
INPUT/ OUTPUT MACRO
I/OF1
INPUT/ OUTPUT MACRO
PRESET PRODUCT TERM
INPUT/ OUTPUT MACRO
(25) I/OF6
INPUT/ OUTPUT MACRO
INPUT/ OUTPUT MACRO
(24) I/O7
I/O1
INPUT/ OUTPUT MACRO
(23)
INPUT/ OUTPUT MACRO
Continued Next Page
08740G-19
2-336
PALCE29M16H-25
LOGIC DIAGRAM (PLCC) Pinouts
INPUT/ OUTPUT MACRO
(21)
INPUT/ OUTPUT MACRO
(10)
INPUT/ OUTPUT MACRO
INPUT/ OUTPUT MACRO
(20) I/O4
(11) I/OF
INPUT/ OUTPUT MACRO
INPUT/ OUTPUT MACRO
(19) I/OF
(12) I/OF
INPUT/ OUTPUT MACRO
PRELOAD PRODUCT TERM INPUT/ OUTPUT MACRO
(18) I/OF
(13) I/OE
RESET PRODUCT TERM
(17) (16) I/CLK/LE
08740G-19 (concluded)
PALCE29M16H-25
2-337
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free 75°C Supply Voltage (VCC) with Respect Ground 4.75 5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Output Voltage Test Conditions IOZH IOZL Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note (Note (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open (IOUT -130 0.33 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-338
PALCE29M16H-25 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS Registered Operation
Parameter Symbol Parameter Description Input Combinatorial Output Unit Combinatorial Output
Output Register tSOR tCOR tHOR Input Register tSIR tCIR tHIR Input Register Setup Register Feedback Clock Combinatorial Output Data Hold Time Input Register Input Output Register Setup Output Register Clock Output Data Hold Time Output Register
Clock Frequency tCIS fMAX fMAXI tCWH tCWL Register Feedback Output Register/Latch Setup Maximum Frequency 1/(tSOR tCOR) Maximum Internal Frequency 1/tCIS Clock Width HIGH Clock Width 33.3
AND-OR Array tCIS
tCIS
tSIR
Input Register
Output Register
tCOR
tSOR
tCIR
08740G-20
PALCE29M16H-25 (Com'l)
2-339
SWITCHING WAVEFORMS
Combinatorial Input Combinatorial Output
08740G-21
Combinatorial Output
Combinatorial Input tSOR Clock tHOR tCOR Registered Output
08740G-22
Output Register
Registered Input tSIR Clock tCIR Combinatorial Output tHIR
08740G-23
Input Register
tCIS Clock tCWH tCWL
08740G-24
Clock Width
2-340
PALCE29M16H-25
SWITCHING CHARACTERISTICS Latched Operation
Parameter Symbol tPTD Output Latch tSOL tGOL tHOL tSTL Input Latch tSIL tGIL tHIL Latch Enable tGIS tGWH tGWL Latch Feedback Output Register/Latch Setup Enable Width HIGH Enable Width Input Latch Setup Latch Feedback, Latch Enable Transparent Mode Combinatorial Output Data Hold Time Input Latch Input Output Latch Setup Latch Enable Output Through Transparent Output Latch Data Hold Time Output Latch Input Output Latch Setup Transparent Input Latch Parameter Description Input Combinatorial Output Input Output Transparent Latch Unit Combinatorial Output
AND-OR Array tGIS Output Latch tGOL tPTD
tGIS tSTL tSIL tPTD Input Latch
tSOL tPTD
tGIL tPTD
08740G-25
Input/Output Latch Specs
PALCE29M16H-25 (Com'l)
2-341
SWITCHING WAVEFORMS
Latched Input Combinatorial Input Combinatorial Output tPTD tPTD Latched Transparent
tGWL tGWL
08740G-27
Width
Latched Output
08740G-26
Latch (Transparent Mode)
Latched tGIS Transparent
Transparent Input Latch
Latched
Output Latch
08740G-29
Latched Input Combinatorial Input
Input Output Latch Relationship
tSTL tSOL tHOL Transparent tGOL
Latched Output tSTL
tSTL
Note
08740G-28
Output Latch
Latched Input
Transparent
Combinatorial Output
Note:
Input Latch
08740G-30
combinatorial input changes while latched mode goes into transparent mode after tPTD elapsed, corresponding latched output will change tGOL after goes into transparent mode. combinatorial input change while latched mode goes into transparent mode before tPTD elapsed, corresponding latched output will change later following-tPTD after combinatorial input changes tGOL after goes into latched mode.
2-342
PALCE29M16H-25
SWITCHING CHARACTERISTICS Reset/Preset, Enable
Parameter Symbol tAPO tARO tARI tPZX tPXZ Parameter Description Input Output Register/Latch Reset/Preset Asynchronous Reset/Preset Pulse Width Asynchronous Reset/Preset Output Register/Latch Recovery Asynchronous Reset/Preset Input Register/Latch Recovery Unit
Combinatorial Output
Output Enable Operation I/OE Output Enable I/OE Output Disable (Note Input Output Enable
Input Output Disable (Note Note: Output disable times include test load time constants.
SWITCHING WAVEFORMS
Combinatorial Asynchronous Reset/Preset
Registered/Latched Output Clock
Output Register/Latch Reset/Preset
08740G-31
Combinatorial/ Registered/ Latched Output
Output Disable/Enable
08740G-32
Combinatorial Asynchronous Reset/Preset
Clock
Input Register/Latch Reset/Preset
08740G-33
Combinatorial Input Combinatorial/ Registered/Latched Output
Input Output Disable/Enable PALCE29M16H-25 (Com'l)
08740G-34
2-343
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010
SWITCHING TEST CIRCUIT
Output
08740G-35
Specification tPD, tCO, tGOL tEA, tPZX tER, tPXZ
Switch Closed open closed open closed
Measured Output Value
-0.5 +0.5
2-344
PALCE29M16H-25
PRELOAD
PALCE29M16 capability product-term Preload. When global-preload product term true, PALCE29M16 will enter preload mode. This feature aids functional testing allowing direct setting register states. procedure Preload follows: selected input pins user selected preload condition. Apply desired register value pins. This sets register. value seen pin, after Preload, will depend whether macrocell active high active low.
Parameter Symbol tI/O Parameter Description Delay Time Pulse Width Valid Output
Pulse clock (pin Remove inputs pins. Remove Preload condition. Verify VOL/VOH output pins programmed pattern. Because Preload command product term, input array used Preload (including pins registers). Preload itself will change values pins registers. This will have unpredictable results. Therefore, only dedicated input pins should used Preload command.
Rec.
Unit
Inputs Preload Mode
Pins Data Preloaded
VOH/VIH VOL/VIL
08740G-36
Preload Waveform
PALCE29M16H-25
2-345
OBSERVABILITY
PALCE29M16 capability product-term Observability. When global-Observe product term true, PALCE29M16 will enter Observe mode. This feature aids functional testing allowing direct observation register states. When PALCE29M16 Observe mode, output buffer enabled value will corresponding register. This overrides inputs. procedure Observe Remove inputs pins.
Parameter Symbol tI/O Parameter Description Delay Time Valid Output
inputs user selected Observe configuration. register values will sent corresponding pins. Remove Observe configuration from selected pins. Because Observe command product term, input array used Observe (including pins registers). pins used, observe mode could cause value change, which would cause device oscillate Observe mode. Therefore, only dedicated input pins should used Observe command.
Rec.
Unit
Input Pins
Observe Mode
Pins
08740G-37
Observability Waveform
2-346
PALCE29M16H-25
POWER-UP RESET
registered devices Family have been designed with capability reset during system power-up. Following power-up, registers will reset LOW. output state will depend polarity output buffer. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below.
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width Rise Time
asynchronous operation power-up reset, wide range ways rise steady state, conditions required ensure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Unit
Switching Characteristics
Power
Registered Active Output
Clock
08740G-38
Power-Up Reset Waveform
PALCE29M16H-25
2-347
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal Impedance, Junction Case Thermal Impedance, Junction Ambient Thermal Impedance, Junction Ambient with Flow Ifpm Ifpm Ifpm Ifpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
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PALCE29M16H-25

PALCE29M16H-25 24-Pin CMOS Programmable Array Logic DISTINCT

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