IND: H-10/15/20 PALCE26V12 Family 28-Pin CMOS Versatile Devi
|
|
|
Top Searches for this datasheet
COM'L: H-7/10/15/20
IND: H-10/15/20
PALCE26V12 Family
28-Pin CMOS Versatile Device
DISTINCTIVE CHARACTERISTICS
28-pin versatile programmable logic device architecture Electrically erasable CMOS technology provides half power (only high speed (7.5 propagation delay) dedicated inputs input/output macrocells architectural flexibility Macrocells registered combinatorial, active high active Varied product term distribution allows product terms output
Lattice/Vantis
clock inputs independent functions Global asynchronous reset synchronous preset initialization Register preload testability built-in register reset power-up Space-efficient 28-pin SKINNYDIP PLCC packages Center pins improve signal characteristics Extensive third-party software programmer support through FusionPLD partners
GENERAL DESCRIPTION
PALCE26V12 28-pin version popular PAL22V10 architecture. Built with low-power, highspeed, electrically-erasable CMOS technology, PALCE26V12 offers many unique advantages. Device logic automatically configured according user's design specification. Design simplified design software, allowing automatic creation programming file based Boolean state equations. software also used verify design provide test vectors programmed device. PALCE26V12 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. functions programmed into device through electrically-erasable floating-gate cells logic array macrocells. unprogrammed state, product terms float HIGH. both true complement input connected, term will permanently LOW. product terms connected fixed array with varied distribution from across outputs (see Block Diagram). products feeds output macrocell. Each macrocell programmed registered combinatorial, active high active low, with registered possible. flip-flop clocked clock inputs. output configuration determined four bits controlling three multiplexers each macrocell.
2-306
Publication# 16072 Rev. Issue Date: February 1996
Amendment
BLOCK DIAGRAM
CLK/I
SYNC. PRESET
PROGRAMMABLE ARRAY (52x150)
ASYNC. RESET
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
16072E-1
CONNECTION DIAGRAMS View
CLK2/I3 CLK1/I0 CLK2/I3 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
PLCC
CLK1/I0 I/O11 I/O10
I/O9 I/O8 I/O7 I/O6 I/O5 I/O4
I/O0 I/O1 I/O2 I/O3
I/O0
16072E-2
Note: marked orientation.
16072E-3
DESCRIPTION
Clock Ground Input Input/Output Supply Voltage PALCE26V12 Family 2-307
ORDERING INFORMATION Commercial Industrial Products
Commercial industrial programmable logic products available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Half Power (115 ICC)
OPTIONAL PROCESSING Blank Standard Processing PROGRAMMING DESIGNATOR First Revision (May require programmer update) OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 28-Pin Plastic SKINNYDIP (PD3028) 28-Pin Plastic Leaded Chip Carrier 028) SPEED
Valid Combinations PALCE26V12H-7 PALCE26V12H-10 PALCE26V12H-15 PALCE26V12H-20
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
2-308
PALCE26V12H-7/10/15/20 (Com'l), H-10/15/20 (Ind)
FUNCTIONAL DESCRIPTION
PALCE26V12 fourteen dedicated input lines, which used clock inputs. Unused inputs should tied directly ground VCC. Buffers device inputs feedbacks have both true complementary outputs provide user-selectable signal polarity. inputs drive programmable logic array, which feeds fixed logic array. gates feed twelve macrocells (see Figure macrocell allows eight potential output configurations; registered combinatorial, active high active low, with register feedback (see Figure addition, registered configurations clocked either clock inputs. configuration choice made according user's design specification corresponding programming configuration bits S0-S3 (see Table Multiplexer controls initially float through programmable cell, selecting path through multiplexer. Programming cell connects control line (0), selecting path.
8,8,10,12,14,16
When (unprogrammed) feedback selected When (programmed), feedback opposite that selected
16072E-4
Figure PALCE26V12 Macrocell
Registered Combinatorial
Each macrocell PALCE26V12 includes D-type flip-flop data storage synchronization. flip-flop loaded LOW-to-HIGH edge selected clock input. macrocell configured combinatorial selecting multiplexer path that bypasses flip-flop. Bypass controlled
Table Macrocell Configuration Table
Output Configuration Registered Output Feedback, Active Registered Output Feedback, Active High Combinatorial I/O, Active Combinatorial I/O, Active High Registered I/O, Active Registered I/O, Active High Combinatorial Output, Registered Feedback, Active Combinatorial Output, Registered Feedback, Active High
Programmable Clock
clock input flip-flop selected from either multiplexer controlled determines clock input.
Programmable Feedback
multiplexer allows user determine whether macrocell feedback comes from flip-flop from pin, independent whether output registered combinatorial. Thus, registered outputs have internal register feedback higher speed (fMAX internal), feedback direct input (fMAX external). Combinatorial outputs have feedback, either signal other equations another direct input, register feedback.
Unprogrammed Programmed
Clock Input CLK1/I0 CLK2/I3
PALCE26V12 Family
2-309
feedback multiplexer controlled same (S1) that controls whether output registered combinatorial, 22V10, with additional control (S3) that allows alternative feedback path selected. When selects register feedback registered outputs feedback combinatorial outputs When opposite selected: feedback registered outputs register feedback combinatorial outputs.
Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE26V12 will HIGH depending whether output active active high, respectively. rise must monotonic, reset delay time 1000 maximum.
Register Preload
register PALCE26V12 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, thereby making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Programmable Enable
Each macrocell three-state output buffer controlled individual product term. Enable disable function combination device inputs feedback. macrocell provides bidirectional feedback selected, configured dedicated input buffer always disabled. This accomplished connecting inputs enable term, forcing complemented inputs always LOW. permanently enable outputs, inputs left disconnected from term (the unprogrammed state).
Security
After programming verification, PALCE26V12 design secured programming security bit. Once programmed, this defeats readback internal programmed pattern device programmer, securing proprietary designs from competitors. Programming security disables preload, array will read every disconnected. security only erased conjunction with erasure entire pattern.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection controlled programmable output macrocell, affects both registered combinatorial outputs. Selection automatic, based design specification definitions. definition output equation have same polarity, output programmed active high.
Programming Erasing
PALCE26V12 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Quality Testability
PALCE26V12 offers very high level built-in quality. erasability device provides means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming yields post-programming functional yields industry.
Preset/Reset
initialization, PALCE26V12 additional Preset Reset product terms. These terms connected registered outputs. When Synchronous Preset (SP) product term asserted high, output registers will loaded with HIGH next LOW-to-HIGH clock transition. When Asynchronous Reset (AR) product term asserted high, output registers will immediately loaded with independent clock. Note that preset reset control flip-flop, output pin. output level determined output polarity selected.
Technology
high-speed PALCE26V12 fabricated with advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clean switching.
2-310
PALCE26V12 Family
Registered Active-Low Output, Register Feedback
Registered Active-High Output, Register Feedback
Registered Active-Low
Registered Active-High
Registered Outputs
Combinatorial Active-Low
Combinatorial Active-High
Combinatorial Active-Low Output, Register Feedback
Combinatorial Active-High Output, Register Feedback
Combinatorial Outputs
16072E-5
Figure PALCE26V12 Macrocell Configuration Options PALCE26V12 Family 2-311
LOGIC DIAGRAM
PALCE26V12
ASYNCH. RESET
CLK1
When (unprogrammed) feedback selected When (programmed), feedback opposite that selected
16072E-6
2-312
PALCE26V12 Family
LOGIC DIAGRAM (continued)
PALCE26V12
CLK1
I/O5
I/O4
I/O3
I/O2
I/O1
SYNCH PRESET
When (unprogrammed) feedback selected When (programmed), feedback opposite that selected
16072E-6 (concluded)
PALCE26V12 Family
2-313
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.6 +7.0 Output Voltage -0.5 Static Discharge Voltage 2001
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) (Dynamic) (Dynamic) Industrial Supply Current Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Test Conditions -3.2 -170 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note
Input HIGH Leakage Current 5.25 (Note Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT H-7/10 Max, H-7/10 Outputs Open (IOUT Max, H-10
Commercial Supply Current
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-314
PALCE26V12H-7/10 (Com'l), H-10 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT +25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR fMAX Maximum Frequency (Notes Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Setup Time from Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback Internal Feedback (fCNT) 1/(tS tCO) 1/(tS tCF) 105.3 71.4 Unit
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE26V12H-7/10 (Com'l), H-10 (Ind)
2-315
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.6 +7.0 Output Voltage -0.5 Static Discharge Voltage 2001
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 lndustrial Devices Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) (Dynamic) (Static) (Dynamic) Industrial Supply Current Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Commerical Supply Current Test Conditions -3.2 -160 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT H-15/20 Max, Outputs Open (IOUT H-15 Max, Outputs Open (IOUT H-20 Outputs Open (IOUT H-20 Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-316
PALCE26V12H-15/20 (Com'l, Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT +25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback, Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width Maximum Frequency (Notes HIGH External Feedback Internal Feedback (fCNT) 1/(tS tCO) 1/(tS tCF) 58.8 Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE26V12H-15/20 (Com'l, Ind)
2-317
SWITCHING WAVEFORMS
Input Feedback Input Feedback Clock Combinatorial Output
16072E-7
16072E-8
Registered Output
Combinatorial Output
Registered Output
Input Clock Output 0.5V 0.5V
16072E-10
Clock Width
16072E-9
Input Output Disable/Enable
tARW Input Asserting Asynchronous Reset Registered Outputs tARR Clock
16072E-11
Input Asserting Synchronous Preset Clock Registered Outputs
tSPR
16072E-12
Asynchronous Reset
Synchronous Preset
Notes: Input pulse amplitude Input rise fall times ns-5 typical.
2-318
PALCE26V12 Family
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
16072E-13
Specification tPD,
Closed Open Closed Open Closed
Com'l: H-15/20 Ind: H-20 Com'l: H-7/10 Ind: H-10/15
Measured Output Value
PALCE26V12 Family
2-319
TYPICAL CHARACTERISTICS PALCE26V12H-7/10
25°C
(mA)
16072E-14
Frequency (MHz)
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
2-320
PALCE26V12 Family
ENDURANCE CHARACTERISTICS
PALCE26V12 manufactured using advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles
parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
Unit Years Years Cycles
PALCE26V12 Family
2-321
Bus-Friendly Inputs
PALCE26V12H-7/10 (Com'l) H-10/15 (Ind) inputs loop back input after second stage input buffer. This configuration reinforces
state input pulls voltage away from input threshold voltage where noise cause oscillations. illustration this configuration, below.
INPUT/OUTPUT EQUIVALENT SCHEMATICS REV. VERSION*
Protection
Input
Preload Circuitry
Feedback Input
16072E-15
Output
Device PALCE26V12H-7 PALCE26V12H-10 PALCE26V12H-15 Rev. Letter
Topside Marking: CMOS PLDs marked package following manner: PALCE xxxx Datecode numbers) characters) (Rev. Letter) Rev. letter separated spaces.
2-322
PALCE26V12 Family
ROBUSTNESS FEATURES
PALCE26V12 some unique features that make extremely robust, especially when operating high speed design environments. Input clamping circuitry limits negative overshoot, eliminating possibility
false clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about
INPUT/OUTPUT EQUIVALENT SCHEMATICS REV. VERSION*
Protection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input
16072E-16
Typical Output
Device PALCE26V12-15 PALCE26V12-20
Rev. Letter
Topside Marking: CMOS PLDs marked package following manner: PALCE xxxx Datecode numbers) characters) (Rev. Letter) Rev. letter separated spaces.
PALCE26V12 Family
2-323
POWER-UP RESET
power-up reset feature ensures that flip-flops will reset after device been powered output state will depend programmed configuration. This feature valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width
range ways rise steady state, conditions required ensure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
1000
Unit
Switching Characteristics
Power
Registered Active-Low Output
Clock
16072E-17
Power-Up Reset Waveform
2-324
PALCE26V12 Family
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
PALCE26V12
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE26V12H-15/20
2-325
Other recent searches
TMS320C6000 - TMS320C6000 TMS320C6000 Datasheet
STD-402 - STD-402 STD-402 Datasheet
QC300801 - QC300801 QC300801 Datasheet
US0001 - US0001 US0001 Datasheet
MVL-324DRDL - MVL-324DRDL MVL-324DRDL Datasheet
M62301SP - M62301SP M62301SP Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
