PALCE24V10H-15/25 CMOS 28-Pin Universal Programmable Array Logic

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PALCE24V10H-15/25 CMOS 28-Pin Universal Programmable Array Logic

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COM'L: H-15/25
PALCE24V10H-15/25
CMOS 28-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
Electrically erasable CMOS technology provides reconfigurable logic full testability High speed CMOS technology 15-ns propagation delay "-15" version 25-ns propagation delay "-25" version Outputs individually programmable registered combinatorial Programmable output polarity
Lattice/Vantis
Programmable enable/disable control Preloadable output registers testability Automatic register reset power-up Cost-effective 28-pin plastic SKINNYDIP PLCC packages Extensive third-party support through FusionPLD partners Fully tested 100% programming functional yields high reliability
GENERAL DESCRIPTION
PALCE24V10 advanced device built with low-power, electrically-erasable CMOS technology. macrocells provide universal device architecture. PALCE24V10 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floatinggate cells logic array that erased electrically. fixed array allows eight product terms output logic functions. these products feeds output macrocell. Each macrocell programmed registered combinatorial with active-high active-low output. output configuration determined global bits local controlling four multiplexers each macrocell.
BLOCK DIAGRAM
I1-I12, I14,
CLK/I0
Programmable Array
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
Input
Input
OE/I13
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
12222F-1
Publication# 12222 Rev. Issue Date: February 1996
Amendment
2-291
CONNECTION DIAGRAMS View SKINNYDIP
PLCC
CLK/I0
I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I13
12222F-2
OE/I13 I/O0 I/O1 I/O2
12222F-3
I/O9
CLK/I0
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3
Note: marked orientation.
DESIGNATIONS
Clock Input Input/Output Output Enable Supply Voltage Ground
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PALCE24V10H-15/25
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Half Power (115 ICC) SPEED
OPERATING CONDITIONS Commercial (0°C +75°C) PACKAGE TYPE 28-Pin Plastic SKINNYDIP (PD3028) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PALCE24V10H-15 PALCE24V10H-25
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
PALCE24V10H-15/25 (Com'l)
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FUNCTIONAL DESCRIPTION
PALCE24V10 universal device. independently configurable macrocells (MC0.MC9). Each macrocell configured registered output, combinatorial output, combinatorial I/O, dedicated input. programming matrix implements programmable logic array, which drives fixed logic array. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Pins serve either array inputs clock (CLK) output enable (OE) flip-flops.
Unused input pins should tied directly GND. Product terms with bits unprogrammed (disconnected) assume logical HIGH state product terms with both true complement input signal connected assume logical state. programmable functions PALCE24V10 automatically configured from user's design specification, which number formats. design specification processed development software verify design create programming file. This file, once downloaded programmer, configures device according user's desired function.
SL0X SL1X Macrocells SL0X
I/OX
SL0X SL1X Macrocells SL0X
I/OX
From Adjacent
12222F-4
PALCE24V10 Macrocell
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PALCE24V10H-15/25
Configuration Options
Each macrocell configured following: registered output, combinatorial output, combinatorial dedicated input. registered output configuration, output buffer enabled pin. combinatorial configuration, buffer either controlled product term always enabled. dedicated input configuration, buffer always disabled. macrocell configurations controlled configuration control word. contains global bits (SG0 SG1) local bits (SL00 through SL09 SL10 through SL19). determines whether registers will allowed. determines whether output buffer user-controlled fixed state. Within each macrocell, SL0x, conjunction with SG1, selects configuration macrocell SL1x sets output either active active high. configuration bits work acting control inputs multiplexers macrocell. There four multiplexers: product term input, enable select, output select, feedback select multiplexer. SL0x control signals four multiplexers. MC9, added feedback multiplexer. These configurations summarized table illustrated figure PALCE24V10 configured combinatorial device, pins available inputs array. device configured with registers, pins cannot used data inputs.
Dedicated Input Non-Registered Device
control settings SL0x output buffer disabled. feedback signal pin.
Combinatorial Non-Registered Device
control settings SL0x Only seven product terms available gate. eighth product term used enable output buffer. signal back array feedback multiplexer. This allows used input.
Combinatorial Registered Device
control settings SG0=0,SG1=1 SL0x Only seven product terms available gate. eighth product term used output enable. feedback signal corresponding signal. Table Macrocell Configurations
SL0x Cell Configuration Registered Output Combinatorial
Device registers
Device registers Combinatorial Output Dedicated Input Combinatorial
Registered Output Configuration
control settings SL0x There only registered configuration. eight product terms available inputs gate. Data polarity determined SL1x. SL1x input exclusive-OR gate which input flipflop. SL1x programmed inverted output non-inverted output. flip-flop loaded LOWto-HIGH transition CLK. feedback path from register. output buffer enabled
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection made through programmable SL1x which controls exclusive-OR gate output AND/OR logic. output active high SL1x active SL1x
Combinatorial Configurations
PALCE24V10 three combinatorial output configurations: dedicated output non-registered device, non-registered device registered device.
Dedicated Output Non-Registered Device
control settings SL0x eight product terms available gate. Because macrocell dedicated output, feedback used.
PALCE24V10H-15/25
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Registered Active
Registered Active High
Combinatorial Active
Combinatorial Active High
Combinatorial Output Active
Combinatorial Output Active High
Dedicated Input
12222F-5
Figure Macrocell Configurations Figure Macrocell Configurations
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PALCE24V10H-15/25
Power-Up Reset
flip-flops power logic predictable system initialization. Outputs PALCE24V10 depend whether they selected registered combinatorial. registered selected, output will HIGH. combinatorial selected, output will function logic.
Programming Erasing
PALCE24V10 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Quality Testability Register Preload
register PALCE24V10 Series preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery. PALCE24V10 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, verifies complete programmability functionality this device yield highest programming yields post-programming function yields industry.
Technology
PALCE24V10 fabricated with advanced electrically-erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input-clamp diodes, output slew-rate control, grounded substrate clean switching.
Security
security provided PALCE24V10 deterrent unauthorized copying array configuration patterns. Once programmed, this defeats readback programmed pattern device programmer, securing proprietary designs from competitors. However, programming verification also defeated security bit. only erased conjunction with array during erase cycle.
Electronic Signature Word
electronic signature word provided PALCE24V10. consists bits programmable memory that contain user-defined data. signature data always available user independent security bit.
PALCE24V10H-15/25
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LOGIC DIAGRAM
CLK/I
12222F-6
2-298
PALCE24V10H-15/25
LOGIC DIAGRAM (continued)
OE/I13
12222F-6 (concluded)
PALCE24V10H-15/25
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -150 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note Outputs Open (IOUT Max,
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
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PALCE24V10H-15/25 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Descriptions Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Clock Width Maximum Frequency (Notes Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Clock Hold Time Clock Output HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) 1/(tWH tWL) 83.3 41.6 62.5 Unit
fMAX
tPZX tPXZ
Output Enable (Note Output Disable (Note Input Output Enable Using Product Term Control (Note Input Output Disable Using Product Term Control (Note
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE24V10H-15/25 (Com'l)
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SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
12222F-7
Clock
Registered Output
12222F-8
Combinatorial Output
Registered Output
Input Output 0.5V 0.5V
12222F-9
tPXZ Output 0.5V 0.5V tPZX
12222F-10
Input Output Disable/Enable
Output Disable/Enable
Clock
12222F-11
Clock Width
Notes: Input pulse amplitude Input rise fall times ns-5 typical.
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PALCE24V10H-15/25
SWITCHING WAVEFORMS
WAVEFORM
INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output
12222F-12
Specification tPD, tPZX, tPXZ,
Closed Open Closed Open Closed
Measured Output Value
PALCE24V10H-15/25
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ENDURANCE CHARACTERISTICS
PALCE24V10 manufactured using advanced electrically erasable process. This technology uses cell replace fuse link used bipolar
parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Endurance Characteristics
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions Unit Years Years Cycles
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Program/Verify Protection Circuitry
Typical Input
Preload Circuitry
Feedback Input
Typical Output
12222F-14
2-304
PALCE24V10H-15/25
POWER-UP RESET
PALCE24V10 been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below.
Parameter Symbol Parameter Description Power-Up Reset Time Input Feedback Setup Time Clock Width
synchronous operation power-up reset wide range ways rise steady state, conditions required ensure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
1000 Switching Characteristics Unit
Power
Registered Output
Clock
12222F-15
Power-Up Reset Waveform
PALCE24V10H-15/25
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PALCE24V10H-15/25 CMOS 28-Pin Universal Programmable Array Logic

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