IND: H-7/10/15/20 PALCE20RA10 Family 24-Pin Asynchronous CMO

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IND: H-7/10/15/20 PALCE20RA10 Family 24-Pin Asynchronous CMO

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COM'L: H-7/10/15/20
IND: H-7/10/15/20
PALCE20RA10 Family
24-Pin Asynchronous CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
power fast maximum propagation delay fMAX (external) Individually programmable asynchronous clock, preset, reset, enable Registered combinatorial outputs Programmable polarity Programmable replacement high-speed CMOS logic
Lattice/Vantis
TTL-level register preload testability Extensive third-party software programmer support through FusionPLD partners 24-pin PDIP 28-pin PLCC packages save space versions utilize split leadframes improved performance
GENERAL DESCRIPTION
PALCE20RA10 advanced device built with low-power, high-speed, electrically-erasable CMOS technology. PALCE20RA10 offers asynchronous clocking each flip-flops device. macrocells feature programmable clock, preset, reset, enable, operate asynchronously other macrocells same device. PALCE20RA10 also flip-flop bypass, allowing combination registered combinatorial outputs. PALCE20RA10 utilizes familiar sum-of-products (AND/OR) architecture that allows users implement complex logic functions easily efficiently. Multiple levels combinatorial logic always reduced sum-of-products form, taking advantage very wide input gates available devices. equations programmed into device through floating-gate cells logic array that erased electrically.
BLOCK DIAGRAM
Output Enable
Dedicated Inputs Preload
Programmable Array
Enable
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro Preload
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9 15434H-1
Amendment
2-184
Publication# 15434 Rev. Issue Date: February 1996
CONNECTION DIAGRAMS View SKINNYDIP
PLCC JEDEC
I/O9 I/O8
I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I/O0 I/O1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2
15434H-2
15434H-3
Note: marked orientation.
DESIGNATIONS
Ground Input Input/Output Connect Output Enable Preload Supply Voltage
PALCE20RA10 Family
2-185
ORDERING INFORMATION Commercial Industrial Products
Programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Registered Asynchronous NUMBER OUTPUTS POWER Half Power (ICC SPEED OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028)
Valid Combinations PALCE20RA10H-7 PALCE20RA10H-10 PALCE20RA10H-15 PALCE20RA10H-20
Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
2-186
PALCE20RA10H-7/10/15/20 (Com'l, Ind)
Commercial Industrial Products
Output
15434H-5
Figure PALCE20RA10 Macrocell
FUNCTIONAL DESCRIPTION
PALCE20RA10 dedicated input lines programmable macrocells. Registered Asynchronous (RA) macrocell shown Figure serves global register preload serves global output enable. Programmable output polarity available provide user-programmable output polarity each individual macrocell. programmable functions PALCE20RA10 automatically configured from user's design specification, which number formats. design specification processed development software verify design create programming file. This file, once downloaded programmer, configures device according user's desired function.
Programmable Clock
clock input each flip-flop comes from programmable array, allowing flip-flop clocked independently desired.
Registered/Active
Combinatorial/Active
Programmable Preset Reset
each macrocell, product lines dedicated asynchronous preset asynchronous reset. preset product line HIGH, output register becomes logic output will logic reset product line HIGH, output register becomes logic output will logic operation programmable preset reset overrides clock.
Registered/Active High
Combinatorial/Active High
15434H-6
Combinatorial/Registered Outputs
both preset reset product lines HIGH, flip-flop bypassed output becomes combinatorial. Otherwise, output from register. Each output configured combinatorial registered.
Figure Macrocell Configurations
PALCE20RA10 Family
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Three-State Outputs
devices provide product term dedicated local output control. There also global output control pin. output enabled both global output control local output control product term HIGH. global output control HIGH, outputs will disabled. local output control product term LOW, then that output will disabled.
Output Register Preload
output registers PALCE20RA10 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery. Register preload controlled TTL-level signal, making convenient board-level initialization function. Details output register preload found page
Security
security also provided prevent unauthorized copying device patterns. Once programmed, circuitry enabling verification permanently disabled, array will read every programmed. With verification operating, impossible simply copy device pattern device programmer. security only erased conjunction with entire pattern.
Power-Up Reset
flip-flops power logic predictable system initialization. Registered outputs PALCE20RA10 will HIGH output inverter. state combinatorial outputs will function logic. Details power-up reset found page
Programmable Polarity
outputs programmed either active-LOW active-HIGH. This represented Exclusive-OR gate shown PALCE20RA10 logic diagram. When output polarity programmed, lower input Exclusive-OR gate HIGH, output activeHIGH. Similarly when output polarity unprogrammed, output active-LOW. programmable output polarity feature allows user higher degree flexibility when writing equations.
Quality Testability
PALCE20RA10 offers very high level built-in quality. erasability device provides means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming yields post-programming functional yields industry.
Programming Erasing
PALCE20RA10 programmed standard logic programmers. Approved programmers listed this databook. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Technology
high-speed PALCE20RA10 fabricated with advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clean switching.
2-188
PALCE20RA10 Family
LOGIC DIAGRAM SKINNYDIP (PLCC JEDEC) Pinouts
(28)
(27)
(26)
(25)
(24)
(23)
(21)
(20)
(10)
(19)
(11)
(18)
(12)
(17)
(13) (14)
(16)
15434H-7
PALCE20RA10 Family
2-189
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25 Industrial Devices Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol Parameter Description Output HIGH Voltage Test Conditions -3.2 Guaranteed Input Logical HIGH (Note Guaranteed Input Logical (Note VOUT (Note VOUT (Note VOUT (Note Outputs Open -7/10/15 IOUT Max, (Note Outputs Open -7/10/15 IOUT Max, (Note -100 -100 -130 Unit
Output Voltage
IOZH IOZL (Static) (Static)
Input HIGH Voltage Voltage Inputs Input Voltage Voltage Inputs Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Commercial Supply Current Industrial Supply Current
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter guaranteed under worst case test conditions.
2-190
PALCE20RA10H-7/10/15/20 (Com'l, Ind)
CAPACITANCE (Note
Parameter Symbol Parameter Description Input Capacitance Inputs COUT Output Capacitance VOUT Test Conditions +25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description tAPW tAPR tARW tARR fMAX tPZX tPXZ Maximum Frequency (Note Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Feedback Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Clock Width HIGH External Feedback 1/(tS tCO) Feedback 1/(tWH tWL) 76.9 52.6 62.5 41.6 Unit
Output Enable Output Disable Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control Preload Pulse Duration Preload Setup Time Preload Hold Time
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where these parameters affected. These parameters 100% tested, calculated initial characterization time design modified where frequency affected.
PALCE20RA10H-7/10/15/20 (Com'l, Ind)
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SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
15434H-8
Clock
Registered Output
15434H-9
Combinatorial Output
Registered Output
tARW
Input Asserting Asynchronous Preset Registered Output
tAPW tAPR
Input Asserting Asynchronous Reset
Registered Output
15434H-10
tARR
Clock
Clock
15434H-11
Asynchronous Preset
Asynchronous Reset
Clock
15434G-12
Clock Width
Input Feedback Output 0.5V 0.5V
15434H-13
tPXZ Output 0.5V 0.5V
tPZX
15434H-14
Input Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times typical.
Output Disable/Enable
2-192
PALCE20RA10 Family
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
15434H-15
Commercial Industrial Specification tPD, tPZX, tPXZ, Closed Open Closed Open Closed except H-20: H-20: except H-20: H-20: Measured Output Value
PALCE20RA10 Family
2-193
TYPICAL CHARACTERISTICS 25°C
PALCE20RA10 Family
(mA)
15434H-16
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
2-194
PALCE20RA10 Family
ENDURANCE CHARACTERISTICS
PALCE20RA10 manufactured using advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles
parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
Unit Years Years Cycles
Robustness
PALCE20RA10 been designed with some unique features that make extremely robust, even when operating high-speed design environments. Pull-up resistors inputs I/Os cause unconnected pins default HIGH state. Please note that these pull-up resistors only this purpose, provide enough current sufficiently pull line high. recommend that external pull-up
pull-down resistors used condition floating line exists. Input-clamping circuitry limits negative overshoot, eliminating possibility false clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection Clamping
Programming Pins Only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input
15434H-17
Typical Output PALCE20RA10 Family 2-195
POWER-UP RESET
PALCE20RA10 been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will HIGH independent logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width Power
wide range ways rise steady state, conditions required ensure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
1000
Unit
Switching Characteristics
Registered Output
Clock
Power-Up Reset Waveform
15434H-18
OUTPUT REGISTER PRELOAD
preload function allows register loaded from output pins. This feature aids functional testing sequential designs allowing direct setting output states. procedure preloading follows. Disable output registers. Apply either registered outputs. Leave combinatorial outputs floating. Pulse from VIH. Remove VIL/VIH from registered output pins.
Output Disable/Enable
Enable output registers. Verify VOL/VOH registered output pins. Note that because output inverter, register that been preloaded HIGH will provide output. Also note that because there inverter register preload input, level presented register preload input time preload will present register output following preload sequence e.g., register time preload will result that after preload.
Register Outputs
Preload Clock
Output Register Preload Waveform 2-196 PALCE20RA10 Family
15434H-19

IND: H-7/10/15/20 PALCE20RA10 Family 24-Pin Asynchronous CMO

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