Error detection techniques allow receiver determine when message been

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Error detection techniques allow receiver determine when message been

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32-Bit Error Checking Using ispLSI 2128E
Error detection techniques allow receiver determine when message been corrupted during transmission though noisy channel. This typically done having transmitter calculate value (often known checksum) based message transmitted. This checksum then appended message transmitted. receiver then re-calculate this checksum message received compare transmitted checksum determine there were errors during transmission. Traditional checksum calculations used simple summing formulas. traditional formulas random enough detect transmission errors that occur that checksum internally consistent (i.e. multiple errors resulting same checksum). This seen following simple checksum example: Message Message with checksum Message after transmission
original data. CRCCs very effective variety reasons: They provide good protection against many common errors. original data first part transmission. They easy understand implement. They well suited process serial data streams. They consume hardware resources. CRCCs used verify frame data treating entire frame very large binary number. This number divided generator number remainder produced. This remainder then transmitted along with data. receiver end, incoming data again divided same generator number, remainder compared against transmitted checksum. remainders different, transmission error occurred. Because implementation division operations practical CPLDs, incoming information must converted form that computationally intensive. incoming stream represented coefficients large polynomial. example: 1001001000000100 This polynomial then divided generator polynomial that chosen different error detection capabilities. Optimum error detection achieved choosing generator polynomial that detect expected transmission errors. Several standard generator polynomials different transmission mediums shown Table
above case, that although entire message been corrupted, checksum remains same. inherent problem with using simple summing formulas calculating checksums that probability detecting error only dependent width incoming data words, width checksum itself. Thus, 32-bit summing checksum same probability missing error 8-bit checksum when data transmitted byte form. problem only overcome having sophisticated formula that causes each incoming byte have effect entire checksum register. Thus requirements good checksum calculation that checksum register width sufficiently large (e.g. bits gives 1/(232) chance error). checksum formula designed such that each incoming byte potential affect number bits checksum register.
Serial Implementation
Although math behind calculation somewhat complicated beyond scope this document, implementation almost trivial serial computation. calculations implemented using linear feedback shift registers (LFSRs). LFSRs will yield same results subtract shift division process. Figure shows CCITT CRC-16 generator. advantages this type implementation that comparison remainders done automatically. When checksum shifted through
Error Checking
Cyclic Redundancy Codes(CRCs) popular type redundant encoding. Cyclic redundancy code checkers (CRCCs) test differences between transmitted
an8030_01
October 1998
32-Bit Error Checking Using ispLSI 2128E
Table Common Generator Polynomials
Generator Name SDLC (CCITT) SDLC Reverse CRC-16 CRC-16 Reverse CRC-12 CRC-32 (Ethernet)
Polynomial
Figure LFSR CRC-16 Implementation
XOR0 Register Register XOR5 Register Register XOR12 Register Register
XOR16 Data
LFSR after incoming data, "new" checksum should zero transmission error free.
Post-Route Design Implementation: Number Macrocells: Number GLBs: Number IOCs: Number DIs: Number Levels:
VHDL 32-bit Serial Implementation
VHDL code written implement 32-bit serial calculation. 32-bit LFSR with clock enable constructed instantiating D-type flip-flops linking them together. There check signal that when asserted high calculates 32-bit from incoming serial data stream while also passing data through serial output. When check signal asserted low, 32-bit calculation shifted out. error signal compares register zero. non-zero value indicates that transmission error occurred. design compiled synthesized using Viewlogic® Workview® Office version 7.4. design using Lattice ispDesignEXPERTCompiler ispLSI 2128E. post-route design statistics given below: Utilization (Out 32): Utilization (Out 136): Utilization (Out 264):
maximum clock frequency design calculated using ispEXPERT Static Timing Analyzer found just over 150MHz.
Conclusion
error checking used variety telecommunications data communications applications. Many these applications involve transmission reception data serial format with data rates below 100Mbps. LFSR approach well suited processing data serial format, achieve relatively high performance without wasting valuable hardware resources. source code files this design available from your local Lattice Field Applications Engineer e-mail from Lattice Semiconductor Applications Engineering Group ispgenapps@latticesemi.com applications@latticesemi.com.

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