In-System Programmable High Density Features ENHANCEMENTS ispLSI
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ispLSI 2064/A
In-System Programmable High Density Features
ENHANCEMENTS ispLSI 2064A Fully Form Function Compatible ispLSI 2064, with Identical Timing Specifcations Packaging ispLSI 2064A Built Advanced 0.35 Micron E2CMOS® Technology
Output Routing Pool (ORP)
Input
Functional Block Diagram
Output Routing Pool (ORP)
2000 Gates Pins, Four Dedicated Inputs Registers High Speed Global Interconnect Wide Input Gating Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size Random Logic HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax Maximum Operating Frequency Propagation Delay Compatible Inputs Outputs Electrically Erasable Reprogrammable Non-Volatile 100% Tested Time Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE In-System Programmable (ISPTM) Only Increased Manufacturing Yields, Reduced Time-toMarket Improved Product Quality Reprogram Soldered Devices Faster Prototyping OFFERS EASE FAST SYSTEM SPEED PLDs WITH DENSITY FLEXIBILITY FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Combine Glue Logic Structured Designs Enhanced Locking Capability Three Dedicated Clock Input Pins Synchronous Asynchronous Clocks Programmable Output Slew Rate Control Minimize Switching Noise Flexible Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERT- LOGIC COMPILER COMPLETE DEVICE DESIGN SYSTEMS FROM SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality Results Tightly Integrated with Leading Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator ispANALYZER- UNIX Platforms
Input
Logic Array
Output Routing Pool (ORP)
Input
Description
0139Bisp/2064
ispLSI 2064 2064A High Density Programmable Logic Devices. devices contain Registers, Universal pins, four Dedicated Input pins, three Dedicated Clock Input pins, dedicated Global input pins Global Routing Pool (GRP). provides complete interconnectivity between these elements. 2064 2064A feature in-system programmability in-system diagnostic capabilities. ispLSI 2064 2064A offer non-volatile reprogrammability logic, well interconnect, provide truly reconfigurable systems. basic unit logic these devices Generic Logic Block (GLB). GLBs labeled A1.B7 (Figure There total GLBs ispLSI 2064 2064A devices. Each made four macrocells. Each inputs, programmable AND/OR/Exclusive array, four outputs which configured either combinatorial registered. Inputs come from dedicated inputs. outputs brought back into that they connected inputs device.
Copyright 2000 Lattice Semiconductor Corp. brand product names trademarks registered trademarks their respective holders. specifications information herein subject change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; (503) 268-8037; http://www.latticesemi.com
February 2000
2064_06
Input
Output Routing Pool (ORP)
HIGH DENSITY PROGRAMMABLE LOGIC
Global Routing Pool (GRP)
Specifications ispLSI 2064/A
Functional Block Diagram
Figure ispLSI 2064/A Functional Block Diagram
Input
Generic Logic Blocks (GLBs)
Megablock
Output Routing Pool (ORP)
Output Routing Pool (ORP)
TDI/IN TMS/IN
Input
Input
Output Routing Pool (ORP)
TCK/IN TDO/IN
Global Routing Pool (GRP)
BSCAN
Input
devices also have cells, each which directly connected pin. Each cell individually programmed combinatorial input, output bi-directional with 3-state control. signal levels compatible voltages output drivers source sink Each output programmed independently fast slow output slew rate minimize overall output switching noise. Eight GLBs, cells, dedicated inputs ORPs connected together make Megablock (Figure outputs eight GLBs connected universal cells ORPs. Each ispLSI 2064 2064A device contains Megablocks.
inputs, outputs from GLBs inputs from bi-directional cells. these signals made available inputs GLBs. Delays through have been equalized minimize timing skew. Clocks ispLSI 2064 2064A devices selected using dedicated clock pins. Three dedicated clock pins (Y0, asynchronous clock selected basis. asynchronous Product Term clock generated clock.
0139B(1)isp/2064
RESET
Output Routing Pool (ORP)
Specifications ispLSI 2064/A
Absolute Maximum Ratings
Supply Voltage -0.5 +7.0V Input Voltage Applied -2.5 +1.0V Off-State Output Voltage Applied -2.5 +1.0V Storage Temperature 150°C Case Temp. with Power Applied 125°C Max. Junction Temp. (TJ) with Power Applied 150°C
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation device these other conditions above those indicated operational sections this specification implied (while programming, follow programming specifications).
Recommended Operating Condition
SYMBOL PARAMETER Supply Voltage Input Voltage Input High Voltage Commercial Industrial 70°C -40°C 85°C MIN. 4.75 MAX. 5.25 Vcc+1 UNITS
Table 0005/2064
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance Capacitance Clock Capacitance TYPICAL UNITS TEST CONDITIONS 5.0V, 2.0V 5.0V, VI/O 2.0V 5.0V, 2.0V
Table 2-0006/2064
Data Retention Specifications
PARAMETER Data Retention Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM UNITS Years Cycles
Table 2-0008/2064
Specifications ispLSI 2064/A
Switching Test Conditions
Input Pulse Levels Input Rise Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels measured 0.5V from steady-state active level. 3.0V -125 Others 1.5V 1.5V Figure
Table 2-0003/2064
Figure Test Load
Device Output Test Point
Output Load Conditions (see Figure
TEST CONDITION Active High Active Active High -0.5V Active +0.5V 35pF 35pF 35pF
includes Test Fixture Probe Capacitance.
Table 2-0004/2064
Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Voltage Output High Voltage Input Leakage Current Input High Leakage Current ispEN Input Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= (Max.) 3.5V VOUT 0.5V 0.0V, 3.0V fCLOCK Commercial Industrial CONDITION MIN. TYP.
MAX. UNITS -150 -150 -200
IIL-isp IIL-PU IOS1 ICC2,
Table 2-0007/2064
output time maximum duration second. VOUT 0.5V selected avoid test problems tester ground degradation. Characterized 100% tested. Measured using four 16-bit counters. Typical values 25°C. Maximum varies widely with specific device configuration operating frequency. Refer Power Consumption section this data sheet Thermal Management section Lattice Semiconductor Data Book CD-ROM estimate maximum
Specifications ispLSI 2064/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
DESCRIPTION1 Data Propagation Delay, Bypass, Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle Reg. Setup Time before Clock, Bypass Reg. Clock Output Delay, Bypass Reg. Hold Time after Clock, Bypass Reg. Setup Time before Clock
-125 10.0 10.0 12.0 12.0
-100 10.0 13.0 13.5 15.0 15.0
15.0 18.5 17.0 18.0 18.0 12.0 12.0
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 tsu2 tco2 trw1 tptoeen tptoedis tgoeen tgoedis
77.0
81.0 57.0 11.0 10.0
Clock Frequency with External Feedback tsu2 tco1)
Reg. Clock Output Delay Reg. Hold Time after Clock Ext. Reset Output Delay Ext. Reset Pulse Duration Product Term Enable Product Term Disable Global Enable Global Disable External Synchronous Clock Pulse Duration, High External Synchronous Clock Pulse Duration,
Unless noted otherwise, parameters GRP, PTXOR path, clock. Refer Timing Model this data sheet further details. Standard 16-bit counter using feedback. Reference Switching Test Conditions section.
Table 0030B/2064-130
Specifications ispLSI 2064/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
DESCRIPTION
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs tdin tgrp t4ptbp t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgco tgro tptre tptoe tptck torp
Input Buffer Delay Dedicated Input Delay
Delay
Product Term Bypass Comb. Path Delay Product Term Bypass Reg. Path Delay Product Term/XOR Path Delay Product Term/XOR Path Delay Adjacent Path Delay3
10.2
Register Bypass Delay Register Setup Time before Clock Register Hold Time after Clock Register Clock Output Delay Register Reset Output Delay Product Term Reset Register Delay Product Term Output Enable Cell Delay Product Term Clock Delay
Delay Bypass Delay
torpbp Outputs toen todis tgoe Clocks tgy0 tgy1/2 Global Reset
Output Buffer Delay Output Slew Limited Delay Adder Cell Output Enabled Cell Output Disabled Global Output Enable
10.0
10.0
10.0
Clock Delay, Global Clock Line (Ref. clock) Clock Delay, Global Clock Line
Global Reset
11.4
Internal Timing Parameters tested reference only. Refer Timing Model this data sheet further details. adjacent path only used hard macros.
Table 0036C/2064-130
Specifications ispLSI 2064/A
ispLSI 2064/A Timing Model
Cell Feedback Ded. Comb Bypass Bypass Delays #25, Reset #29, Bypass Delay Bypass Delay #38, (Output) Cell
Delay
(Input)
Control #33, Y0,1,2 #43,
#40,
0491/2064
Derivations tsu, from Product Term Clock
Logic Clock (min) (tio tgrp t20ptxor) (tgsu) (tio tgrp tptck(min)) (#20 #26) (#29) (#20 #35) (0.2 6.0) (0.8) (0.2 3.3) Clock (max) Logic (tio tgrp tptck(max)) (tgh) (tio tgrp t20ptxor) (#20 #35) (#30) (#20 #26) (0.2 5.6) (3.0) (0.2 6.0) Clock (max) Output (tio tgrp tptck(max)) (tgco) (torp tob) (#20 #35) (#31) (#36 #38) (0.2 5.6) (0.2) (0.8 1.2)
Table 0042A-2064
Note: Calculations based upon timing specifications ispLSI 2064/A-125L.
Specifications ispLSI 2064/A
Power Consumption
Power consumption ispLSI 2064 2064A devices depends primary factors: speed which device operating number Product Terms Figure Typical Device Power Consumption fmax
used. Figure shows relationship between power operating speed.
ispLSI 2064/A
(mA)
fmax (MHz)
Notes: Configuration Four 16-bit Counters Typical Current
estimated ispLSI 2064/A using following equation: ICC(mA) 0.33) nets freq 0.007) Where: Number Product Terms used design nets Number Signals used device freq Highest Clock Frequency device MHz) estimate based typical conditions (VCC 5.0V, room temperature) assumption loads average exists. These values estimates only. Since value sensitive operating conditions program device, actual should verified.
0127A/2064A
Specifications ispLSI 2064/A
Description
NAME
RESET ispEN
PLCC NUMBERS
DESCRIPTION
Input/Output Pins These general purpose pins used logic array.
Global Output Enable input pins. Dedicated Clock input. This clock input connected clock inputs GLBs device. Active Reset which resets registers device. Input Dedicated in-system programming enable pin. This brought enable programming mode. When low, MODE, SDI, SCLK controls become active. Input This performs functions. When ispEN logic low, functions input load programming data into device. SDI/IN also used control pins state machine. When ispEN high, functions dedicated input. Input This performs functions. When ispEN logic low, functions control operation state machine. When ispEN high, functions dedicated input pin. Output/Input This performs functions. When ispEN logic low, functions output read serial shift register data. When ispEN high, functions dedicated input pin. Input This performs functions. When ispEN logic low, functions clock Serial Shift Register. When ispEN high, functions dedicated input pin.
SDI/
MODE/
SDO/IN
SCLK/IN
Ground (GND) Connect
Table 2-0002A-08isp/2064
pins connected active signals, GND. Pins have dual function capability.
Specifications ispLSI 2064/A
Description
NAME
RESET ispEN
TQFP NUMBERS
DESCRIPTION
Input/Output Pins These general purpose pins used logic array.
Global Output Enable input pins. Dedicated Clock input. This clock input connected clock inputs GLBs device. Active Reset which resets registers device. Input Dedicated in-system programming enable input pin. This brought enable programming mode. MODE, SDI, SCLK controls become active. Input This performs functions. When ispEN logic low, functions input load programming data into device. SDI/IN also used control pins state machine. When ispEN high, functions dedicated input pin. Input This performs functions. When ispEN logic low, functions control operation state machine. When ispEN high, functions dedicated input pin. Output/Input This performs functions. When ispEN logic low, functions output read serial shift register data. When ispEN high, functions dedicated input pin. Input This performs functions. When ispEN logic low, functions clock Serial Shift Register. When ispEN high, functions dedicated input pin.
SDI/IN
MODE/IN
SDO/IN
SCLK/IN
Ground (GND) Connect.
pins connected active signals, GND. Pins have dual function capability.
Table 2-0002-2064b.eps
Specifications ispLSI 2064/A
Configuration
ispLSI 2064/A 84-Pin PLCC Pinout Diagram
2MODE/IN 2SDO/IN
SCLK/IN
ispEN RESET
2SDI/IN
ispLSI 2064/A
View
0123A/2064
pins connected active signals, GND. Pins have dual function capability.
Specifications ispLSI 2064/A
Configuration
ispLSI 2064/A 100-Pin TQFP Pinout Diagram
ispEN RESET 2SDI/IN
ispLSI 2064/A
View
SCLK/IN
2MODE/IN 2SDO/IN
0766A-2064-isp
pins connected active signals, GND. Pins have dual function capability.
Specifications ispLSI 2064/A
Part Number Description ispLSI XXXXX
Device Family 2064 2064A Device Number Speed fmax fmax fmax
Grade Blank Commercial Industrial Package PLCC TQFP Power
0212/2064/A
ispLSI 2064/A Ordering Information
COMMERCIAL
FAMILY fmax (MHz) ispLSI (ns) ORDERING NUMBER ispLSI 2064A-125LJ84 ispLSI 2064A-125LT100 ispLSI 2064A-100LJ84 ispLSI 2064A-100LT100 ispLSI 2064A-80LJ84 ispLSI 2064A-80LT100 ispLSI 2064-125LJ ispLSI 2064-125LT ispLSI 2064-100LJ ispLSI 2064-100LT ispLSI 2064-80LJ ispLSI 2064-80LT PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP
Table 2-0041A/2064A
INDUSTRIAL
FAMILY fmax (MHz) ispLSI (ns) ORDERING NUMBER ispLSI 2064A-80LJ84I ispLSI 2064A-80LT100I ispLSI 2064-80LJI ispLSI 2064-80LTI PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP
Table 2-0041B/2064A
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