IND: -14/18/24 MACH215-12/15/20 High-Density CMOS Programmab

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IND: -14/18/24 MACH215-12/15/20 High-Density CMOS Programmab

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COM'L: -12/15/20
IND: -14/18/24
MACH215-12/15/20
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins Output Macrocells Input Macrocells Product terms for: Individual flip-flop clock Individual asynchronous reset, preset Individual output enable Commercial 14.5 Industrial fCNT
Lattice/Vantis
Inputs with pull-up resistors Outputs Flip-flops asynchronous synchronous applications "PAL22RA8" blocks with buried macrocells Pin-compatible with MACH110, MACH111, MACH210, MACH211
GENERAL DESCRIPTION
MACH215 member high-performance CMOS MACH device family. This device approximately three times capability popular PAL20RA10 without loss speed. This device designed asynchronous well synchronous applications. MACH215 consists four blocks interconnected programmable switch matrix. four blocks essentially "PAL22RA8" structures complete with product-term arrays programmable macrocells, individual register control product terms, input registers. switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. MACH215 kinds macrocell: output input. MACH215 output macrocell provides registered, latched, combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type T-type help reduce number product terms. register type decision made designer software. Each macrocell dedicated clock, asynchronous reset, asynchronous preset control. polarity clock signal programmable. output macrocells connected cell. MACH215 dedicated input macrocells which provide input registers latches synchronizing input signals reducing setup time requirements.
Publication# 16751
Rev.
Amendment/0
Issue Date: 1995
BLOCK DIAGRAM
I/O0-I/O7 I/O8-I/O15 I0-I1, I3-I4
Cells
Cells Output Macrocells
Output Macrocells
Input Macrocells
Input Macrocells
44x64 Logic Array Logic Allocator
44x64 Logic Array Logic Allocator
Switch Matrix
44x64 Logic Array Logic Allocator
44x64 Logic Array Logic Allocator
Output Macrocells
Input Macrocells
Output Macrocells
Input Macrocells
Cells
Cells
I/O24-I/O31
I/O16-I/O23
CLK0/I2 CLK1/I5
16751E-1
MACH215-12/15/20
CONNECTION DIAGRAM View PLCC
I/O31 I/O30 I/O2 I/O1 I/O29 I/O28 I/O14 I/O15 I/O18 I/O19 I/O12 I/O13 I/O16 I/O17 I/O20 I/O0 I/O4 I/O5 I/O6 I/O7 CLK0/I2 I/O8 I/O9 I/O10 I/O11 I/O3
I/O27 I/O26 I/O25 I/O24 CLK1/I5 I/O23 I/O22 I/O21
16751E-2
Note: Pin-compatible with MACH110, MACH111, MACH210, MACH211.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output
Supply Voltage
MACH215-12/15/20
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed DEVICE NUMBER Asynchronous Output Macrocells, Pins SPEED
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Commercial (0°C +70°C) PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044)
Valid Combinations MACH215-12 MACH215-15 MACH215-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH215-12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
Programmable logic products industrial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed DEVICE NUMBER Asynchronous Output Macrocells, Pins SPEED 14.5
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Industrial (-40°C +85°C) PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044)
Valid Combinations MACH215-14 MACH215-18 MACH215-24
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH215-14/18/24 (Ind)
FUNCTIONAL DESCRIPTION
MACH215 consists four asynchronous blocks connected switch matrix. There pins dedicated input pins feeding switch matrix. These signals distributed four blocks efficient design implementation. There also additional global clock pins that used dedicated inputs. This device provides kinds macrocell: output macrocells input macrocells. This adds greater logic density without affecting number pins.
Table Logic Allocation
Output Macrocell Available Clusters
Blocks
Each block MACH215 (Figure contains 64-product-term array, logic allocator, output macrocells, input macrocells, cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL22RA8" with input macrocells. flip-flops within device operate independently.
Macrocell
There types macrocell MACH215: output macrocells input macrocells. output macrocell takes logic device provides pins and/or provides feedback additional logic generation. input macrocell allows pins configured registered latched inputs. output macrocell (Figure generate registered combinatorial outputs. addition, transparent-low latched configuration provided. used, register configured T-type D-type flip-flop. Register latch functionality defined Table Programmable polarity T-type flip-flop both give software minimize number product terms needed. These choices made automatically software when fits design into device. Table Register/Latch Operation
Configuration D-Register CLK/LE*
Switch Matrix
MACH215 switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device.
Product-term Array
MACH215 product-term array consists product terms logic product terms generating macrocell control signals.
Logic Allocator
logic allocator MACH215 (Figure takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
T-Register
Latch
*Polarity CLK/LE programmed.
MACH215-12/15/20
output macrocell sends output back switch matrix, internal feedback, cell. feedback always available regardless configuration cell. This allows buried combinatorial registered functions, freeing pins inputs needed outputs. basic output macrocell configurations shown Figure clock/latch-enable each individual output macrocell driven four signals. signals provided global clock CLK0/LE0; either polarity chosen. other signals come from product term provided each output macrocell. Either polarity logic generated product term chosen. global clock also available input, although care must taken when signal acts both clock input same device. Each individual output macrocell also product term asynchronous reset product term asynchronous preset. This means that register latch reset preset without affecting other register latch device. functionality flip-flops with respect initialization illustrated Table Table Asynchronous Reset/Preset Operation
CLK/LE Table
input macrocell (Figure consists flip-flop that used provide registered latched inputs. flip-flop clocked either polarity global clock/latch-enable pins. Reset preset provided these flip-flops. combinatorial inputs desired, this macrocell used, feedback from used directly. Both feedback output input register latch always available switch matrix. Possible input macrocell configurations shown Figure
Cell
cell (Figure provides three-state output buffer. three-state control provided individual product term each cell. Depending logic programmed onto this product term, configured output, input, bidirectional pin. feedback from always available switch matrix, regardless state output buffer output macrocell.
MACH215-12/15/20
Output Macro Cell
Cell
Input Macro Cell
Output Macro Cell
Cell
Input Macro Cell
Cell
Output Macro Cell
Logic Allocator
Input Macro Cell
Cell
Switch Matrix
Output Macro Cell
Input Macro Cell
Output Macro Cell
Cell
Input Macro Cell
Output Macro Cell
Cell
Input Macro Cell
Cell Output Macro Cell
Input Macro Cell
Cell Output Macro Cell
Input Macro Cell
CLK0 CLK1
16751E-3
Figure MACH215 Block MACH215-12/15/20
From
Macrocell
Product Term Cluster
From
Logic Allocator
16751E-4
Figure Product Term Clusters Logic Allocator
Individual Asynchronous Preset Products from Logic Allocator CLK0 Individual Clock Individual Asynchronous Reset Switch Matrix D/T/L
Cell
16751E-5
Figure Output Macrocell
MACH215-12/15/20
From Logic Allocator
Cell
From Logic Allocator
Cell
Switch Matrix
Switch Matrix
Combinatorial, Active High
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset Switch Matrix Cell
Combinatorial, Active
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset Switch Matrix Cell
D-type Register, Active High
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset Switch Matrix Cell
D-type Register, Active
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset Switch Matrix Cell
T-type Register, Active High
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset Switch Matrix Cell
T-type Register, Active
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset Switch Matrix Cell
Latch, Active High
Latch, Active
16751E-6
Figure Output Macrocell Configurations
MACH215-12/15/20
From CLK0 CLK1
Switch Matrix
16751E-7
Figure Input Macrocell
From Cell
From Cell
CLK0 CLK1
CLK0 CLK1
Switch Matrix
Switch Matrix
Input Register
Input Latch
16751E-8
Figure Input Macrocell Configurations
Individual Output Enable Product Term
From Output Macrocell
Switch Matrix
Input Macrocell
16751E-9
Figure Cell MACH215-12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note -100 -100 -160 Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset.
MACH215-12/15/20 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description tCOA tWLA tWHA Maximum Frequency Using Product Term Clock (Note External Feedback 1/(tSA tCOA) Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output (Note Product Term, Clock Width HIGH D-type T-type D-type Internal Feedback (fCNTA) Feedback 1/(tWLA tWHA) D-type T-type T-type D-type T-type 52.6 58.8 55.6 62.5 Global Clock Width Maximum Frequency Using Global Clock (Note HIGH D-type External Feedback 1/(tSS tCOS) T-type D-type Internal Feedback (fCNTS) Feedback tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS 1/(tWLS tWHS) T-type 66.7 62.5 83.3 76.9 83.3 41.7 45.5 43.5 55.6 47.6 66.6 62.5 83.3 33.3 32.2 35.7 34.5 41.7 38.5 47.6 62.5 Unit
fMAXA
tCOS tWLS tWHS
Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output (Note
fMAXS
Setup Time from Input, I/O, Feedback Product Term Gate Latch Data Hold Time Using Product Term Clock Product Term Gate Output (Note Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output (Note Global Gate Width (for transparent) HIGH (for HIGH transparent)
MACH215-12/15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tPDL tSIR tHIR tICO tICS Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Global Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Input Register Clock Width HIGH 1/(tWICL tWICH) 83.3 83.3 62.5 Unit
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tARW tARR tAPW tAPR
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. Switching Test Circuit test conditions. Switching waveforms illustrate true clocks only. Switching waveforms used illustrate both synchronous asynchronous clock timing. example, parameter synchronous clocks parameter asynchronous clocks. Parameters measured with outputs switching.
MACH215-12/15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 (Note Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note -100 -100 -160 Unit
Notes: Total block should exceed These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset.
MACH215-14/18/24 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description tCOA tWLA tWHA Maximum Frequency Using Product Term Clock (Note External Feedback 1/(tSA tCOA Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock Output (Note Product Term, Clock Width HIGH D-type T-type D-type Internal Feedback (fCNTA Feedback 1/(tWLA tWHA D-type T-type T-type Global Clock Width Maximum Frequency Using Global Clock (Note External Feedback 1/(tSS tCOS HIGH D-type T-type D-type Internal Feedback (fCNTS Feedback 1/(tWLS tWHS T-type 66.5 61.5 66.5 19.5 13.5 66.5 14.5 14.5 D-type T-type 34.5 44.5 13.5 30.5 26.5 14.5 26.5 25.5 28.5 27.5 14.5 26.5 Unit
fMAXS
tCOS tWLS tWHS
Setup Time from Input, I/O, Feedback Global Clock Register Data Hold Time Using Global Clock Global Clock Output (Note
fMAXS
tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS
Setup Time from Input, I/O, Feedback Product Term Gate Latch Data Hold Time Using Product Term Clock Product Term Gate Output (Note Product Term Gate Width (for transparent) HIGH (for HIGH transparent) Setup Time from Input, I/O, Feedback Global Gate Latch Data Hold Time Using Global Gate Gate Output (Note Global Gate Width (for transparent) HIGH (for HIGH transparent)
MACH215-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tPDL tSIR tHIR tICO tICS Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Product Term Output Latch Gate Input Latch Gate Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, Feedback Through Transparent Input Latch Global Output Latch Gate Input Latch Gate Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note 14.5 14.5 14.5 14.5 19.5 19.5 19.5 HIGH 1/(tWICL tWICH 14.5 66.5 20.5 19.5 66.5 26.5 25.5 32.5 20.5 26.5 Unit
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tARW tARR tAPW tAPR
14.5 19.5
25.5
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. Switching Test Circuit test conditions. Switching waveforms illustrate true clocks only. Switching waveforms used illustrate both synchronous asynchronous clock timing. example, parameter synchronous clocks parameter asynchronous clocks. Parameters measured with outputs switching.
MACH215-14/18/24 (Ind)
TYPICAL CURRENT VOLTAGE (I-V) CHARACTERISTICS
25°C
(mA) -1.0 -0.8 -0.6 -0.4 -0.2
Output,
(mA) -100 -125 -150
16751E-10
Output, HIGH (mA)
-100
16751E-11
16751E-12
Input MACH215-12/15/20
TYPICAL CHARACTERISTICS
25°C
MACH215
(mA)
16751E-13
Frequency (MHz)
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH215-12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PLCC Units °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH215-12/15/20
SWITCHING WAVEFORMS
Input, I/O, Feedback
Combinatorial Output
16751E-14
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
16751E-15
16751E-16
Latched
Registered Output
Latched Output (MACH
Clock
16751E-17
Gate tGWS
16751E-18
Clock Width
Gate Width (MACH
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
16751E-20
16751E-19
Registered Input (MACH
Input Register Output Register Setup (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH215-12/15/20
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
16751E-21
Latched Input (MACH
tPDLL Latched Latched Input Latch Gate tIGOL
tIGS Output Latch Gate
tSLL
16751E-22
Latched Input Output (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH215-12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL
16751E-23
Input Latch Gate tWIGL
16751E-24
Input Register Clock Width (MACH
Input Latch Gate Width (MACH
tARW Input, I/O, Feedback Registered Output tARR Clock
16751E-25
tAPW Input, I/O, Feedback Registered Output tAPR Clock
16751E-26
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
16751E-27
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH215-12/15/20
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
16751E-28
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided accurate measurement.
MACH215-12/15/20
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL tWICH). clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
tSIR
tHIR fMAXIR 1/(tSIR tHIR) 1/(tWICL tWICH)
16751E-29
fMAX Feedback; 1/(tS 1/(tWH tWL)
MACH215-12/15/20
ENDURANCE CHARACTERISTICS
MACH families manufactured using advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH215-12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection
Input
Preload Circuitry
Feedback Input
16751E-30
MACH215-12/15/20
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
16751E-31
Power-Up Reset Waveform
MACH215-12/15/20
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
16751E-33
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
16751E-32
MACH215-12/15/20
PHYSICAL DIMENSIONS* 44-Pin Plastic Leaded Chip Carrier (measured inches)
.685 .695
.650 .656
.042 .056
.062 .083
I.D. .685 .695 .650 .656 .500 .590 .630
.013 .021
.026 .032
.050
.009 .015
.090 .120 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DA78 6-28-94
*For reference only. ANSI standard Basic Space Centering.
MACH215-12/15/20

IND: -14/18/24 MACH215-12/15/20 High-Density CMOS Programmab

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