IND: -14/18/24 MACH220-10/12/15/20 High-Density CMOS Program
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COM'L: -10/12/15/20
IND: -14/18/24
MACH220-10/12/15/20
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins Macrocells fCNT Inputs with pull-up resistors Outputs
Lattice/Vantis
Flip-flops; clock choices "PAL26V12" blocks with buried macrocells Pin-compatible with MACH120 MACH221
GENERAL DESCRIPTION
MACH220 member high-performance CMOS MACH device family. This device approximately nine times logic macrocell capability popular PAL22V10 without loss speed. MACH220 consists eight blocks interconnected programmable switch matrix. eight blocks essentially "PAL26V12" structures complete with product-term arrays, programmable macrocells, including buried macrocells. switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. MACH220 kinds macrocell: output buried. output macrocell provides registered, latched, combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type T-type help reduce number product terms. register type decision made designer software. output macrocells connected cell. buried macrocell desired, internal feedback path from macrocell used, which frees input. MACH220 dedicated buried macrocells which, addition capabilities output macrocell, also provide input registers synchronizing signals reducing setup time requirements.
BLOCK DIAGRAM
would like view Block Diagram full size, please click box.
Publication# 14130 Rev. Issue Date: 1995
Amendment
I/O0 I/O5 I/O6 I/O11 I/O12 I/O17 I/O18- I/O23
Cells Macrocells Macrocells Cells Macrocells
Macrocells Cells Macrocells
Macrocells Cells Macrocells
Macrocells
Logic Array Logic Allocator
Logic Array Logic Allocator Switch Matrix
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Logic Array Logic Allocator
Macrocells Cells
Macrocells
Macrocells Cells
Macrocells
Macrocells Cells
Macrocells
Macrocells Cells
Macrocells
I/O42 I/O47
I/O36 I/O41
I/O30 I/O35
I/O24 I/O29
CLK0/I0, CLK1/I1 CLK2/I4 CLK3/I5
14130I-1
CONNECTION DIAGRAMS View PLCC
I/O47 I/O46
I/O5 I/O4 I/O3
I/O7 I/O8 I/O9 I/O10 I/O11 CLK0/I0 CLK1/I1 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17
I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 CLK3/I5 CLK2/I4 I/O35 I/O34 I/O33 I/O32 I/O31
I/O18 I/O26 I/O27 I/O28 I/O29 I/O30 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25
I/O45
I/O2 I/O1
I/O44 I/O43
I/O0
I/O42
14130D-001A 14130I-2
Note: Pin-compatible with MACH120 MACH221.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output
Supply Voltage
I/O6
MACH220-10/12/15/20
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Commercial (0°C +70°C)
DEVICE NUMBER Macrocells, Pins SPEED
PACKAGE TYPE 68-Pin Plastic Leaded Chip Carrier 068)
Valid Combinations MACH220-10 MACH220-12 MACH220-15 MACH220-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH220-10/12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
Programmable logic products industrial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Industrial (-40°C +85°C)
DEVICE NUMBER Macrocells, Pins SPEED 14.5
PACKAGE TYPE 68-Pin Plastic Leaded Chip Carrier 068)
Valid Combinations MACH220-14 MACH220-18 MACH220-24
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH220-14/18/24 (Ind)
FUNCTIONAL DESCRIPTION
MACH220 consists eight blocks connected switch matrix. There pins dedicated input pins feeding switch matrix. These signals distributed four blocks efficient design implementation. There clock pins that also used dedicated inputs. inputs pins have built-in pull-up resistors. While always good design practice unused pins high low, pull-up resistors provide design security stability event that unused pins left disconnected.
Table Logic Allocation Macrocell Output Buried Available Clusters C10, C10, C10,
Blocks
Each block MACH220 (Figure contains 48-product-term logic array, logic allocator, output macrocells, buried macrocells, cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL26V12" with buried macrocells. addition logic product terms, output enable product terms, asynchronous reset product term, asynchronous preset product term provided. output enable product terms chosen within each cell block. flip-flops within block initialized together.
Macrocell
MACH220 types macrocell: output buried. output macrocells configured either registered, latched, combinatorial, with programmable polarity. macrocell provides internal feedback whether configured with without flipflop. registers configured D-type T-type, allowing product-term optimization. flip-flops individually select four clock/gate pins, which also available data inputs. registers clocked LOW-to-HIGH transition clock signal. latch holds data when gate input HIGH, transparent when gate input LOW. flip-flops also asynchronously initialized with common asynchronous reset preset product terms. buried macrocells same output macrocells they used generating logic. that case, only thing that distinguishes them from output macrocells fact that there cell connection, signal only used internally. buried macrocell also configured input register latch.
Switch Matrix
MACH220 switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device.
Product-Term Array
MACH220 product-term array consists product terms logic use, special-purpose product terms. special-purpose product terms provide programmable output enable, provides asynchronous reset, provides asynchronous preset.
Cell
cell MACH220 consists three-state output buffer. three-state buffer configured three ways: always enabled, always disabled, controlled product term. product term control chosen, product terms used provide control. product terms that available common cells block. These choices make possible macrocell output, input, bidirectional pin, three-state output driving bus.
Logic Allocator
logic allocator MACH220 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
MACH220-10/12/15/20
Output Enable Output Enable Asynchronous Reset Asynchronous Preset
Output Macro Cell
Cell
Buried Macro Cell
Logic Allocator
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Switch Matrix
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
14130I-3
Figure MACH220 Block
MACH220-10/12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note -100 -100 -130 Unit
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 12-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset.
MACH220-10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output Clock Width External Feedback fMAX Maximum Frequency (Note Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup D-type T-type HIGH HIGH D-type T-type D-type T-type D-type T-type Unit
MACH220-10 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tWIGL tPDLL tARW tARR tAPW tAPR Parameter Description Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable Input, I/O, Feedback Output Disable Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit, test conditions.
MACH220-10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature 65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note -100 -100 -130 Unit
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should shorted time duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 12-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset.
MACH220-12/15/20 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) Input, I/O, Feedback Combinatorial Output (Note D-type Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output (Note Clock Width HIGH D-type T-type D-type T-type Feedback tGWL tPDL tSIR tHIR tICO tICS 1/(tWL tWH) 66.7 62.5 83.3 76.9 83.3 D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup Input Register Clock Width HIGH 1/(tWICL tWICH) 83.3 83.3 62.5 T-type
Unit
47.6 66.6 62.5 83.3
38.5 47.6 62.5
Internal Feedback (fCNT)
Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output (Note Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup
MACH220-12/15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tWIGL tPDLL tARW tARR tAPW tAPR Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit test conditions. Parameters measured with outputs switching.
MACH220-12/15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature 65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note -100 -100 -130 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 12-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset.
MACH220-14/18/24 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C, Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note D-type Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output (Note Clock Width HIGH D-type External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) T-type D-type T-type Feedback tGWL tPDL tSIR tHIR tICO tICS Latch Data Hold Time Gate Output (Note Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS tWIGL tPDLL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches 19.5 HIGH 1/(tWICL tWICH 14.5 66.5 20.5 14.5 19.5 19.5 66.5 26.5 25.5 25.5 32.5 1/(tWL tWH) 61.5 66.5 20.5 T-type 66.5 13.5 26.5 14.5 13.5 30.5 34.5 14.5 14.5 Unit
Internal Feedback (fCNT)
Setup Time from Input, I/O, Feedback Gate
MACH220-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note (continued)
Parameter Symbol Parameter Description tARW tARR tAPW tAPR Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note 14.5 14.5 14.5 14.5 19.5 19.5 Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. Switching Test Circuit test conditions. Parameters measured with outputs switching.
MACH220-14/18/24 (Ind)
TYPICAL CURRENT VOLTAGE (I-V) CHARACTERISTICS
25°C
(mA) -1.0 -0.8 -0.6 -0.4 -0.2
14130I-4
Output,
(mA) -100 -125 -150
14130I-5
Output, HIGH (mA)
-100
14130I-6
Input MACH220-10/12/15/20
TYPICAL CHARACTERISTICS
25°C
MACH220
(mA)
Frequency (MHz)
14130I-7
selected "typical" pattern 12-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH220-10/12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PLCC Units °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH220-10/12/15/20
SWITCHING WAVEFORMS
Input, I/O, Feedback
Combinatorial Output
14130I-8
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
14130I-9
14130I-10
Latched
Registered Output
Latched Output (MACH
Clock
14130I-11
Gate tGWS
14130I-12
Clock Width
Gate Width (MACH
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
14130I-14
14130I-13
Registered Input (MACH
Input Register Output Register Setup (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH220-10/12/15/20
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
14130I-15
Latched Input (MACH
tPDLL Latched Latched Input Latch Gate tIGOL
tIGS Output Latch Gate
tSLL
14130I-16
Latched Input Output (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH220-10/12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL
14130I-17
Input Latch Gate tWIGL
14130I-18
Input Register Clock Width (MACH
Input Latch Gate Width (MACH
tARW Input, I/O, Feedback Registered Output tARR Clock
14130I-19
tAPW Input, I/O, Feedback Registered Output tAPR Clock
14130I-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
14130I-21
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH220-10/12/15/20
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
14130I-22
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided accurate measurement.
MACH220-10/12/15/20
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL tWICH). clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
tSIR
tHIR fMAXIR 1/(tSIR tHIR) 1/(tWICL tWICH)
14130I-23
fMAX Feedback; 1/(tS 1/(tWH tWL)
MACH220-10/12/15/20
ENDURANCE CHARACTERISTICS
MACH families manufactured using advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH220-10/12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection
Input
Preload Circuitry
Feedback Input
14130I-24
MACH220-10/12/15/20
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
14130I-25
Power-Up Reset Waveform
MACH220-10/12/15/20
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
14130I-27
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
14130I-26
MACH220-10/12/15/20
PHYSICAL DIMENSIONS* 68-Pin Plastic Leaded Chip Carrier (measured inches)
.985 .995
.950 .956
.042 .056
.062 .083
I.D. .985 .995 .950 .956 .800 .890 .930
.013 .021
.026 .032
.050
.007 .013
.090 .130 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DA78 6-28-94
*For reference only. ANSI standard Basic Space Centering.
MACH220-10/12/15/20
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