IND: -14/18/24 MACH110-12/15/20 High-Density CMOS Programmab

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

IND: -14/18/24 MACH110-12/15/20 High-Density CMOS Programmab

Datasheet Thumbnail

Top Searches for this datasheet

COM'L: -12/15/20
IND: -14/18/24
MACH110-12/15/20
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
Pins Macrocells Commercial Industrial fCNT Inputs Outputs
Lattice/Vantis
Flip-flops; clock choices "PAL22V16" Blocks Pin-compatible with MACH111, MACH210, MACH211, MACH215
GENERAL DESCRIPTION
MACH110 member high-performance CMOS MACH family. This device approximately three times logic macrocell capability popular PAL22V10 without loss speed. MACH110 consists blocks interconnected programmable switch matrix. blocks essentially "PAL22V16" structures complete with product-term arrays programmable macrocells. switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. MACH110 macrocell provides either registered combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type T-type help reduce number product terms. register type decision made designer software. macrocells connected cell. buried macrocell desired, internal feedback path from macrocell used, which frees input.
Publication# 14127 Rev. Issue Date: 1995
Amendment
BLOCK DIAGRAM
I/O0 I/O15
Cells
Macrocells
Logic Array Logic Allocator
Switch Matrix
Logic Array Logic Allocator
Macrocells Cells
I/O16 I/O31
CLK1/I5, CLK0/I2
14127I-1
MACH110-12/15/20
CONNECTION DIAGRAM View PLCC
I/O31 I/O30 I/O29 I/O28 I/O14 I/O15 I/O18 I/O19 I/O12 I/O13 I/O16 I/O17 I/O20
I/O0
I/O5 I/O6 I/O7 CLK0/I2 I/O8 I/O9 I/O10 I/O11
I/O2 I/O1
I/O27 I/O26 I/O25 I/O24 CLK1/I5 I/O23 I/O22 I/O21
I/O4
I/O3
14127I-2
Note: Pin-compatible with MACH111, MACH210, MACH211, MACH215.
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output
Supply Voltage
MACH110-12/15/20
ORDERING INFORMATION Commercial Products
Programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing OPERATING CONDITIONS Commercial (0°C +70°C)
DEVICE NUMBER Macrocells, Pins SPEED
PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044)
Valid Combinations MACH110-12 MACH110-15 MACH110-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH110-12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
Programmable logic products Industrial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed DEVICE NUMBER Macrocells, Pins SPEED
OPTIONAL PROCESSING Blank Standard Processing
OPERATING CONDITIONS Industrial (-40°C +85°C) PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044)
Valid Combinations MACH110-14 MACH110-18 MACH110-24
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult your local sales office confirm availability specific valid combinations check newly released combinations.
MACH110-14/18/25 (Ind)
FUNCTIONAL DESCRIPTION
MACH110 consists blocks connected switch matrix. There pins dedicated input pins feeding switch matrix. These signals distributed blocks efficient design implementation. There clock pins that also used dedicated inputs.
Table Logic Allocation
Output Macrocell Available Clusters C10, C10, C11, C11, C12, C12, C13, C13, C14, C14,
Blocks
Each block MACH110 (Figure contains 64-product-term logic array, logic allocator, macrocells cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL22V16". There four additional output enable product terms each block. purposes output enable, cells divided into banks macrocells. Each bank allocated output enable product terms. asynchronous reset product term asynchronous preset product term provided flip-flop initialization. flip-flops within block initialized together.
Macrocell
MACH110 macrocells configured either registered combinatorial, with programmable polarity. macrocell provides internal feedback whether configured registered combinatorial. flip-flops configured D-type T-type, allowing product-term optimization. flip-flops individually select clock pins, which also available data inputs. registers clocked LOW-to-HIGH transition clock signal. flip-flops also asynchronously initialized with common asynchronous reset preset product terms.
Switch Matrix
MACH110 switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device.
Product-Term Array
MACH110 product-term array consists product terms logic use, special-purpose product terms. Four special-purpose product terms provide programmable output enable, provides asynchronous reset, provides synchronous preset. output enable product terms used first eight cells; other control last eight macrocells.
Cell
cell MACH110 consists three-state output buffer. three-state buffer configured three ways: always enabled, always disabled, controlled product term. product term control chosen, product terms used provide control. product terms that available common eight cells. Within each block, product terms available selection first eight three-state outputs; other product terms available selection last eight three-state outputs. These choices make possible macrocell output, input, bidirectional pin, three-state output driving bus.
Logic Allocator
logic allocator MACH110 takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
MACH110-12/15/20
Output Enable Output Enable Asynchronous Reset Asynchronous Preset
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Logic Allocator
Cell
Output Macro Cell
Output Macro Cell
Cell
Cell
Output Macro Cell
Switch Matrix
Cell
Output Macro Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Output Macro Cell
Cell
Cell
Output Macro Cell
Cell Output Macro Cell Cell Output Macro Cell
Output Enable Output Enable
14127I-3
Figure MACH110 Block
MACH110-12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature With Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Note TA=25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter program. This pattern programmed each block capable being loaded, enabled, reset.
MACH110-12/15/20 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Hold Time Clock Output (Note Clock Width HIGH D-type External Feedback 1/(tS tCO) fMAX Maximum Frequency (Note Internal Feedback (fCNT) Feedback tARW tARR tAPW tAPR 1/(tWL tWH) T-type D-type T-type 66.7 62.5 76.9 71.4 83.3 D-type T-type 47.6 66.6 55.5 83.3 38.5 47.6 43.5 62.5 Unit
Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit, test conditions. Parameters measured with outputs switching.
MACH110-12/15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature With Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Typical) Test Conditions -3.2 Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT= 5.25 (Note VOUT (Note VOUT (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. Measured with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled, reset.
MACH110-14/18/20 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Hold Time Clock Output (Note Clock Width HIGH D-type External Feedback 1/(tS tCO) fMAX Maximum Frequency (Note Internal Feedback (fCNT Feedback tARW tARR tAPW tAPR 1/(tWL tWH) T-type D-type T-type 53.5 61.5 66.5 19.5 14.5 19.5 14.5 14.5 14.5 D-type T-type 66.5 14.5 13.5 34.5 14.5 Unit
Asynchronous Reset Registered Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit, test conditions. Parameters measured with outputs switching.
MACH110-14/18/20 (Ind)
TYPICAL CURRENT VOLTAGE (I-V) CHARACTERISTICS
25°C
(mA) -1.0 -0.8 -0.6 -0.4 -0.2
Output,
(mA) -100 -125 -150
14127I-4
14127I-5
Output, HIGH (mA)
-100
14127I-6
Input MACH110-12/15/20
TYPICAL CHARACTERISTICS 25°C
MACH110
(mA)
14127I-7
Frequency (MHz)
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH110-12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
MACH110-12/15/20
SWITCHING WAVEFORMS
Input, I/O, Feedback
Combinatorial Output
14127I-8
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL
14127I-9
14127I-10
Latched
Registered Output
Latched Output (MACH
Clock
14127I-11
Gate tGWS
14127I-12
Clock Width
Gate Width (MACH
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
14127I-14
14127I-13
Registered Input (MACH
Input Register Output Register Setup (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH110-12/15/20
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
14127I-15
Latched Input (MACH
tPDLL Latched Latched Input Latch Gate tIGOL
tIGS Output Latch Gate
tSLL
14127I-16
Latched Input Output (MACH
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH110-12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL
14127I-17
Input Latch Gate tWIGL
14127I-18
Input Register Clock Width (MACH
Input Latch Gate Width (MACH
tARW Input, I/O, Feedback Registered Output tARR Clock
14127I-19
tAPW Input, I/O, Feedback Registered Output tAPR Clock
14127I-20
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs 0.5V 0.5V
14127I-21
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH110-12/15/20
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
14127I-22
Commercial Specification tPD, Closed Open Closed Open Closed
Measured Output Value
*Switching several outputs simultaneously should avoided accurate measurement.
MACH110-12/15/20
fMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT." third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL tWICH). clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
tSIR
tHIR fMAXIR 1/(tSIR tHIR) 1/(tWICL tWICH)
14127I-23
fMAX Feedback; 1/(tS 1/(tWH tWL)
MACH110-12/15/20
ENDURANCE CHARACTERISTICS
MACH families manufactured using advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Units Years Years Cycles Test Conditions Storage Temperature Operating Temperature Normal Programming Conditions
MACH110-12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection
Input
Preload Circuitry
Feedback Input
14127I-24
MACH110-12/15/20
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following powerup, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset
Parameter Symbol
wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Clock Width
Switching Characteristics
Unit
Power
Registered Output
Clock
14127I-25
Power-Up Reset Waveform
MACH110-12/15/20
USING PRELOAD OBSERVABILITY
order testable, circuit must both controllable observable. achieve this, MACH devices incorporate register preload observability. preload mode, each flip-flop MACH device loaded from pins, order perform functional testing complex state machines. Register preload makes possible series tests from known starting state, load illegal states test proper recovery. This ability control MACH device's internal state shorten test sequences, since easier reach state interest. observability function makes possible internal state buried registers during test overriding each register's output enable activating output buffer. values stored output buried registers then observed pins. Without this feature, thorough functional test would impossible designs with buried registers. While implementation testability features fairly straightforward, care must taken certain instances insure valid testing. case involves asynchronous reset preset. MACH registers drive asynchronous reset preset lines preloaded such that reset preset asserted, reset preset remove preloaded data. This illustrated Figure Care should taken when planning functional tests, that states that will cause unexpected resets presets preloaded. Another case aware arises testing combinatorial logic. When output configured combinatorial, observability feature forces output into registered mode. When this happens, product terms forced zero, which eliminates combinatorial data. straight combinatorial output, correct value will restored after preload observe function, there will problem. function implements combinatorial latch, however, relies feedback hold correct value, shown Figure this value change during preload observe operation, cannot count data being correct after operation. insure valid testing these cases, outputs that combinatorial latches should tested immediately following preload observe sequence, should first restored known state. MACH devices support both preload observability. Contact individual programming vendors order verify programmer support.
Reset Figure Combinatorial Latch
14127I-27
Preloaded HIGH
Preloaded HIGH
Preload Mode
Figure Preload/Reset Conflict
14127I-26
MACH110-12/15/20
PHYSICAL DIMENSIONS* 44-Pin Plastic Leaded Chip Carrier (measured inches)
.685 .695
.650 .656
.042 .056
.062 .083
I.D. .685 .695 .650 .656 .500 .590 .630
.013 .021
.026 .032
.050
.009 .015
.090 .120 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DA78 6-28-94
*For reference only. ANSI standard Basic Space Centering.
MACH110-12/15/20

IND: -14/18/24 MACH110-12/15/20 High-Density CMOS Programmab

Top Searches for this datasheet

Other recent searches