1/8, 1/9, 1/10 Duty BITMAP DRIVER with SCAN NJU6538 10-common 65-

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1/8, 1/9, 1/10 Duty BITMAP DRIVER with SCAN NJU6538 10-common 65-

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NJU6538
1/8, 1/9, 1/10 Duty BITMAP DRIVER with SCAN
NJU6538 10-common 65-segment bitmap driver display graphics characters. contains bits display data RAM, microprocessor interface circuit, common segment drivers, scan circuit, general output ports. image data from through serial interface stored into bits internal displayed panel through commons segments drivers. NJU6538 displays dots graphics 11-character 1-line dots character dots icons. contains scan circuit transmitting 25-keys maximum MPU. Also provides general purpose output ports with output function maximum drive LEDs others directly. Furthermore, NJU6538 select driving voltage steps voltage instruction adjust display contrast panel.
PACKAGE OUTLINE
NJU6538FG1
NJU6538FC2
FEATURES
Direct Correspondence between Display Data Pixel Display Data 650-bits Drivers 65-seg, 10-com Serial interface (SIO, SCL, Programmable Duty Ratio Duty 7-common 65-segment 1-icon common Duty 7-common 65-segment 2-icon common 1/10Duty 7-common 65-segment 3-icon common Bias Ratio bias 25-key scan Function matrix) Needless anti-reverse current diodes scan general Output Ports with 128-steps output (possible driving) maximum 4-ports Useful Instruction Display ON/OFF, Page Address Set, Column Address Set, Display Data write, Select, Inverse Display ON/OFF, whole display ON/OFF, Reset, Register Set, Duty Select, Power Save mode set, General Output Port phase frequency set, General Output Port data set, General Output Port scan output select Bleeder Resistance On-chip Software Contrast Control steps) Operating Voltage Logic Operating Voltage 5.5V Driving Voltage 10.0V Package Outline QFP100-G1 QFP100-C2 C-MOS Technology (Substrate:
Ver.2003-03-17
NJU6538
CONFIGRATION
S0/Po3 VLCD1 VLCD2 RESb S0/Po3 VLCD1 VLCD2 RESb
NJU6538FG1
NJU6538FC2
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49
COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51
SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29
Ver.2003-03-17
NJU6538
BLOCK DIAGRAM
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10
VLCD1 E.V.R. Common Driver VLCD2 Instruction Decoder Instruction Data Buffer Page Address Decoder Input Buffer Segment Driver
Display Data
Column Address Decoder
Oscillator
Timing Generator
Data Buffer
RESb Power Reset
RESET
Serial
Scan Control
General Output Driver
Po3/S0
Ver.2003-03-17
SEG63 SEG64 SEG65
SEG1 SEG2 SEG3
Reset
NJU6538
TERMINAL DESCRIPTION
Symbol
SEG1 SEG65 COM1 COM7 COM8 COM10
Description
Segment output terminal. Common output terminal. Icon common output terminal. General output port 128-step waveform output control. General output port scanning input terminal Select General output port scanning input terminal instruction. function must selected either General output port 128-step waveform output control. scanning input terminals need anti-reverse current diode scan)
Po3/S0
VLCD1 VLCD2 RESb
scanning input terminals. need anti-reverse current diode scan) scanning input terminals. (with internal pull-down resistor) Power supply terminal.(2.7V 5.5V) driving voltage input terminal. driving voltage stabilization capacitor terminals. Connect capacitor between each terminal Vss.
Ground terminal.
Osclator terminal. Conect external resistor. Reset terminal. (with internal pull-up resistor) case only Power-on Reset should open. Chip enable terminal Serial clock input terminal Serial Data input output terminal
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NJU6538
FUNCTIONAL DESCRIPTION
Description each blocks (1-1) Serial serial controls serial data from external data. (1-2) Instruction data buffer instruction data buffer stores instruction code from external. (1-3) Instruction decoder instruction decoder decodes instruction code controls each blocks. (1-4) Display data Display data stores data display from MPU. (1-5) Segment driver Segment driver generates driving waveform segment terminal display data. (1-6) General output driver General output driver generates output signal level general output terminal output data. (1-7) Common driver Common driver generates driving waveform common terminal. (1-8) Electrical Variable Resistance (E.V.R.) Electrical Variable Resistance adjusts driving voltage from (1-9) scan controller scan controller controls input from external data. (1-10) data buffer data buffer stores data until next data stored.
(1-11) Oscillator Oscillator external connect resistor, which generates master clock. (1-12) Reset circuit Reset circuit type detectable voltage. resets internal circuit when power turns drop voltage.
Fig.1 Display data (DDRAM)
Page address Data Display Pattern Common Drivers COM1 COM2 COM3
D0="0"
PAGE
COM4 COM5 COM6 COM7 COM8
D0="1"
PAGE
COM9 COM10
Column Address
D0="0" D0="1"
Segment Drivers
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NJU6538
Instruction 3-wired Serial clock synchronized clock. signal select data instruction signal. data input MSB(D7) first serially. Table Instruction Code Code
Don't Care) Description
display D0=0 OFF, D0=1 page DDRAM page address registor. D0=0 PAGE D0=1 PAGE Higher order bits column address registor. Lower order bits column address registor. Write data into Display data RAM(DDRAM) DDRAM driver D0=0 Nomal, D0=1 Inverse Inverse display D0=0 Nomal, D0=1 Inverse Whole Display tern D0=0: Normal, D0=1: Whole Display Initialize internal circuit Contrast control E.V.R. steps) Duty (1/8,1/9,1/10) (D2,D1,D0)=( 0,0,0) 1/8Duty (D2,D1,D0)=( 0,0,1) Duty (D2,D1,D0)=( 0,1,0) 1/10 Duty Power save mode (D1,D0)=(0,0) Nomal (D1,D0)=(0,1) Power save (D1,D0)=(1,0) Power save (D1,D0)=(1,1) Power save phase freqency Phase Freqenccy Select General output port level PWMEN=0:"L" output PWMEN=1:PWM output Higher order bits data registor. Lower order bits data registor. Select General output port scan output select Po3/S0 terminal D0=0 General output port D0=1 scan output this instruction.
Instruction
Display ON/OFF Page address Culumn address Higher order 3-bits Culumn address Lower order 4-bits Display data write select Inverse display Whole display Normal display Reset E.V.R. Register
Higher order Column add. Lower order Column add.
Write data
E.V.R. data
Duty select
Duty
Power save mode
Power save
Phase
Freq.
General output port phase freqency General output port serect General output port High order 3-bits enable General output port Lower order 4-bits
PWMEN
Port
High order data
Lower order data
General output port scan output select
Maker test
Test data
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NJU6538
(2-1) Instruction discription Display This instruction selects display turn-on turn-off regardless contents DDRAM.
Display Display
Page address order access DDRAM writing reading display data, both "page address set" "column address set" instructions required before accessing. page address should used icon display because only valid. page address should used icon display because only valid. Page
Column address above-mentioned, order access DDRAM writing reading display data, necessary execute both "page address set" "column address set" before accessing. 8-bit column address data will valid when both upper 3-bit lower 4-bit data into column address register. Once column address set, will automatically increment (+1) whenever DDRAM will accessed, that DDRAM will able continuously accessed without "column address set" instruction. column address will stop increment page address will changed when last address (40)H addressed.
Upper 4-bit Lower 4-bit
Column address (HEX)
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NJU6538
Display data write This instruction writes display data into selected column address DDRAM. column address automatically increments (+1) whenever display data written this instruction, that this instruction continuously issued without "column address set" instruction. Write data
*:Don't Care select This instruction selects segment driver direction. correspondence between column address segment driver direction shown Fig.1. Segment Driver Output order inverse, when this instruction executes, therefore, placement NJU6538 against panel becomes easy.
Clokwise Output(Normal) Counterclockwise Output(Inverse)
Inverse display This instruction inverses status turn-on turn-off entire pixels. doesn't change contents DDRAM. Normal Inverse
data correspond "On" data correspond "On"
Whole display This instruction turns entire pixels regardless contents DDRAM. doesn't change contents DDRAM. This instruction executed prior "Normal Inverse display On/Off Set" Instruction.
Normal Display Whole Display turns
(Whole display OFF) (Whole display
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NJU6538
Reset This instruction reset following status, however doesn't change contents DDRAM. Please careful that can't substituted reset operation using RESb terminal. Reset status "reset" instruction: Page address page Column address (00)H register (D3, Duty select :1/10 Duty General output port(Po0 Po3) phase frequency (D1,D0 "0,0") General output port(Po0 Po3) PWMEN=0, value (PWM6, 0,0,0,0,0,0,0") General output port (Po3) Po3/S0 terminal DDRAM affected this initialization.
(i)EVR register E.V.R. resister instruction adjusts contrast LCD, selects. driving voltage VLCD voltage-stages setting E.V.R. register. binary code "0000" when contrast adjustment unused. E.V.R. data
VLCD2 terminal level (Typical) LCD1 0.984V LCD1 0.968V LCD1 0.952V LCD1 0.938V LCD1 0.923V LCD1 0.909V LCD1 0.896V LCD1 0.882V LCD1 0.870V LCD1 0.857V LCD1 0.845V LCD1 0.833V LCD1 0.822V LCD1 0.811V LCD1 0.800V LCD1
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NJU6538
Duty select Duty select instruction which sets driving duty ratio 1/10 duty. Duty
Duty ratio Duty Duty 1/10 Duty
Scan Common COM1 COM8 (5x7 character 1-icon COM1 COM9 (5x7 character 2-icon COM1 COM10 (5x7 character 3-icon
Power save mode Power save mode reduces operating current application using Display selects terminal condition scan signal output. terminal, which "L", does output scan signal shown following table. Internal OSC. Stop Stop Stop
Power save
scanning output terminals
Function
output Display Display Display
Normal Power save Power save Power save scanning states.
states
General output port phase freqency General output port phase frequency instruction setting phase frequency. Phase Frequency
General Output Port phase 32-steps shift phase output timinng Po1, Po2, Po3. same phase output timinng Po3. General Output Port frequency fsys frequency. (Default) fsys frequency. (fsys system clock fosc
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NJU6538
General output port set. This instruction sets value outputted from terminals. "General output port select" instruction selects general output port output with PWM. "General output port set" instruction sets value. "General output port select instruction" "General output port instruction" necessary continuously perform. Because these instructions independently.
General output port select. This instruction selects general output port output with PWM. Port Port
General output port This instruction sets value outputted from terminals. output setting available 128-step each port output terminals.
PWMEN PWM3
PWM6 PWM2
PWM5 PWM1
PWM4 PWM0
PWMEN 0:Selected general output port output. 1:Selected general output port outputs depending data. PWM6 PWM0 value:This register sets duty value outputted from selected general output port. value requires twice, which upper 3-bit lower 4-bit. duty (Register 128.
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NJU6538
(*:Don't Care)
PWMEN PWMEN
DUTY
0/128 1/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128 10/128 11/128 12/128 13/128 14/128 15/128 16/128 17/128 18/128 19/128 20/128 21/128 22/128 23/128 24/128 25/128 26/128 27/128 28/128 29/128 30/128 31/128 32/128 33/128 34/128 35/128 36/128 37/128 38/128 39/128 40/128 41/128 42/128 43/128 44/128 45/128 46/128 47/128 48/128 49/128 50/128 51/128 52/128 53/128 54/128 55/128 56/128 57/128 58/128 59/128 60/128 61/128 62/128 63/128 64/128
65/128 66/128 67/128 68/128 69/128 70/128 71/128 72/128 73/128 74/128 75/128 76/128 77/128 78/128 79/128 80/128 81/128 82/128 83/128 84/128 85/128 86/128 87/128 88/128 89/128 90/128 91/128 92/128 93/128 94/128 95/128 96/128 97/128 98/128 99/128 100/128 101/128 102/128 103/128 104/128 105/128 106/128 107/128 108/128 109/128 110/128 111/128 112/128 113/128 114/128 115/128 116/128 117/128 118/128 119/128 120/128 121/128 122/128 123/128 124/128 125/128 126/128 127/128 128/128
Ver.2003-03-17
DUTY
NJU6538
Example output waveform terminal, shown below: phase D1=0, PWMEN=1, (PWM6, 0)=(1,0,0,0,0,0,0)
frequency (fPWM)
32-steps
32-steps
32-steps
General output port scan output select This instruction assigns function general purpose output port scan output Po3/S0 terminals.
General output port Keyscan output
Ver.2003-03-17
NJU6538
Input Data Format Timing Data format shown below. When terminal goes "L", data output. When terminal goes (rising edge) terminal "H", data input.
state Output
Input
Output
NOTE1) Data fetched rising edge. NOTE2) contents change instruction data which were written fetched rising edge SCL. NOTE3) When instruction data which were written less than 9-bit, they ignored fetched. NOTE4) When instruction data which were written over 9-bit, last 9-bit valid. Power save mode Power save mode "Power save mode set" instruction. segment common output outputted, terminal halts oscillation oscillates time key-on), consumption current decreased. Power save mode canceled, when normally "Power save mode set" instruction.
scan circuit scan circuit connects key-matrix maximum reads data keys maximum. chooses number keys key-matrix "General output port scan output select" instruction. outputs identified data after comparison with data read from key-matrix twice reliable operation. those data identified, data outputted. outputs signal through "SO" terminal request after 332T[s] (T=1/fsys=2/fosc,fsys Internal system clock frequency) when operated. Furthermore, scan circuit structures reducing external components like Diodes prevent circuit short problem.
(5-1) relation between output data matrix relation between output data matrix shows bellow table sets signal operated key. case keys application, unassigned area keys from bellow table take signal. mode Power save area keys from KD20 bellow table take signal. mode Power save area from KD15 take signal also. terminals, which connected keys, should open. KD10 KD11 KD12 KD13 KD14 KD15 KD16 KD17 KD18 KD19 KD20 KD21 KD22 KD23 KD24 KD25
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NJU6538
(5-2) Data output timing data output format shows bellow. data output mode status terminal rising signal terminal.
KD24 KD25
data
state
Output
Output
Output
(5-3) Power save flag (PSF) status Power save flag outputted after KD25 data reading. This flag sets signal mode Power save data reading sets mode Normal.
(5-4) Timing scan scan cycle 160T[S] (T=1/fsys=2/fosc,fsys Internal system clock frequency). data scan result comparison with couple scan correct judge whether Off. When result comparison correct (accord), NJU6538 recognizes outputs level from terminal after 322T[S] from start scan request read data external MPU. When terminals outputs signal, scan does operate until data reading MPU, scanned data kept. When result comparison incorrect (not accord), scan operates again Therefore, scan operate incorrectly case shorter period than 322T[S]
160T[s] T=1/fsys =2/fosc (fsys Internal system clock frequency) 322T
Instruction General output ports output scan signals (refer (1)Instruction (n)General output port scan select)
scan cycle timing data read request constant Power save mode.
Ver.2003-03-17
NJU6538
(5-5) Normal mode scan operates with follows normal mode. scan signal output terminals output signals when scan does operate, output scan signals after start scan operation. conditions scan signal input terminals state with internal pull-down resistances, though signal comes corresponding turned keys. function scan starts twice operations when turned stops when couple data continuously twice scan operations accorded fixed correct status. operates more times when status fixed keys still turning repeats again again until status fixed. correct status data stored newly scan operation does start until external reads data after status fixed. When status fixed, terminal outputs signal data read request MPU. should read data detection this signal. data read request signal released terminal outputs signal after finish data read newly scan operation. terminal requires pull resistor because Open drain type output. Multiple data output case more input that should process data itself. scan example (Normal mode)
input input
fosc
scan 322T[s] 322T[s] 322T[s]
Data send Data send Data send
data read data read request data read data read request data read data read request
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NJU6538
(5-6) Power save mode scan operates with follows Power save mode. scan signal output terminals output "H", signals Power save mode when scan does operate (refer detail instructions), output scan signals after start scan operation. conditions scan signal input terminals state with internal pull-down resistances, though signal comes corresponding turned keys. oscillation circuit function scan starts twice operations when keys cross points with terminals line turned stops when couple data continuously twice scan operations accorded fixed correct status. operates more times when status fixed keys still turning repeats again again until status fixed. correct status data stored newly scan operation does start until external reads data after status fixed. When status fixed, terminal outputs signal data read request MPU. should read data detection this signal. data read request signal released terminal outputs signal after finish data read newly scan operation. Although Power save mode released. terminal requires pull resistor because Open drain type output. Multiple data output case more input that should process data itself.
scan example (Power save mode) Ex.) "0", (K4="H" power save)
When some these lines turned oscillation starts scan starts operation until turned off.
These diodes required recognize more input keys line when only terminal outputs signal power save mode shown above example. case diodes, incorrect data read sometimes more input keys lines T=1/fsys =2/fosc (fsys Internal system clock frequency) input (K4) scan 322T[s] 322T[s]
Data send Data send Data send fosc
data read data read request Ver.2003-03-17 data read data read request
NJU6538
(5-7) More Input scan signal output terminal output level state More Input. Although state detected without diodes prevent unexpected scan signal flow, non-pressed data change pressed data triple more Input shown Fig. incorrect data output external MPU. prevention miss-recognition incorrect data, diodes should inserted front terminals shown Fig. control program should ignore combination data miss-recognition. example, keys more data should ignored.
Pressed Miss-recognized
case keys operation left picture, terminal outputs signal, this signal goes around dotted line non-pressed miss-recognized pressed key.
Fig. Miss-recognized example more input modes power save (S0=0, S1=1 Keys only line valid) power save (S0=0, S1=1 Keys only lines valid), attention about followings. When More Input operated across valid line invalid, non-pressed miss-recognized pressed key. However, data invalid line read keys more operation mean time ignored control program shown Fig. this case, diodes operate prevent miss-recognition shown Fig.
Pressed Miss-recognized
active Active Miss-recognition prevent diodes
case power save control program decide ether correct data incorrect shown above because data only line read (all data line become "0".
Fig. Miss-recognition power save
Fig. Connect miss-recognition prevent diodes
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NJU6538
(5-8) data reading operation external Display data writing Display data instruction change operate rising edge 9-bit signal. data reading operation minimum period from terminal 322T(t1) scan operation. When scan operation performs again data preventing from noise bouncing key, period from terminal 676T(t1). When terminal outputs "L", scan operation stopped after execution data reading operation. Therefore, fixed data kept until data reading operation. When data reading operation performed during terminal "H", both data from KD25 power save flag (PSF) outputted correctly. data reading operation example flowchart below shows example timer interrupt application. When terminal condition after check terminal condition every timer interrupt operation, decided data reading operation performed. When terminal condition decided Off. correct decision Off, timer interrupt cycle (1/t3) should expanded over time added with [period scan (676T case measure against bouncing key) [period data reading operation (t2)]. this time, period timer interrupt cycle (t3) must with enough margins including range fosc. Sequence data reading operation
Timer
SO="L"?
data read
Timer
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NJU6538
Timing chart data reading operation
input Interrupt
Decision
scan time data read time Interrupt cycle
Reset circuit initializes Reset circuit initializes NJU6538 Power OFF. generates reset signal initialize system less than power down detection voltage (2.0V typical). (6-1) Initial status reset Stop oscillation circuit Display (Available Serial data transmission) Disable scan function Filled data data buffer (6-2) status output port terminals Reset Output terminals SEG1 SEG65 COM1 COM10 Po3/S0
Reset status
This terminal operates segment driver outputs "L". This terminal consisted Open-drain output type circuit requires external pull-up resister connect ting external power source MPU. data read executed power reset, read data fixed "H".
reset circuit initializes following status using input 10µs(min.) over level signal into RESb terminal. will return normal operation after about 1.0µs(max.) from rising edge rest signal. "Reset" instruction can't substituted reset operation using RESb terminal. executes above-mentioned only items.
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NJU6538
(6-3) Reset status using RESb terminal (default) Serial interface register clear Display select D0="0" (Normal mode) Normal Display (Non-inverse display) Whole display D0="0" (Normal mode) Power save mode D0="0, (Normal mode) Page address page Column address register D0="1, Duty select 1/10 Duty General output port phase frequency D0="0, General output port PWMEN=0 ("L" output), value D0="0, Po3/S0 terminal D0=" (Po3)
(6-4) Initialization Hardware NJU6538 incorporates reset terminal initialize system. When level signal input over then 10us(min.) RESb terminal, reset sequence executed. this time, internal busy during after RESb terminal goes "H". Reset circuit
RESb
Hardware Reset
System Reset
Power Reset
(6-5) Power reset operation When voltage rising time power source over than 1mS, generated signal VDET initializes system NJU6538 reset. When voltage falling time power source over than 1ms, system also reset. When these voltage rising falling time power source over than 1ms, Initialization operation reset does operate correctly.
VDD>2.7V
VDET
VDET
tON>1
tOFF>1
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NJU6538
panel drive (7-1) driving voltage generation circuit driving voltage generation circuit generates driving bias voltages VLCD2, adjusts voltage steps electrical volume from VLCD1 allots voltage VLCD2, resistor-voltage-dividing shown below. VLCD1, VLCD2, terminals requires external capacitors bias voltage stabilization display quality. These values capacitors should fixed accordance with evaluation application.
Power Supply VLCD
Duty ratio Bias
1/8,1/9,1/10 VLCD2-VSS
Internal NJU6538
E.V.R. (16-steps)
VLCD1 VLCD2
(Note (Note (Note (Note
VLCD
(Note
Note Resistor typical value.
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NJU6538
ABSOLUTE MAXIMUM RATINGS
Ta=25°C PARAMETER Supply voltage Input terminal voltage SYMBOL VLCD VIN1 VIN2 VOUT1 terminal VLCD1 terminal OSC, K4,CE, SCL, terminal VLCD2, terminal CONDITIONS RATINGS -0.3 +7.0 -0.3 +11.0 -0.3 VDD+0.3 -0.3 VLCD+0.3 UNIT
terminal -0.3 +6.0 OSC, SEG1 SEG65,COM1 COM10, -0.3 VDD+0.3 VOUT2 Po2, terminal Power dissipation Pdmax Ta=25°C Storage temperature Tstg +125 Operating temperature Topr Note voltage values specified VSS=0V. Note used condition beyond absolute maximum rating, destroyed. Using within electrical characteristics strongly recommended normal operation. beyond erectric characteristics conditions will cause malfunction poor reliability. Note Decoupling capacitor should connected between stabilized operation forthe voltage converter. Output terminal voltage
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NJU6538
Electrical Characteristics
VDD=2.7 5.5V, 85°C PARAMETER Power supply Power supply Output voltage Input voltage level input voltage level input voltage level input voltage Hysteresis voltage level input current level input current Pull-up resistance Pull-down resistance Output off-leak current level output voltage level output voltage level output voltage level output voltage level output voltage Driver ON-resistance (COM) Driver ON-resistance (SEG) Oscillation Frequency
SYMBO
CONDITION VLCD1 VLCD2 SCL, SIO, SCL, SIO, SCL, SIO, SCL, SIO, SCL, SIO,
0.6VDD 0.8VDD -5.0 VDD-1.2 VDD-1.1 VDD-1.0 VDD-0.6 0.05
10.0 VLCD1 VLCD2 VLCD2 VLCD2 0.2VDD
UNIT
VLCD1 VLCD2 VIH(1) VIH(2) VIL(1) IOFFH VOH(1) VOH(2) VOL(1) VOL(2) VOL(3) RCOM RSEG fOSC
VLCD2x3/4 VLCD2x2/4 VLCD2x1/4
0.25VDD
RESb VDD=5.0V, VDD=5.0V, SIO, VO=5.5V VDD=5.0V, -500uA VDD=3.0V, -250uA VDD=5.0V, -10mA VDD=3.0V, -5mA VDD=5.0V, 25µA VDD=3.0V, VDD=5.0V, 10mA VDD=3.0V, Ta=25°C, VO=V LCD2,VSS,V0,V2 +Id=1µA (COM terminal) Ta=25°C, VO=V LCD2,VSS,V1 +Id=1µA (SEG terminal) Ta=25°C, VDD=5.0V ROSC=150k E.V.R. value "0,0,0,0" LCD1=8.0V VLCD2-VSS, Ta=25°C VLCD1-VLCD2, Ta=25°C
VDD-0.2 VDD-0.1
T.B.D.
T.B.D.
Driving voltage Bleeder resistance E.V.R. resistance Power down detect voltage Reset time Reset pulse width
REVR VDET IDD1 IDD2
T.B.D RESb RESb Power save mode VDD=5.5V, Output open fOSC=50kHz, Power save mode VLCD1=10.0V Output open fOSC=50kHz, 10.0
T.B.D
1000
Operating current
ILCD1 ILCD2
Note Note
relation VLCD1VLCD2V0V1V2VSS must maintained. RCOM RSEG resistance values between power supply terminals (VSS, VLCD2, each common terminal, supply voltage (VSS, VLCD2, each segment terminal respectively, measured when current flown every common segment terminals same time.
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NJU6538
Characteristics
VDD=2.7 5.5V, 85°C PARAMETER
SYMBOL
CONDITION
UNIT
NOTE
level tWCLL clock pulse width level tWCLH clock pulse width Data setup time SCL, Data hold time SCL, wait time setup time hold time level width tWCL output delay time SIO, Rpu=4.7k, CL=10pF rise time SIO, Rpu=4.7k, CL=10pF rise tine fall time terminal Open-Drain type output, that characteristics terminal changed values pull-up resistance
Write operation
tWCLL tWCLH tWCL
data read operation
tWCLH tWCLL
INVALID
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NJU6538
Relation between oscillation frequency frame frequency (1)1/8 duty line select time(40 T[s]) VLCD2
1/fsys 2/fosc (fsys Internal system clock frequency)
COM1
1frame
1frame
SEGn
VLCD2
Ex.)fosc=50kHz Frame frequency =1/(40T duty)=1/(40 (2/50kHz) 8)=78.1(Hz)
(2)1/10 duty
1/fsys 2/fosc (fsys Internal system clock frequency)
line select time(35 T[s]) VLCD2
COM1
1frame
1frame
SEGn
VLCD2
fosc=50kHz Frame frequency =1/(35T duty)=1/(35 (2/50kHz) 10)=71.4(Hz)
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NJU6538
APPLICATION CIRCUIT
RESb
COM1 COM10 -SEG1
7com 65seg matrix +195 icon panel
VLCD
VLCD1 VLCD2
NJU6538
SEG65 General output ports Po3/S0
Po3/S0 matrix
rising time Power source voltage Power falling time Power must keep over than because Voltage detection type Reset circuit operation. terminal requires external pull-up resistor connecting Power source external because Open-drain type output. This capacitor bias voltage stabilization should connected accordance with display quality application. terminal general output ports scan signal output duplicated-function terminals. function must selected either Segment output other.
[CAUTION] specifications this databook only given information without guarantee regards either mistakes omissions. application circuits this databook described only show representative usages product intended guarantee permission right including industrial rights.
Ver.2003-03-17

1/8, 1/9, 1/10 Duty BITMAP DRIVER with SCAN NJU6538 10-common 65-

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