HIGH VOLTAGE PHASE GATE DRIVER Features Drives IGBT/MOSFET power

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HIGH VOLTAGE PHASE GATE DRIVER Features Drives IGBT/MOSFET power

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IRS2336(D) IRS23364D
HIGH VOLTAGE PHASE GATE DRIVER Features
Drives IGBT/MOSFET power devices Gate drive supplies channel Integrated bootstrap functionality (IRS2336(4)D) Over-current protection Over-temperature shutdown input Advanced input filter Integrated deadtime protection Shoot-through (cross-conduction) protection Undervoltage lockout Enable/disable input fault reporting Adjustable fault clear timing Separate logic power grounds input logic compatible Tolerant negative transient voltage Designed with bootstrap power supplies Matched propagation delays channels -40°C 125°C operating range RoHS compliant Lead-Free
Product Summary
Topology VOFFSET VOUT IRS2336(D) IRS23364D Phase 11.5
(typical) tOFF (typical) Deadtime (typical)
Package Options
28-Lead PDIP
28-Lead SOIC Wide Body
Typical Applications
Appliance motor drives Servo drives Micro inverter drives General purpose three phase inverters 48-Lead MLPQ7X7 (without leads) 44-Lead PLCC (without leads)
Typical Connection Diagram
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IRS2336x(D) Family
Table Contents
Description Feature Comparison Simplified Block Diagram Typical Application Diagram Qualification Information Absolute Maximum Ratings Recommended Operating Conditions Static Electrical Characteristics Dynamic Electrical Characteristics Functional Block Diagram Input/Output Equivalent Circuit Diagram Lead Definitions Lead Assignments Application Information Additional Details Parameter Temperature Trends Package Details Tape Reel Details Part Marking Information Ordering Information
Page
11-12 13-14 15-16 18-34 35-38 39-42 43-45
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Description
IRS2336xD high voltage, high speed, power MOSFET IGBT gate drivers with three high-side three low-side referenced output channels 3-phase applications. This designed used with low-cost bootstrap power supplies; bootstrap diode functionality been integrated into this device reduce component count size. Proprietary HVIC latch immune CMOS technologies have been implemented rugged monolithic structure. floating logic input compatible with standard CMOS LSTTL outputs (down logic). current trip function which terminates outputs derived from external current sense resistor. Enable functionality available terminate outputs simultaneously. open-drain FAULT signal provided indicate that fault (e.g., over-current, over-temperature, undervoltage shutdown event) occurred. Fault conditions cleared automatically after delay programmed externally network connected RCIN input. output drivers feature high-pulse current buffer stage designed minimum driver cross-conduction. Shoot-through protection circuitry minimum deadtime circuitry have been integrated into this Propagation delays matched simplify HVIC's high frequency applications. floating channels used drive N-channel power MOSFETs IGBTs high-side configuration, which operate
Feature Comparison: IRS2336xD Family
Part Number IRS2336(D) IRS23364D Input Logic HIN/N, LIN/N HIN, UVLO 11.1 10.9 VIT,TH 0.46 0.46 tON, tOFF VOUT 11.5
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Simplified Block Diagram
Typical Application Diagram
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Qualification Information
Qualification Level Industrial Comments: This family passed JEDEC's Industrial qualification. IR's Consumer qualification level granted extension higher Industrial level. SOIC28W MSL3, 260°C (per IPC/JEDEC J-STD-020) MLPQ7X7 PLCC44 PDIP28 MSL3, 245°C (per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
Human Body Model Machine Model Charged Device Model Latch-Up Test RoHS Compliant
applicable (non-surface mount package style) Class (per JEDEC standard JESD22-A114) Class (per EIA/JEDEC standard EIA/JESD22-A115) Class (per JEDEC standard JESD22-C101) Class Level (per JESD78)
Qualification standards found International Rectifier's site http://www.irf.com/ Higher qualification ratings available should user have such requirements. Please contact your International Rectifier sales representative further information. Higher ratings available specific package types listed here. Please contact your International Rectifier sales representative further information. Charged Device Model classification based SOIC28W package.
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Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced unless otherwise stated table. thermal resistance power dissipation ratings measured under board mounted still conditions. Voltage clamps included between Symbol VRCIN VFLT dVS/dt PWHIN Definition side supply voltage Logic input voltage (HIN, LIN, ITRIP, IRS2336(D) IRS23364D -0.3 VSS-0.3 VSS-0.3 VSS-0.3 -0.3 VB-20 VS-0.3 COM-0.3 VSS-0.3 VCC-25 VSS+5.2 VCC+0.3 VCC+0.3 VB+0.3 VB+0.3 VCC+0.3 VCC+0.3 VCC+0.3 Units
RthJA
RCIN input voltage High-side floating well supply voltage High-side floating well supply return voltage Floating gate drive output voltage Low-side output voltage Fault output voltage Power ground Allowable offset supply transient relative High-side input pulse width 28-Lead PDIP 28-Lead SOICW Package power dissipation 44-Lead PLCC 48-Lead MLPQ7X7 28-Lead PDIP 28-Lead SOICW Thermal resistance, junction ambient 44-Lead PLCC 48-Lead MLPQ7X7 Junction temperature Storage temperature Lead temperature (soldering, seconds)
V/ns
supplies tested internal clamp exists each supply.
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IRS2336x(D) Family
Recommended Operating Conditions
proper operation, device should used within recommended conditions. voltage parameters absolute voltages referenced unless otherwise stated table. offset rating tested with supplies (VCC-COM) (VB-VS) Symbol VS(t) VFLT VRCIN VITRIP Definition Low-side supply voltage HIN, LIN, input voltage High-side floating well supply voltage High-side floating well supply offset voltage Transient high-side floating supply voltage Floating gate drive output voltage Low-side output voltage Power ground FAULT output voltage RCIN input voltage ITRIP input voltage Ambient temperature
IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D
11.5 VS+10 VS+11.5 COM-8
VSS+5 VS+20 VS+20 VSS+5
Units
Logic operation Logic state held -VBS. Please refer Design DT97-3 more details. Operational transient negative with pulse width. Guaranteed design. Refer Application Information section this datasheet more details.
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2008 International Rectifier
IRS2336x(D) Family
(VCC-COM) (VB-VS) 25oC unless otherwise specified. parameters referenced applicable channels. parameters referenced respective applicable respective output leads VCCUV parameters referenced VSS. VBSUV parameters referenced Symbol VCCUV+ VCCUVVCCUVHY VBSUV+ VBSUVVBSUVHY IQBS IQCC IoVIH VIN,CLAMP IHIN+ IHINILIN+ ILINVRCIN,TH VRCIN,HY IRCIN RON,RCIN Definition IRS2336(D) supply undervoltage positive IRS23364D going threshold supply undervoltage negative IRS2336(D) IRS23364D going threshold IRS2336(D) supply undervoltage hysteresis IRS23364D IRS2336(D) supply undervoltage positive IRS23364D going threshold supply undervoltage negative IRS2336(D) IRS23364D going threshold IRS2336(D) supply undervoltage hysteresis IRS23364D High-side floating well offset supply leakage Quiescent supply current IRS2336 Quiescent supply current IR2336(4)D High level output voltage drop, VBIAS-VO level output voltage drop, Output high short circuit pulsed current Output short circuit pulsed current Logic input voltage Logic input voltage Logic input voltage Logic input voltage Input voltage clamp (HIN, LIN, ITRIP Input bias current High) Input bias current Low) Input bias current High) Input bias current Low) RCIN positive going threshold RCIN hysteresis RCIN input bias current RCIN resistance 10.4 10.2 10.4 10.2 IRS2336(D) IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D IRS2336(D) IRS23364D 11.1 10.9 11.1 10.9 0.90 0.40 11.6 11.4 11.6 11.4 5.65 VRCIN Units Test Conditions
Static Electrical Characteristics
inputs state VO=0 V,VIN=0 VO=15 V,VIN=5
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Static Electrical Characteristics (continued)
Symbol Definition VIT,TH+ ITRIP positive going threshold VIT,THVIT,HYS IITRIP+ IITRIPVEN,TH+ VEN,THIEN+ IENRON,FLT ITRIP negative going threshold ITRIP hysteresis "High" ITRIP input bias current "Low" ITRIP input bias current Enable positive going threshold Enable negative going threshold "High" enable input bias current "Low" enable input bias current FAULT resistance Internal diode (IRS2336(4)D) IRS2336(D) IRS23364D IRS2336(D) IRS23364D 0.37 0.46 0.07 0.55 Units Test Conditions
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IRS2336x(D) Family
Dynamic Electrical Characteristics
Symbol tOFF tFIL,IN tFILTER,EN tFLTCLR tITRIP tFLT VCC= COM, 25oC, 1000 unless otherwise specified. Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Input filter time (HIN, LIN, ITRIP) Enable output shutdown propagation delay Enable input filter time FAULT clear time RCIN: ITRIP output shutdown propagation delay ITRIP blanking time ITRIP FAULT propagation delay Deadtime matching Delay matching time (tON, tOFF) Pulse width distortion
1.65
1200
Units
Test Conditions
VIN, VITRIP VITRIP VITRIP without external deadtime with external deadtime larger than input=10
minimum width input pulse recommended exceed ensure filtering time input filter exceeded. This parameter applies channels. Please application section more details. defined PWIN PWOUT.
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IRS2336x(D) Family
Functional Block Diagram: IRS2336(D)
Note: IRS2336 without "Integrated BootFET"
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IRS2336x(D) Family
Functional Block Diagram: IRS23364D
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IRS2336x(D) Family
Input/Output Equivalent Circuit Diagrams: IRS2336(D)
Diode
ITRIP
Diode
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IRS2336x(D) Family
Input/Output Equivalent Circuit Diagrams: IRS23364D
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IRS2336x(D) Family
Lead Definitions: IRS2336(D)
Symbol HIN1/N HIN2/N HIN3/N LIN1/N LIN2/N LIN3/N FAULT/N ITRIP RCIN Description Low-side supply voltage Logic ground High-side gate drive floating supply (phase High-side gate drive floating supply (phase High-side gate drive floating supply (phase High voltage floating supply return (phase High voltage floating supply return (phase High voltage floating supply return (phase Logic inputs high-side gate driver outputs (phase input out-of-phase with output Logic inputs high-side gate driver outputs (phase input out-of-phase with output Logic inputs high-side gate driver outputs (phase input out-of-phase with output Logic inputs low-side gate driver outputs (phase input out-of-phase with output Logic inputs low-side gate driver outputs (phase input out-of-phase with output Logic inputs low-side gate driver outputs (phase input out-of-phase with output High-side driver outputs (phase High-side driver outputs (phase High-side driver outputs (phase Low-side driver outputs (phase Low-side driver outputs (phase Low-side driver outputs (phase Low-side gate drive return Indicates over-current, over-temperature (ITRIP), low-side undervoltage lockout occurred. This negative logic open-drain output. over-current overtemperature protection requires external components. Logic input shutdown functionality. Logic functions when high (i.e., positive logic). effect FAULT latched. Analog input over-current shutdown. When active, ITRIP shuts down outputs activates FAULT RCIN low. When ITRIP becomes inactive, FAULT stays active externally time tFLTCLR, then automatically becomes inactive (open-drain high impedance). external network input used define FAULT CLEAR delay (tFLTCLR) approximately equal R*C. When RCIN FAULT goes back into open-drain high-impedance state.
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IRS2336x(D) Family
Lead Definitions: IRS23364D
Symbol HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT/N ITRIP RCIN Description Low-side supply voltage Logic ground High-side gate drive floating supply (phase High-side gate drive floating supply (phase High-side gate drive floating supply (phase High voltage floating supply return (phase High voltage floating supply return (phase High voltage floating supply return (phase Logic inputs high-side gate driver outputs (phase input in-phase with output Logic inputs high-side gate driver outputs (phase input in-phase with output Logic inputs high-side gate driver outputs (phase input in-phase with output Logic inputs low-side gate driver outputs (phase input in-phase with output Logic inputs low-side gate driver outputs (phase input in-phase with output Logic inputs low-side gate driver outputs (phase input in-phase with output High-side driver outputs (phase High-side driver outputs (phase High-side driver outputs (phase Low-side driver outputs (phase Low-side driver outputs (phase Low-side driver outputs (phase Low-side gate drive return Indicates over-current, over-temperature (ITRIP), low-side undervoltage lockout occurred. This negative logic open-drain output. over-current overtemperature protection requires external components. Logic input shutdown functionality. Logic functions when high (i.e., positive logic). effect FAULT latched. Analog input over-current shutdown. When active, ITRIP shuts down outputs activates FAULT RCIN low. When ITRIP becomes inactive, FAULT stays active externally time tFLTCLR, then automatically becomes inactive (open-drain high impedance). external network input used define FAULT CLEAR delay (tFLTCLR) approximately equal R*C. When RCIN FAULT goes back into open-drain high-impedance state.
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Lead Assignments
IRS2336(D)
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IRS2336x(D) Family
Application Information Additional Details
Information regarding following topics included subsections within this section datasheet. IGBT/MOSFET Gate Drive Switching Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Enable Input Fault Reporting Programmable Fault Clear Timer Over-Current Protection Over-Temperature Shutdown Protection Truth Table: Undervoltage lockout, ITRIP, ENABLE Advanced Input Filter Short-Pulse Noise Rejection Integrated Bootstrap Functionality Bootstrap Power Supply Design Separate Logic Power Grounds Tolerant Negative Transients Layout Tips Additional Documentation
IGBT/MOSFET Gate Drive IRS2336xD HVICs designed drive MOSFET IGBT power devices. Figures illustrate several parameters associated with gate drive functionality HVIC. output current HVIC, used drive gate power switch, defined voltage that drives gate external power switch defined high-side power switch low-side power switch; this parameter sometimes generically called VOUT this case does differentiate between high-side low-side output voltage.
VCC)
VCC)
VLO)
COM) COM)
Figure HVIC sourcing current
Figure HVIC sinking current
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Switching Timing Relationships relationship between input output signals IRS2336(D) IRS23364D illustrated below Figures From these figures, definitions several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, associated with this device.
Figure Switching time waveforms (IRS2336(D))
Figure Switching time waveforms (IRS23364D)
following figures illustrate timing relationships some functionality IRS2336xD; this functionality described further detail later this document. During interval Figure HVIC received command turn-on both high- low-side switches same time; result, shoot-through protection HVIC prevented this condition both highand low-side output held state. Interval Figures shows that signal ITRIP input gone from high state; result, gate drive outputs have been disabled (i.e., that returned state; also held low), voltage RCIN been pulled fault reported FAULT output transitioning state. Once ITRIP input returned state, output will remain disabled fault condition reported until voltage RCIN charges VRCIN,TH (see interval Figure charging characteristics dictated network attached RCIN pin. During intervals Figure that enable (EN) been pulled case when driver received command from control shutdown); this results outputs (HOx LOx) being held state until enable pulled high.
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Figure Input/output timing diagram IRS2336xD family
Figure Detailed view intervals Deadtime This family HVICs features integrated deadtime protection circuitry. deadtime these fixed; other within IR's HVIC portfolio feature programmable deadtime greater design flexibility. deadtime feature inserts time period minimum deadtime) which both high- low-side power switches held off; this done ensure that power switch being turned fully turned before second power switch turned This minimum deadtime automatically inserted whenever external deadtime shorter than external deadtimes larger than modified gate driver. Figure illustrates deadtime period relationship between output gate signals. deadtime circuitry IRS2336xD matched with respect high- low-side outputs given channel; additionally, deadtimes each three channels matched. Figure defines deadtime parameters (i.e., DT2) specific channel; deadtime matching parameter (MDT) associated with IRS2336xD specifies maximum difference between DT2. parameter also applies when comparing channel IRS2336xD that another.
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LINx
HINx
Figure Illustration deadtime Matched Propagation Delays IRS2336xD family HVICs designed with propagation delay matching circuitry. With this feature, IC's response output signal input requires approximately same time duration (i.e., tON, tOFF) both low-side channels high-side channels; maximum difference specified delay matching parameter (MT). Additionally, propagation delay each low-side channel matched when compared other low-side channels propagation delays high-side channels matched with each other; specification applies well. propagation turn-on delay (tON) IRS2336xD matched propagation turn-on delay (tOFF). Input Logic Compatibility inputs this compatible with standard CMOS outputs. IRS2336xD family been designed compatible with logic-level signals. IRS2336(D) features integrated Zener clamp HIN, LIN, ITRIP, pins; IRS23364D does offer this input clamp. Figure illustrates input signal IRS2336(D) IRS23364D, input threshold values, logic state result input signal.
Figure input thresholds
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Undervoltage Lockout Protection This family provides undervoltage lockout protection both (logic low-side circuitry) power supply (high-side circuitry) power supply. Figure used illustrate this concept; VBS) plotted over time waveform crosses UVLO threshold (VCCUV+/- VBSUV+/-) undervoltage protection enabled disabled. Upon power-up, should voltage fail reach VCCUV+ threshold, will turn-on. Additionally, voltage decreases below VCCUV- threshold during operation, undervoltage lockout circuitry will recognize fault condition shutdown high- low-side gate drive outputs, FAULT will transition state inform controller fault condition. Upon power-up, should voltage fail reach VBSUV threshold, will turn-on. Additionally, voltage decreases below VBSUV threshold during operation, undervoltage lockout circuitry will recognize fault condition, shutdown high-side gate drive outputs UVLO protection ensures that drives external power devices only when gate supply voltage sufficient fully enhance power devices. Without this feature, gates external power switch could driven with voltage, resulting power switch conducting current while channel impedance high; this could result very high conduction losses within power device could lead power device failure.
Figure UVLO protection Shoot-Through Protection IRS2336xD family high-voltage equipped with shoot-through protection circuitry (also known crossconduction prevention circuitry). Figure shows this protection circuitry prevents both high- low-side switches from conducting same time. Table illustrates input/output relationship devices form truth table. Note that IRS2336(D) inverting inputs (the output out-of-phase with respective input) while IRS23364D non-inverting inputs (the output in-phase with respective input).
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Shoot-through protection enabled
Figure Illustration shoot-through protection circuitry
IRS2336(D)
IRS23364D
Table Input/output truth table IRS2336D IRS23364D Enable Input IRS2336xD family HVICs equipped with enable input that used shutdown enable HVIC. When high state HVIC able operate normally (assuming other fault conditions). When condition occurs that should shutdown HVIC, should logic state. enable circuitry IRS2336xD features input filter; minimum input duration specified tFILTER,EN. Please refer parameters VEN,TH+, VEN,TH-, details use. Table gives summary this pin's functionality Figure illustrates outputs' response shutdown command.
Enable Input Enable input high Enable input Outputs enabled* Outputs disabled
Table Enable functionality truth table (*assumes other fault condition)
Figure Output enable timing waveform
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Fault Reporting Programmable Fault Clear Timer IRS2336xD family provides integrated fault reporting output adjustable fault clear timer. There situations that would cause HVIC report fault FAULT pin. first undervoltage condition second ITRIP recognizes fault. Once fault condition occurs, FAULT internally pulled fault clear timer activated. fault output stays state until fault condition been removed fault clear timer expires; once fault clear timer expires, voltage FAULT will return VCC. length fault clear time period (tFLTCLR) determined exponential charging characteristics capacitor where time constant RRCIN CRCIN. Figure where that fault condition occurred (UVLO ITRIP), RCIN FAULT pulled VSS, once fault been removed, fault clear timer begins. Figure shows that RRCIN connected between RCIN pin, while CRCIN placed between RCIN pins.
Figure RCIN FAULT waveforms design guidelines this network shown Table
Figure Programming fault clear timer
CRCIN
Ceramic RON,RCIN
RRCIN
Table Design guidelines length fault clear time period determined using formula below. vC(t) Vf(1-e-t/RC) tFLTCLR -(RRCINCRCIN)ln(1-VRCIN,TH/VCC)
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Over-Current Protection IRS2336xD HVICs equipped with ITRIP input pin. This functionality used detect over-current events bus. Once HVIC detects over-current event through ITRIP pin, outputs shutdown, fault reported through FAULT pin, RCIN pulled VSS. level current which over-current protection initiated determined resistor network (i.e., connected ITRIP shown Figure ITRIP threshold (VIT,TH+). circuit designer will need determine maximum allowable level current select such that voltage node reaches over-current threshold (VIT,TH+) that current level. VIT,TH+ R0IDC-(R1/(R1+R2))
Figure Programming over-current protection example, typical value resistor could voltage ITRIP should allowed exceed necessary, external voltage clamp used. Over-Temperature Shutdown Protection ITRIP input IRS2336xD also used detect over-temperature events system initiate shutdown HVIC (and power switches) that time. order this functionality, circuit designer will need design resistor network shown Figure select maximum allowable temperature. This network consists thermistor standard resistors temperature changes, resistance thermistor will change; this will result change voltage node resistor values should selected such voltage should reach threshold voltage (VIT,TH+) ITRIP functionality time that maximum allowable temperature reached. voltage ITRIP should allowed exceed When using both over-current protection over-temperature protection with ITRIP input, OR-ing diodes (e.g., DL4148) used. This network shown Figure OR-ing diodes have been labeled
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Figure Programming over-temperature protection Truth Table: Undervoltage lockout, ITRIP, ENABLE
Figure Using over-current protection overtemperature protection
Table provides truth table IRS2336xD. first line shows that UVLO been tripped; FAULT output gone gate drive outputs have been disabled. VCCUV latched this case when greater than VCCUV, FAULT output returns high impedance state. second case shows that UVLO been tripped that high-side gate drive outputs have been disabled. After exceeds VBSUV threshold, will stay until HVIC input receives falling (IRS2336(D)) rising (IRS23364D) transition HIN. third case shows normal operation HVIC. fourth case illustrates that ITRIP trip threshold been reached that gate drive outputs have been disabled fault been reported through fault pin. last case, HVIC received command through input shutdown; result, gate drive outputs have been disabled. <VCCUV <VBSUV ITRIP >VITRIP RCIN High High High High FAULT High impedance High impedance High impedance
UVLO UVLO Normal operation ITRIP fault command
Table IRS2336xD UVLO, ITRIP, RCIN, FAULT truth table Advanced Input Filter advanced input filter allows improvement input/output pulse symmetry HVIC helps reject noise spikes short pulses. This input filter been applied HIN, LIN, inputs. working principle filter shown Figures Figure shows typical input filter asymmetry input output. upper pair waveforms (Example show input signal with duration much longer then tFIL,IN; resulting output approximately difference between input signal tFIL,IN. lower pair waveforms (Example show input signal with duration slightly longer then tFIL,IN; resulting output approximately difference between input signal tFIL,IN. Figure shows advanced input filter symmetry between input output. upper pair waveforms (Example show input signal with duration much longer then tFIL,IN; resulting output
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approximately same duration input signal. lower pair waveforms (Example show input signal with duration slightly longer then tFIL,IN; resulting output approximately same duration input signal.
Figure Typical input filter Short-Pulse Noise Rejection
Figure Advanced input filter
This device's input filter provides protection against short-pulses (e.g., noise) input lines. duration input signal less than tFIL,IN, output will change states. Example Figure shows input output state with positive noise spikes durations less than tFIL,IN; output does change states. Example Figure shows input output high state with negative noise spikes durations less than tFIL,IN; output does change states.
Example
Figure Noise rejecting input filters Figures present data that illustrates characteristics input filters while receiving pulses. input filter characteristic shown Figure left side illustrates narrow pulse (short positive pulse) characteristic while left shows narrow pulse (short negative pulse) characteristic. x-axis Figure shows duration PWIN, while y-axis shows resulting PWOUT duration. seen that PWIN duration less than tFIL,IN, that resulting PWOUT duration zero (e.g., filter rejects input signal/noise). also that once PWIN duration exceed tFIL,IN, that PWOUT durations mimic PWIN durations very well over this interval with symmetry improving duration increases. ensure proper operation HVIC, suggested that input pulse width high-side inputs
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Example
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IRS2336x(D) Family
difference between PWOUT PWIN signals both narrow narrow cases shown Figure careful reader will note scale y-axis. x-axis Figure shows duration PWIN, while y-axis shows resulting PWOUT-PWIN duration. This data illustrates performance near symmetry this input filter.
1000 Time (ns)
Narrow Pulse
PWOUT PWIN
Time (ns)
1000
Figure IRS2336xD input filter characteristic
Figure Difference between input pulse output pulse Integrated Bootstrap Functionality IRS2336xD family features integrated high-voltage bootstrap MOSFETs that eliminate need external bootstrap diodes resistors many applications. There bootstrap MOSFET each high-side output channel connected between supply respective floating supply (i.e., VB1, VB2, VB3); Figure illustration this internal connection. integrated bootstrap MOSFET turned only during time when `high', limited source current RBS. voltage will charged each cycle depending on-time value capacitor, drain-source (collector-emitter) drop external IGBT MOSFET), low-side freewheeling diode drop. bootstrap MOSFET each channel follows state respective low-side output stage (i.e., bootstrap MOSFET when high, when low), unless voltage higher than approximately 110% VCC. that case, bootstrap MOSFET designed remain until returns below that threshold; this concept illustrated Figure
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Figure Internal bootstrap MOSFET connection
Figure Bootstrap MOSFET state diagram
bootstrap MOSFET suitable most modulation schemes used either parallel with external bootstrap network (i.e., diode resistor) replacement integrated bootstrap replacement external bootstrap network have some limitations. example this limitation arise when this functionality used non-complementary schemes (typically 6-step modulations) very high duty cycle. these cases, superior performances achieved using external bootstrap diode parallel with internal bootstrap network. Bootstrap Power Supply Design information related design bootstrap power supply while using integrated bootstrap functionality IRS2336xD family, please refer Application Note 1123 (AN-1123) entitled "Bootstrap Network Analysis: Focusing Integrated Bootstrap Functionality." This application note available www.irf.com. information related design standard bootstrap power supply (i.e., using external discrete diode) please refer Design 04-4 (DT04-4) entitled "Using Monolithic High Voltage Gate Drivers." This design available www.irf.com. Separate Logic Power Grounds IRS2336xD separate logic power ground (VSS respectively) eliminate some noise problems that occur power conversion applications. Current sensing shunts commonly used many applications power inverter protection (i.e., over-current protection), case motor drive applications, motor current measurements. these situations, often beneficial separate logic power grounds. Figure shows HVIC with separate pins these grounds used system. used reference point logic over-current circuitry; figure voltage between ITRIP pin. Alternatively, reference point low-side gate drive circuitry. output voltage used drive low-side gate VLO-COM; gate-emitter voltage (VGE) low-side switch output voltage driver minus drop across RG,LO.
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(x3) (x3) (x3) (x3) RG,HO
HVIC
ITRIP
RG,LO
VGE1
VGE2
VGE3
Figure Separate pins Tolerant Negative Transients common problem today's high-power switching converters transient response switch node's voltage power switches transition quickly while carrying large current. typical 3-phase inverter circuit shown Figure here define power switches diodes inverter. high-side switch (e.g., IGBT Figures switches off, while phase current flowing inductive load, current commutation occurs from high-side switch (Q1) diode (D2) parallel with lowside switch same inverter leg. same instance, voltage node VS1, swings from positive voltage negative voltage.
Figure Three phase inverter
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Figure conducting
Figure conducting
Also when phase current flows from inductive load back inverter (see Figures 29), IGBT switches current commutation occurs from same instance, voltage node, VS2, swings from positive voltage negative voltage.
Figure conducting
Figure conducting
However, real inverter circuit, voltage swing does stop level negative bus, rather swings below level negative bus. This undershoot voltage called "negative transient". circuit shown Figure depicts three phase inverter; Figures show simplified illustration commutation current between parasitic inductances power circuit from bonding tracks lumped together each IGBT. When high-side switch below voltage voltage drops associated with power switch parasitic elements circuit. When high-side power switch turns off, load current momentarily flows low-side freewheeling diode inductive load connected (the load shown these figures). This current flows from (which connected HVIC) load negative voltage between induced (i.e., HVIC higher potential than pin).
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Figure Parasitic Elements
Figure positive
Figure negative
typical motor drive system, dV/dt typically designed range V/ns. negative transient voltage exceed this range during some events such short circuit over-current shutdown, when di/dt greater than normal operation. International Rectifier's HVICs have been designed robustness required many today's demanding applications. IRS2336xD been seen withstand large negative transient conditions order period illustration IRS2336D's performance seen Figure This experiment conducted using various loads create this condition; curve shown this figure illustrates successful operation IRS2336D under these stressful conditions. case transients greater then period time greater than HVIC designed hold high-side outputs state order ensure that high- low-side power switches same time.
Figure Negative transient results International Rectifier HVIC Even though IRS2336xD been shown able handle these large negative transient conditions, highly recommended that circuit designer always limit negative transients much possible careful layout component use. Layout Tips Distance between high voltage components: It's strongly recommended place components tied floating voltage pins near respective high voltage portions device. IRS2336xD PLCC44 package some unused pins removed order maximize distance between high voltage voltage pins. Please Case Outline PLCC44 information this datasheet details.
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Ground Plane: order minimize noise coupling, ground plane should placed under near high voltage floating side. Gate Drive Loops: Current loops behave like antennas able receive transmit noise (see Figure 34). order reduce coupling improve power switch turn on/off performance, gate drive loops must reduced much possible. Moreover, current injected inside gate drive loop IGBT collector-to-gate parasitic capacitance. parasitic auto-inductance gate loop contributes developing voltage across gate-emitter, thus increasing possibility self turn-on effect.
Figure Antenna Loops Supply Capacitor: recommended place bypass capacitor (CIN) between pins. This connection shown Figure ceramic ceramic capacitor suitable most applications. This component should placed close possible pins order reduce parasitic elements.
Figure Supply capacitor
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IRS2336x(D) Family
Routing Placement: Power stage parasitic elements contribute large negative voltage transients switch node; recommended limit phase voltage negative transients. order avoid such conditions, recommended minimize high-side emitter low-side collector distance, minimize low-side emitter negative rail stray inductance. However, where negative spikes remain excessive, further steps taken reduce spike. This includes placing resistor less) between switch node (see Figure 36), some cases using clamping diode between (see Figure 37). DT04-4 www.irf.com more detailed information.
Figure resistor Additional Documentation
Figure clamping diode
Several technical documents related HVICs available www.irf.com; Site Search function document number quickly locate them. Below short list some these documents. DT97-3: Managing Transients Control Driven Power Stages AN-1123: Bootstrap Network Analysis: Focusing Integrated Bootstrap Functionality DT04-4: Using Monolithic High Voltage Gate Drivers AN-978: Floating MOS-Gate Driver
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IRS2336x(D) Family
Parameter Temperature Trends
Figures 38-58 provide information experimental performance IRS2336xD HVIC. line plotted each figure generated from actual data. small number individual samples were tested three temperatures (-40 order generate experimental (Exp.) curve. line labeled Exp. consist three data points (one data point each tested temperatures) that have been connected together illustrate understood temperature trend. individual data points curve were determined calculating averaged experimental value parameter (for given temperature).
1000
1000
tOFF (ns)
(ns)
Exp.
Exp.
Temperature
Temperature
Figure temperature
Figure tOFF temperature
1500
Exp.
1200
tITRIP (ns)
(ns)
Exp.
Temperature
Temperature
Figure temperature
Figure tITRIP temperature
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IRS2336x(D) Family
1200 1000 1000
tFLT (ns)
Exp.
(ns)
Exp.
Temperature
Temperature
Figure tFLT temperature
Figure temperature
Exp.
(ns)
(ns)
Exp.
Temperature
Temperature
Figure temperature
Figure temperature
Exp.
TRIP+
(ns)
Exp.
Temperature
Temperature
Figure temperature
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Figure IITRIP+ temperature
2008 International Rectifier
IRS2336x(D) Family
(mA)
Exp.
IQBS
Exp.
Temperature
Temperature
Figure IQCC temperature
Figure IQBS temperature
0.60
0.60
Exp.
0.40
0.40
0.20
Exp.
0.20 0.00 0.00
Temperature
Temperature
Figure temperature
Figure temperature
Exp.
Exp.
VCCUV+
VCCUV-
Temperature
Temperature
Figure VCCUV+ temperature
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Figure VCCUV- temperature
2008 International Rectifier
IRS2336x(D) Family
Exp.
Exp.
VBSUV+
VBSUV-
Temperature
Temperature
Figure VBSUV+ temperature
Figure VBSUV- temperature
VIT,TH+ (mV)
VIT,TH- (mV)
EXP.
Exp.
Temperature (oC)
Temperature
Figure VIT,TH+ temperature
Figure VIT,TH- temperature
RON,RCIN
RON,FLT
Exp.
Exp.
Temperature
Temperature
Figure RON,RCIN temperature
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Figure RON,FLT temperature
2008 International Rectifier
IRS2336x(D) Family
Package Details: PDIP28
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2008 International Rectifier
IRS2336x(D) Family
Package Details: SOIC28W
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2008 International Rectifier
IRS2336x(D) Family
Package Details: PLCC44
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2008 International Rectifier
IRS2336x(D) Family
Case outline drawing for: MLPQ7X7
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2008 International Rectifier
IRS2336x(D) Family
Tape Reel Details: SOIC28W
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 11.90 12.10 3.90 4.10 23.70 24.30 11.40 11.60 10.80 11.00 18.20 18.40 1.50 1.50 1.60
28SOICW Imperial 0.468 0.476 0.153 0.161 0.933 0.956 0.448 0.456 0.425 0.433 0.716 0.724 0.059 0.059 0.062
REEL DIMENSIONS 28SOICW Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 30.40 1.196 26.50 29.10 1.04 1.145 24.40 26.40 0.96 1.039
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IRS2336x(D) Family
Tape Reel Details: PLCC44
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 23.90 24.10 3.90 4.10 31.70 32.30 14.10 14.30 17.90 18.10 17.90 18.10 2.00 1.50 1.60
44PLCC Imperial 0.94 0.948 0.153 0.161 1.248 1.271 0.555 0.562 0.704 0.712 0.704 0.712 0.078 0.059 0.062
REEL DIMENSIONS 44PLCC Metric Code 329.60 330.25 20.95 21.45 12.80 13.20 1.95 2.45 98.00 102.00 38.4 34.7 35.8 32.6 33.1
Imperial 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 1.511 1.366 1.409 1.283 1.303
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2008 International Rectifier
IRS2336x(D) Family
Tape Reel Details: MLPQ7X7
LOADED TAPE FEED DIRECTION
NOTE CONTROLLING DIMENSION
CARRIER TAPE DIMENSION 48MLPQ7X7 Metric Imperial Code 11.90 12.10 0.474 0.476 3.90 4.10 0.153 0.161 15.70 16.30 0.618 0.641 7.40 7.60 0.291 0.299 7.15 7.35 0.281 0.289 7.15 7.35 0.281 0.289 1.50 0.059 1.50 1.60 0.059 0.062
REEL DIMENSIONS 48MLPQ7X7 Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 22.4 0.881 18.5 21.1 0.728 0.83 16.4 18.4 0.645 0.724
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IRS2336x(D) Family
Part Marking Information
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IRS2336x(D) Family
Ordering Information
Standard Pack Form Tube/Bulk Tape Reel Tube/Bulk Tube/Bulk Tape Reel PLCC44 PDIP28 SOIC28W IRS2336 PLCC44 PDIP28 SOIC28W IRS23364D PLCC44 Tube/Bulk Tape Reel Tube/Bulk Tube/Bulk Tape Reel Tube/Bulk Tape Reel Tube/Bulk Tube/Bulk Tape Reel Tube/Bulk Tape Reel Quantity 3000 1000 1000 1000
Base Part Number
Package Type
Complete Part Number IRS2336DMPbF IRS2336DMTRPbF IRS2336DPbF IRS2336DSPbF IRS2336DSTRPbF IRS2336DJPbF IRS2336DJTRPbF IRS2336PbF IRS2336SPbF IRS2336STRPbF IRS2336JPbF IRS2336JTRPbF IRS23364DPbF IRS23364DSPbF IRS23364DSTRPbF IRS23364DJPbF IRS23364DJTRPbF
MLPQ7x7 PDIP28 IRS2336D SOIC28W
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2008 International Rectifier
IRS2336x(D) Family
information provided this document believed accurate reliable. However, International Rectifier assumes responsibility consequences this information. International Rectifier assumes responsibility infringement patents other rights third parties which result from this information. license granted implication otherwise under patent patent rights International Rectifier. specifications mentioned this document subject change without notice. This document supersedes replaces information previously supplied.
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2008 International Rectifier

HIGH VOLTAGE PHASE GATE DRIVER Features Drives IGBT/MOSFET power

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