IR21364(S&J)PBF 3-PHASE BRIDGE DRIVER Floating channel desig

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IR21364(S&J)PBF 3-PHASE BRIDGE DRIVER Floating channel desig

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Data Sheet PD60342
IR21364(S&J)PBF
3-PHASE BRIDGE DRIVER
Floating channel designed bootstrap operation fully operational +600 Tolerant negative transient voltage dV/dt immune Gate drive supply range from 11.5 Undervoltage lockout channels Over-current shutdown turns drivers Independent half-bridge drivers Matched propagation delay channels Cross-conduction prevention logic side High side outputs phase with inputs. logic compatible Lower di/dt gate drive better noise immunity Externally programmable delay automatic fault clear RoHS Compliant
Packages
28-Lead SOIC
44-Lead PLCC Leads
Applications:
*Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives
Description
IR21364(S&J)PBF high voltage, high speed power MOSFET IGBT drivers with three independent high side referenced output channels 3-phase applications. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs compatible with CMOS LSTTL outputs, down 3.3V logic. current trip function which terminates outputs derived from external current sense resistor. enable function available terminate outputs simultaneously. open-drain FAULT signal provided indicate that overcurrent undervoltage shutdown occurred. Overcurrent fault conditions cleared automatically after delay programmed externally network connected RCIN input. output drivers feature high pulse current buffer stage designed minimum driver cross-conduction. Propagation delays matched simplify high frequency applications. floating channel used drive N-channel power MOSFETs IGBTs high side configuration which operates
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Qualification Information
Qualification Level
Industrial Comments: This family passed JEDEC's Industrial qualification. IR's Consumer qualification level granted extension higher Industrial level. SOIC28W MSL3, 260°C (per IPC/JEDEC J-STD-020) MSL3, 245°C (per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level PLCC44 Human Body Model Machine Model Latch-Up Test RoHS Compliant
Class (per JEDEC standard JESD22-A114) Class (per EIA/JEDEC standard EIA/JESD22-A115) Class Level (per JESD78)
Qualification standards found International Rectifier's site http://www.irf.com/ Higher qualification ratings available should user have such requirements. Please contact your International Rectifier sales representative further information. Higher ratings available specific package types listed here. Please contact your International Rectifier sales representative further information.
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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage device occur. voltage parameters absolute voltages referenced COM. thermal resistance power dissipation ratings measured under board mounted still conditions.
Symbol
VLO1,2,3 VFLT dV/dt RthJA High side offset voltage
Definition
High side floating supply voltage High side floating output voltage side logic fixed supply voltage Logic ground side output voltage Input voltage LIN, HIN, ITRIP, RCIN FAULT output voltage Allowable offset voltage slew rate Package power dissipation Thermal resistance, junction ambient Junction temperature Storage temperature Lead temperature (soldering, seconds) lead SOIC) lead PLCC) lead SOIC) lead PLCC)
-0.3 -0.3 -0.3 -0.3 -0.3
lower Vss+15
Units
1,2,3 1,2,3 VS1,2,3 1,2,3
V/ns °C/W
Recommended Operating Conditions
input/output logic timing diagram shown Fig. proper operation device should used within recommended conditions. voltage parameters absolute referenced COM. offset rating tested with supplies biased differential.
Symbol
VB1,2,3 1,2,3 1,2,3 VLO1,2,3 VFLT VRCIN
Definition
High side floating supply voltage High side floating supply voltage side supply voltage High side output voltage side output voltage Logic ground FAULT output voltage RCIN input voltage IR21364 IR21364
Min.
VS1,2,3 +11.5 Note 11.5 VS1,2,3
Max.
VS1,2,3 VB1,2,3
Units
ITRIP input voltage Logic input voltage LIN, HIN, Ambient temperature Note Logic operational Logic state held VBS.
(Please refer Design DT97 more details).
VITRIP
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Static Electrical Characteristics
VBIAS (VCC, 1,2,3) 25°C unless otherwise specified. VIN, parameters referenced applicable channels (HIN1,2,3 LIN1,2,3). parameters referenced VS1,2,3 applicable respective output leads: HO1,2,3 LO1,2,3.
Symbol
VEN,TH+ VEN,THVIT,TH+ VIT,HYS VRCIN, VRCIN, VCCUV+ VCCUVVCCUVHY VBSUV+ VBSUVVBSUVHY IQBS IQCC ILIN+ ILINIHIN+ IHINIITRIP+ IITRIPIEN+ IENIRCIN IoRon_RCIN Ron_FAULT
Definition
Logic input voltage Logic input voltage Enable positive going threshold Enable negative going threshold ITRIP positive going threshold ITRIP hysteresis RCIN positive going threshold RCIN hysteresis High level output voltage, VBIAS level output voltage, supply undervoltage positive going threshold supply undervoltage negative going threshold supply undervoltage hysteresis supply undervoltage positive going threshold supply undervoltage negative going threshold supply undervoltage hysteresis Offset supply leakage current Quiescent supply current Quiescent supply current Input bias current (LOUT Input bias current (LOUT Input bias current (HOUT Input bias current (HOUT "High" ITRIP input bias current "Low" ITRIP input bias current "High" ENABLE input bias current "Low" ENABLE input bias current RCIN input bias current Output high short circuit pulsed current Output short circuit pulsed current RCIN resistance FAULT resistance IR21364 IR21364 IR21364 IR21364 IR21364 IR21364
Units
0.37 0.46 0.07 10.4 10.4 0.55 11.2 10.2 11.2 10.2
Test Conditions
VB1,2,3 VS1,2,3 VLIN VLIN VHIN VHIN VITRIP VITRIP
Vrcin
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Dynamic Electrical Characteristics
Dynamic Electrical Characteristics VBIAS VS1,2,3 COM, 25°C 1000 unless otherwise specified.
Symbol
Definition
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time ENABLE output shutdown propagation delay ITRIP output shutdown propagation delay ITRIP blanking time ITRIP FAULT propagation delay Input filter time (HIN, LIN) Enable input filter time Deadtime Ton, matching time channels) matching (Hi->Lo Lo->Hi channels) pulse width distortion (pwin-pwout) FAULT clear time RCIN:
1.65
Units
1000
Test Conditions
tITRIP tFLT tFILIN tfilterEn tFLTCLR
VIN, VITRIP VITRIP External dead time >450 nsec input VITRIP
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HIN1,2,3 LIN1,2,3
ITRIP FAULT RCIN
HO1,2,3 LO1,2,3
Fig. Input/Output Timing Diagram
LIN1,2,3 HIN1,2,
PWIN
HO1,2,3 LO1,2,3
HO1,2,3 LO1,2,3
Fig. Switching Time Waveforms
Fig. Output Enable Timing Waveform
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Fig. Internal Deadtime Timing Waveforms
ITRIP
uput
tflt
tfltclr
titrip
Fig. ITRIP/RCIN Timing Waveforms
tin,fi
tin,fi
HIN/LI
high
Fig. Input Filter Function
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Lead Definitions
Symbol
HIN1,2,3 LIN1,2,3 FAULT ITRIP RCIN VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 side supply voltage Logic ground Logic inputs high side gate driver outputs (HO1,2,3), phase Logic input side gate driver outputs (LO1,2,3), phase Indicates over-current (ITRIP) low-side undervoltage lockout occurred. Negative logic, open-drain output Logic input enable functionality. Positive logic, i.e. logic functions When ENABLE high. effect FAULT latched Analog input overcurrent shutdown. When active, ITRIP shuts down outputs activates FAULT RCIN low. When ITRIP becomes inactive, FAULT stays active externally time TFLTCLR, then automatically becomes inactive (open-drain high impedance). External network input used define FAULT CLEAR delay, TFLTCLR, approximately equal R*C. When RCIN FAULT goes back into open-drain high-impedance side gate drivers return High side floating supply High side gate driver outputs High voltage floating supply return side gate driver outputs
Description
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Functional Block Diagram
<UVCC
<UVBS
ITRIP
>VITRIP
ENAB
FAULT
(note high high (note high
LO1,2,3
LIN1,2,3 LIN1,2,3
HO1,2,3
HIN1,2,3
Note shoot-through prevention logic prevents LO1,2,3 HO1,2,3 each channel from turning simultaneously. Note UVCC latched, when UVCC, FAULT return high impedance. Note When ITRIP <VITRIP, FAULT returns high-impedance after RCIN becomes greater than
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Parameter Temperature Trends
Figures 7-39 provide information experimental performance IR21364 HVIC. line plotted each figure generated from actual data. small number individual samples were tested three temperatures (-40 order generate experimental (Exp.) curve. line labeled Exp. consist three data points (one data point each tested temperatures) that have been connected together illustrate understood temperature trend. individual data points curve were determined calculating averaged experimental value parameter (for given temperature).
Exp.
1000
tOFF (ns)
(ns)
Exp.
Temperature (oC)
Temperature (oC)
Fig. (Ton_Ls1 Turn-on Propagation Delay Temperature
Fig. (Toff_Ls1) Turn-off Propagation Delay Temperature
Exp.
tOFF (ns)
Exp.
(ns)
Temperature (oC)
Temperature (oC)
Fig. (Ton_Hs11) Turn-on Propagation Delay Temperature
Fig. (Toff_Hs21) Turn-off Propagation Delay Temperature
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(ns)
(ns)
Exp.
Exp.
Temperature (oC)
Temperature (oC)
Fig. Turn-on Rise Time Temperature
Fig. Turn-off Fall Time Temperature
Exp.
(ns)
(ns)
Exp.
Temperature (oC)
Temperature (oC)
Fig. Ton, matching time Temperature
Fig. matching time Temperature
1000
Exp.
tITRIP (ns)
(ns)
Exp.
Temperature (oC)
Temperature (oC)
Fig. Pulse Width Distortion Temperature
Fig. ITRIP Output Shutdown Propagation Delay Temperature
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1200 1000
Exp.
1000
DLTon1 (ns)
(nS)
Exp.
Temperature (oC)
Temperature (oC)
Fig. Dead Time Temperature
Figure Output Shutdown Time Temperature
1000
tFLT (ns)
Exp.
TFLTCLR (mS)
Exp.
Temperature (oC)
Temperature (oC)
Fig. ITRIP FAULT Indication Delay Temperature
Fig. FAULT Clear Time Temperature
LIN1_VTH+
LIN1_VTH-
Exp.
Exp.
Temperature (oC)
Temperature (oC)
Fig. Input Positive Going Threshold Temperature
Fig. Input Negative Going Threshold Temperature
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VIT,TH- (mV)
VIT,TH+ (mV)
EXP.
Exp.
Temperature (oC)
Temperature (oC)
Fig. ITRIP Input Positive Going Threshold Temperature
Fig. ITRIP Input Negative Going Threshold Temperature
1600
1200
Exp.
VOH_LO1 (mV)
VOL_LO1 (mV)
Exp.
Temperature (oC)
Temperature (oC)
Fig. Level Output Voltage Temperature
Fig. High Level Output Voltage Temperature
ileak1 (µA)
RON,FLT
Exp.
Exp.
Temperature
Temperature (oC)
Fig. FAULT On-Resistance Temperature
Fig. Offset Supply Leakage Current Temperature
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IQCC1 (mA)
IQCC0 (mA)
Exp.
Exp.
Temperature (oC)
Temperature (oC)
Fig. Quiescent Supply Current Temperature
Fig. Quiescent Supply Current Temperature
IQBS10
IQBS11
Exp.
Exp.
Temperature (oC)
Temperature (oC)
Fig. Quiescent Supply Current Temperature
15.0
Fig. Quiescent Supply Current Temperature
18.0
12.0
Exp.
15.0
12.0
VCCUV-
VCCUV+
Exp.
Temperature (oC)
Temperature (oC)
Fig. Supply Undervoltage Negative Going Threshold Temperature
Fig. Supply Undervoltage Positive Going Threshold Temperature
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15.0
15.0
12.0
Exp.
12.0
Exp.
VBSUV+
VBSUV-
Temperature (oC)
Temperature (oC)
Fig. Supply Undervoltage Negative Going Threshold Temperature
-0.1
Exp.
Fig. Supply Undervoltage Positive Going Threshold Temperature
Exp.
(mA)
-0.2
(mA)
-0.3
-0.4
-0.5
Temperature (oC)
Temperature (oC)
Fig. Output High Short Circuit Pulsed Current Temperature
Fig. Output Short Circuit Pulsed Current Temperature
Vs1_RST_domin
Exp.
Temperature (oC)
Fig. Temperature
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Case Outlines
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LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 11.90 12.10 3.90 4.10 23.70 24.30 11.40 11.60 10.80 11.00 18.20 18.40 1.50 1.50 1.60
28SOICW Imperial 0.468 0.476 0.153 0.161 0.933 0.956 0.448 0.456 0.425 0.433 0.716 0.724 0.059 0.059 0.062
REEL DIMENSIONS 28SOICW Metric Imperial Code 329.60 330.25 12.976 13.001 20.95 21.45 0.824 0.844 12.80 13.20 0.503 0.519 1.95 2.45 0.767 0.096 98.00 102.00 3.858 4.015 30.40 1.196 26.50 29.10 1.04 1.145 24.40 26.40 0.96 1.039
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LOADED TAPE FEED DIRECTION
NOTE CONTROLLING ENSION
CARRIER TAPE DIMENSION Metric Code 23.90 24.10 3.90 4.10 31.70 32.30 14.10 14.30 17.90 18.10 17.90 18.10 2.00 1.50 1.60
44PLCC Imperial 0.94 0.948 0.153 0.161 1.248 1.271 0.555 0.562 0.704 0.712 0.704 0.712 0.078 0.059 0.062
REEL DIMENSIONS 44PLCC Metric Code 329.60 330.25 20.95 21.45 12.80 13.20 1.95 2.45 98.00 102.00 38.4 34.7 35.8 32.6 33.1
Imperial 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 1.511 1.366 1.409 1.283 1.303
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ORDER INFORMATION
28-Lead SOIC IR21364SPbF 44-Lead PLCC IR21364JPbF 28-Lead SOIC Tape Reel IR21364STRPbF 44-Lead PLCC Tape Reel IR21364JTRPbF
information provided this document believed accurate reliable. However, International Rectifier assumes responsibility consequences this information. International Rectifier assumes responsibility infringement patents other rights third parties which result from this information. license granted implication otherwise under patent patent rights International Rectifier. specifications mentioned this document subject change without notice. This document supersedes replaces information previously supplied.
technical support, please contact IR's Technical Assistance Center
WORLD HEADQUARTERS: Kansas St., Segundo, California 90245 Tel: (310) 252-7105
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IR21364(S&J)PBF 3-PHASE BRIDGE DRIVER Floating channel desig

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